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Author SHA1 Message Date
SalimTerryLi 6bb6eefc94 dts: add various dts for SpacemiT K1 based boards 2025-01-02 17:25:03 +08:00
12152 changed files with 301522 additions and 780138 deletions
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.azure-pipelines.yml
+78 -222
View File
@@ -2,44 +2,23 @@ variables:
windows_vm: windows-2022
ubuntu_vm: ubuntu-24.04
macos_vm: macOS-14
ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20251013-26Nov2025
# Ensure we do a shallow clone
Agent.Source.Git.ShallowFetchDepth: 1
ci_runner_image: trini/u-boot-gitlab-ci-runner:jammy-20240808-21Aug2024
# Add '-u 0' options for Azure pipelines, otherwise we get "permission
# denied" error when it tries to "useradd -m -u 1001 vsts_azpcontainer",
# since our $(ci_runner_image) user is not root.
container_option: -u 0
work_dir: /u
# We define all of these as variables so we can easily reference them twice
am33xx_kirkwood: "am33xx kirkwood"
amd: "amd xilinx zynq"
amlogic_bcm: "amlogic bcm -x mips"
atmel: "atmel"
engicam_renesas: "engicam renesas"
k3_32b: "k3 -x aarch64,phytec,toradex"
k3_64b: "k3 -x armv7,phytec,toradex"
kirkwood_mvebu: "kirkwood mvebu"
layerscape_vf610: "ls1 ls2 lx2 vf610 -x phytec,toradex"
m68k_remaining_mx_xtensa: "m68k imxrt mx xtensa -x mx6,aarch64"
mips_x86: "mips x86 -x mediatek"
mx6: "mx6 -x engicam,phytec,toradex"
imx8: "imx8 -x engicam,phytec,toradex"
imx9_arc_nios2_socfpga: "imx9 arc nios2 socfpga -x phytec,toradex"
phytec_toradex: "phytec toradex"
am33xx_kirkwood_ls1_mvebu_omap: "am33xx kirkwood ls1 mvebu omap -x siemens,freescale"
amlogic_bcm_boundary_engicam_siemens_technexion_oradex: "amlogic bcm boundary engicam siemens technexion toradex -x mips"
arm_nxp_minus_imx_and_at91: "at91 freescale -x powerpc,m68k,imx,mx"
imx: "mx imx -x boundary,engicam,technexion,toradex"
rk: "rk"
sunxi: "sunxi"
powerpc: "powerpc"
riscv_stm32: "riscv stm32 -x engicam,xilinx"
rk3399: "rk3399"
rk352x_rk358x: "rk352 rk358"
rk356x_rk357x: "rk356 rk357"
rk3xxx_rest: "rk30 rk31 rk32 rk33 -x rk3399,phytec"
sandbox_tegra: "tegra sandbox -x toradex"
samsung_omap_mediatek: "samsung omap mediatek"
sun4i_5i: "sun4i sun5i"
sun6i_sun7i: "sun6i sun7i"
sun8i: "sun8i"
sunxi_rest: "sunxi -x sun4i,sun5i,sun6i,sun7i,sun8i"
arm_catch_all: "arm -x aarch64,am33xx,atmel,bcm,ls,lx,imx,k3,kirkwood,mvebu,mx,omap,renesas,rk,samsung,socfpga,stm32,sunxi,tegra,vf610,xilinx,zynq"
aarch64_catch_all: "aarch64 -x amd,amlogic,bcm,engicam,imx,k3,ls,lx,mediatek,mvebu,renesas,rk,samsung,socfpga,stm32,sunxi,tegra,xilinx,zynq"
arm_catch_all: "arm -x aarch64,am33xx,at91,bcm,ls1,kirkwood,mvebu,omap,rk,siemens,mx,sunxi,technexion,toradex"
aarch64_catch_all: "aarch64 -x amlogic,bcm,engicam,imx,ls1,ls2,lx216,mvebu,rk,siemens,sunxi,toradex"
everything_but_arm_and_powerpc: "arc m68k microblaze mips nios2 riscv sandbox sh x86 xtensa -x arm,powerpc"
stages:
- stage: testsuites
@@ -110,10 +89,9 @@ stages:
options: $(container_option)
steps:
- script: |
set -e
python3 -m venv /tmp/venvhtml
virtualenv -p /usr/bin/python3 /tmp/venvhtml
. /tmp/venvhtml/bin/activate
pip install -r doc/sphinx/requirements.txt -r test/py/requirements.txt
pip install -r doc/sphinx/requirements.txt
make htmldocs KDOC_WERROR=1
make infodocs
@@ -153,23 +131,16 @@ stages:
git config --global user.email bmeng.cn@gmail.com
git config --global --add safe.directory $(work_dir)
export USER=azure
python3 -m venv /tmp/venv
virtualenv -p /usr/bin/python3 /tmp/venv
. /tmp/venv/bin/activate
pip install -r test/py/requirements.txt \
-r tools/binman/requirements.txt \
-r tools/buildman/requirements.txt \
-r tools/patman/requirements.txt \
-r tools/u_boot_pylib/requirements.txt
pip install -r test/py/requirements.txt
pip install -r tools/buildman/requirements.txt
export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only
export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
export PATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}
./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w --board tools-only
set -ex
export TOOLPATH="--toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools --toolpath /opt/coreboot"
./tools/binman/binman ${TOOLPATH} tool -f missing
./tools/binman/binman ${TOOLPATH} test
# Avoid "Permission denied: 'cov'" error by using a temporary file
COVERAGE_FILE=/tmp/.coverage ./tools/binman/binman ${TOOLPATH} test -T
./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test
./tools/buildman/buildman -t
./tools/dtoc/dtoc -t
./tools/patman/patman test
@@ -191,14 +162,9 @@ stages:
- script: |
git config --global --add safe.directory $(work_dir)
export USER=azure
python3 -m venv /tmp/venv
. /tmp/venv/bin/activate
pip install -r test/py/requirements.txt \
-r tools/binman/requirements.txt \
-r tools/buildman/requirements.txt \
-r tools/patman/requirements.txt \
-r tools/u_boot_pylib/requirements.txt \
asteval pylint==3.3.4 pyopenssl
pip install -r test/py/requirements.txt
pip install -r tools/buildman/requirements.txt
pip install asteval pylint==2.12.2 pyopenssl
export PATH=${PATH}:~/.local/bin
echo "[MASTER]" >> .pylintrc
echo "load-plugins=pylint.extensions.docparams" >> .pylintrc
@@ -209,6 +175,18 @@ stages:
export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
make pylint_err
- job: check_for_pre_schema_tags
displayName: 'Check for pre-schema driver model tags'
pool:
vmImage: $(ubuntu_vm)
container:
image: $(ci_runner_image)
options: $(container_option)
steps:
# If grep succeeds and finds a match the test fails as we should
# have no matches.
- script: git grep u-boot,dm- -- '*.dts*' && exit 1 || exit 0
- job: check_packing_of_python_tools
displayName: 'Check we can package the Python tools'
pool:
@@ -232,36 +210,16 @@ stages:
# First get the total number of boards
total=$(tools/buildman/buildman ${BMANARGS} | grep "Total boards to build for each commit" | cut -d ' ' -f 8)
# Now build up the list of what each job built.
built="$(tools/buildman/buildman ${BMANARGS} $(am33xx_kirkwood) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(amd) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(amlogic_bcm) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(atmel) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(engicam_renesas) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(k3_32b) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(k3_64b) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(kirkwood_mvebu) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(layerscape_vf610) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(m68k_remaining_mx_xtensa) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(mips_x86) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(mx6) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(imx8) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(imx9_arc_nios2_socfpga) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(phytec_toradex) | grep '^ ')"
built="$(tools/buildman/buildman ${BMANARGS} $(am33xx_kirkwood_ls1_mvebu_omap) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(amlogic_bcm_boundary_engicam_siemens_technexion_oradex) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(arm_nxp_minus_imx_and_at91) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(imx) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(rk) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(sunxi) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(powerpc) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(riscv_stm32) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(rk3399) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(rk352x_rk358x) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(rk356x_rk357x) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(rk3xxx_rest) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(sandbox_tegra) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(samsung_omap_mediatek) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(sun4i_5i) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(sun6i_sun7i) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(sun8i) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(sunxi_rest) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(arm_catch_all) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(aarch64_catch_all) | grep '^ ')"
built="$built $(tools/buildman/buildman ${BMANARGS} $(everything_but_arm_and_powerpc) | grep '^ ')"
# Finally see how many machines that is.
actual=$(tools/buildman/buildman ${BMANARGS} $built | grep "Total boards to build for each commit" | cut -d ' ' -f 8)
echo We would build a total of $actual out of $total platforms this CI run
@@ -280,18 +238,20 @@ stages:
# the below corresponds to .gitlab-ci.yml "before_script"
cd \${WORK_DIR}
git config --global --add safe.directory \${WORK_DIR}
git clone --depth=1 https://github.com/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
# qemu_arm64_lwip_defconfig is the same as qemu_arm64 but with NET_LWIP enabled.
# The test config and the boardenv file from qemu_arm64 can be re-used so create symlinks
ln -s conf.qemu_arm64 /tmp/uboot-test-hooks/bin/travis-ci/conf.qemu_arm64_lwip_na
ln -s conf.qemu_arm64_na /tmp/uboot-test-hooks/bin/travis-ci/conf.qemu_arm64_lwip_na
ln -s u_boot_boardenv_qemu_arm64_na.py /tmp/uboot-test-hooks/py/travis-ci/u_boot_boardenv_qemu_arm64_lwip_na.py
ln -s travis-ci /tmp/uboot-test-hooks/bin/\`hostname\`
ln -s travis-ci /tmp/uboot-test-hooks/py/\`hostname\`
if [[ "\${TEST_PY_BD}" == "qemu-riscv32_spl" ]] || [[ "\${TEST_PY_BD}" == "xilinx_mbv32_smode" ]]; then
grub-mkimage --prefix=\"\" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
grub-mkimage --prefix=\"\" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
if [[ "\${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
fi
if [[ "\${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "\${TEST_PY_BD}" == "sifive_unleashed" ]] || [[ "\${TEST_PY_BD}" == "xilinx_mbv64_smode" ]]; then
if [[ "\${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "\${TEST_PY_BD}" == "sifive_unleashed" ]]; then
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
fi
@@ -306,16 +266,10 @@ stages:
if [ -n "\${BUILD_ENV}" ]; then
export \${BUILD_ENV};
fi
python3 -m venv /tmp/venv
. /tmp/venv/bin/activate
pip install -r tools/binman/requirements.txt \
-r tools/buildman/requirements.txt \
-r test/py/requirements.txt \
-r tools/u_boot_pylib/requirements.txt \
pytest-azurepipelines
pip install -r tools/buildman/requirements.txt
tools/buildman/buildman -o \${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e --board \${TEST_PY_BD} \${OVERRIDE}
cp /opt/grub/grub_x86.efi \${UBOOT_TRAVIS_BUILD_DIR}/
cp /opt/grub/grub_x64.efi \${UBOOT_TRAVIS_BUILD_DIR}/
cp ~/grub_x86.efi \${UBOOT_TRAVIS_BUILD_DIR}/
cp ~/grub_x64.efi \${UBOOT_TRAVIS_BUILD_DIR}/
cp /opt/grub/grubriscv64.efi \${UBOOT_TRAVIS_BUILD_DIR}/grub_riscv64.efi
cp /opt/grub/grubaa64.efi \${UBOOT_TRAVIS_BUILD_DIR}/grub_arm64.efi
cp /opt/grub/grubarm.efi \${UBOOT_TRAVIS_BUILD_DIR}/grub_arm.efi
@@ -336,39 +290,15 @@ stages:
/opt/coreboot/cbfstool \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom remove -n fallback/payload;
/opt/coreboot/cbfstool \${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f \${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
fi
# If we have TF-A binaries, we need to use them.
tfa_dir=""
rm -f /tmp/fip.bin
rm -f /tmp/bl1.bin
if [[ -d /opt/tf-a/"\${TEST_PY_BD}\${TEST_PY_ID//--id /_}" ]]; then
tfa_dir="/opt/tf-a/\${TEST_PY_BD}\${TEST_PY_ID//--id /_}";
elif [[ -d /opt/tf-a/"\${TEST_PY_BD}" ]]; then
tfa_dir="/opt/tf-a/\${TEST_PY_BD}";
fi
if [[ -n "\$tfa_dir" ]]; then
cp "\$tfa_dir"/fip.bin "\$tfa_dir"/bl1.bin /tmp/;
fi
if [ -f /tmp/fip.bin ] && [ -f /tmp/bl1.bin ]; then
export fip=/tmp/fip.bin;
export bl1=/tmp/bl1.bin;
export PATH=/opt/Base_RevC_AEMvA_pkg/models/Linux64_GCC-9.3:\${PATH};
fi
virtualenv -p /usr/bin/python3 /tmp/venv
. /tmp/venv/bin/activate
pip install -r test/py/requirements.txt
pip install pytest-azurepipelines
export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:\${PATH}
export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci
python3 -m http.server 80 --directory "\${UBOOT_TRAVIS_BUILD_DIR}" > /dev/null 2>&1 &
HTTP_PID=\$!
sleep 1 # Give the server a moment to start
if ps -p \${HTTP_PID} > /dev/null; then
export HTTP_PID
else
unset HTTP_PID
fi
# "\${var:+"-k \$var"}" expands to "" if \$var is empty, "-k \$var" if not
./test/py/test.py -ra -o cache_dir="\$UBOOT_TRAVIS_BUILD_DIR"/.pytest_cache --bd \${TEST_PY_BD} \${TEST_PY_ID} \${TEST_PY_EXTRA} \${TEST_PY_TEST_SPEC:+"-k \${TEST_PY_TEST_SPEC}"} --build-dir "\$UBOOT_TRAVIS_BUILD_DIR" --report-dir "\$UBOOT_TRAVIS_BUILD_DIR" --junitxml=\$(System.DefaultWorkingDirectory)/results.xml
./test/py/test.py -ra -o cache_dir="\$UBOOT_TRAVIS_BUILD_DIR"/.pytest_cache --bd \${TEST_PY_BD} \${TEST_PY_ID} \${TEST_PY_TEST_SPEC:+"-k \${TEST_PY_TEST_SPEC}"} --build-dir "\$UBOOT_TRAVIS_BUILD_DIR" --report-dir "\$UBOOT_TRAVIS_BUILD_DIR" --junitxml=\$(System.DefaultWorkingDirectory)/results.xml
# the below corresponds to .gitlab-ci.yml "after_script"
if [[ -n "\${HTTP_PID}" ]]; then
kill \${HTTP_PID};
fi
rm -rf /tmp/uboot-test-hooks /tmp/venv
EOF
- task: CopyFiles@2
@@ -390,25 +320,22 @@ stages:
matrix:
sandbox:
TEST_PY_BD: "sandbox"
TEST_PY_EXTRA: "--timing"
sandbox_asan:
TEST_PY_BD: "sandbox"
OVERRIDE: "-a ASAN"
TEST_PY_TEST_SPEC: "version"
sandbox_clang:
TEST_PY_BD: "sandbox"
OVERRIDE: "-O clang-18"
OVERRIDE: "-O clang-17"
sandbox_clang_asan:
TEST_PY_BD: "sandbox"
OVERRIDE: "-O clang-18 -a ASAN"
OVERRIDE: "-O clang-17 -a ASAN"
TEST_PY_TEST_SPEC: "version"
sandbox64:
TEST_PY_BD: "sandbox64"
sandbox64_clang:
TEST_PY_BD: "sandbox64"
OVERRIDE: "-O clang-18"
sandbox64_lwip:
TEST_PY_BD: "sandbox64_lwip"
OVERRIDE: "-O clang-17"
sandbox_spl:
TEST_PY_BD: "sandbox_spl"
TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
@@ -483,16 +410,14 @@ stages:
TEST_PY_BD: "evb-ast2500"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep"
evb_ast2600:
TEST_PY_BD: "evb-ast2600"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep"
vexpress_ca9x4:
TEST_PY_BD: "vexpress_ca9x4"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep"
vexpress_fvp:
TEST_PY_BD: "vexpress_fvp"
TEST_PY_TEST_SPEC: "not sleep and not hostfs"
vexpress_fvp_bloblist:
TEST_PY_BD: "vexpress_fvp_bloblist"
TEST_PY_TEST_SPEC: "not sleep and not hostfs"
integratorcp_cm926ejs:
TEST_PY_BD: "integratorcp_cm926ejs"
TEST_PY_ID: "--id qemu"
@@ -506,10 +431,6 @@ stages:
qemu_arm64_lwip:
TEST_PY_BD: "qemu_arm64_lwip"
TEST_PY_TEST_SPEC: "test_net_dhcp or test_net_ping or test_net_tftpboot"
qemu_arm64_tfa_fw_handoff:
TEST_PY_BD: "qemu_arm64"
TEST_PY_ID: "--id fw_handoff_tfa_optee"
TEST_PY_TEST_SPEC: "test_fw_handoff"
qemu_arm_sbsa_ref:
TEST_PY_BD: "qemu-arm-sbsa"
TEST_PY_TEST_SPEC: "not sleep"
@@ -549,12 +470,6 @@ stages:
qemu_riscv64_spl:
TEST_PY_BD: "qemu-riscv64_spl"
TEST_PY_TEST_SPEC: "not sleep"
qemu_riscv64_smode:
TEST_PY_BD: "qemu-riscv64_smode"
TEST_PY_TEST_SPEC: "not sleep"
qemu_riscv64_smode_acpi:
TEST_PY_BD: "qemu-riscv64_smode_acpi"
TEST_PY_TEST_SPEC: "not sleep"
qemu_x86:
TEST_PY_BD: "qemu-x86"
TEST_PY_TEST_SPEC: "not sleep"
@@ -580,31 +495,14 @@ stages:
TEST_PY_BD: "r2dplus"
TEST_PY_ID: "--id tulip_qemu"
TEST_PY_TEST_SPEC: "not sleep"
# This is broken upsteam: https://gitlab.com/qemu-project/qemu/-/issues/2945
# sifive_unleashed_sdcard:
# TEST_PY_BD: "sifive_unleashed"
# TEST_PY_ID: "--id sdcard_qemu"
# TEST_PY_TEST_SPEC: "not sleep"
sifive_unleashed_sdcard:
TEST_PY_BD: "sifive_unleashed"
TEST_PY_ID: "--id sdcard_qemu"
TEST_PY_TEST_SPEC: "not sleep"
sifive_unleashed_spi-nor:
TEST_PY_BD: "sifive_unleashed"
TEST_PY_ID: "--id spi-nor_qemu"
TEST_PY_TEST_SPEC: "not sleep"
xilinx_mbv32:
TEST_PY_BD: "xilinx_mbv32"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep"
xilinx_mbv32_smode test.py:
TEST_PY_BD: "xilinx_mbv32_smode"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep"
xilinx_mbv64 test.py:
TEST_PY_BD: "xilinx_mbv64"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep"
xilinx_mbv64_smode test.py:
TEST_PY_BD: "xilinx_mbv64_smode"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep"
xilinx_zynq_virt:
TEST_PY_BD: "xilinx_zynq_virt"
TEST_PY_ID: "--id qemu"
@@ -613,7 +511,6 @@ stages:
TEST_PY_BD: "xilinx_versal_virt"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep"
OVERRIDE: "-a ~CONFIG_USB_DWC3"
xtfpga:
TEST_PY_BD: "xtfpga"
TEST_PY_ID: "--id qemu"
@@ -656,64 +553,26 @@ stages:
# We split the world up in to 10 jobs as we can have at most 10
# parallel jobs going on the free tier of Azure.
matrix:
am33xx_kirkwood:
BUILDMAN: $(am33xx_kirkwood)
amd:
BUILDMAN: $(amd)
amlogic_bcm:
BUILDMAN: $(amlogic_bcm)
atmel:
BUILDMAN: $(atmel)
engicam_renesas:
BUILDMAN: $(engicam_renesas)
k3_32b:
BUILDMAN: $(k3_32b)
k3_64b:
BUILDMAN: $(k3_64b)
kirkwood_mvebu:
BUILDMAN: $(kirkwood_mvebu)
layerscape_vf610:
BUILDMAN: $(layerscape_vf610)
m68k_remaining_mx_xtensa:
BUILDMAN: $(m68k_remaining_mx_xtensa)
mips_x86:
BUILDMAN: $(mips_x86)
mx6:
BUILDMAN: $(mx6)
imx8:
BUILDMAN: $(imx8)
imx9_arc_nios2_socfpga:
BUILDMAN: $(imx9_arc_nios2_socfpga)
phytec_toradex:
BUILDMAN: $(phytec_toradex)
am33xx_kirkwood_ls1_mvebu_omap:
BUILDMAN: $(am33xx_kirkwood_ls1_mvebu_omap)
amlogic_bcm_boundary_engicam_siemens_technexion_oradex:
BUILDMAN: $(amlogic_bcm_boundary_engicam_siemens_technexion_oradex)
arm_nxp_minus_imx_and_at91:
BUILDMAN: $(arm_nxp_minus_imx_and_at91)
imx:
BUILDMAN: $(imx)
rk:
BUILDMAN: $(rk)
sunxi:
BUILDMAN: $(sunxi)
powerpc:
BUILDMAN: $(powerpc)
riscv_stm32:
BUILDMAN: $(riscv_stm32)
rk3399:
BUILDMAN: $(rk3399)
rk352x_rk358x:
BUILDMAN: $(rk352x_rk358x)
rk356x_rk357x:
BUILDMAN: $(rk356x_rk357x)
rk3xxx_rest:
BUILDMAN: $(rk3xxx_rest)
sandbox_tegra:
BUILDMAN: $(sandbox_tegra)
samsung_omap_mediatek:
BUILDMAN: $(samsung_omap_mediatek)
sun4i_5i:
BUILDMAN: $(sun4i_5i)
sun6i_sun7i:
BUILDMAN: $(sun6i_sun7i)
sun8i:
BUILDMAN: $(sun8i)
sunxi_rest:
BUILDMAN: $(sunxi_rest)
arm_catch_all:
BUILDMAN: $(arm_catch_all)
aarch64_catch_all:
BUILDMAN: $(aarch64_catch_all)
everything_but_arm_and_powerpc:
BUILDMAN: $(everything_but_arm_and_powerpc)
steps:
- script: |
cat << EOF > build.sh
@@ -722,10 +581,7 @@ stages:
# make environment variables available as tests are running inside a container
export BUILDMAN="${BUILDMAN}"
git config --global --add safe.directory ${WORK_DIR}
python3 -m venv /tmp/venv
. /tmp/venv/bin/activate
pip install -r tools/binman/requirements.txt \
-r tools/buildman/requirements.txt
pip install -r tools/buildman/requirements.txt
EOF
cat << "EOF" >> build.sh
if [[ "${BUILDMAN}" != "" ]]; then
.b4-config
-6
View File
@@ -1,6 +0,0 @@
# Configuration for the `b4` tool
# See https://b4.docs.kernel.org/en/latest/config.html
[b4]
send-auto-to-cmd = scripts/get_maintainer.pl --nogit --nogit-fallback --nogit-chief-penguins --norolestats --nom
send-auto-cc-cmd = scripts/get_maintainer.pl --nogit-fallback --nogit-chief-penguins --norolestats --nol
.checkpatch.conf
-3
View File
@@ -19,9 +19,6 @@
# Not Linux, so we don't recommend usleep_range() over udelay()
--ignore USLEEP_RANGE
# We also do not have a functionally different mdelay() and udelay()
--ignore LONG_UDELAY
# Ignore networking block comment style
--ignore NETWORKING_BLOCK_COMMENT_STYLE
.clang-format
-804
View File
@@ -1,804 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
#
# clang-format configuration file. Intended for clang-format >= 11.
#
# For more information, see:
#
# Documentation/dev-tools/clang-format.rst
# https://clang.llvm.org/docs/ClangFormat.html
# https://clang.llvm.org/docs/ClangFormatStyleOptions.html
#
---
AccessModifierOffset: -4
AlignAfterOpenBracket: Align
AlignConsecutiveAssignments: false
AlignConsecutiveDeclarations: false
AlignEscapedNewlines: Left
AlignOperands: true
AlignTrailingComments: false
AllowAllParametersOfDeclarationOnNextLine: false
AllowShortBlocksOnASingleLine: false
AllowShortCaseLabelsOnASingleLine: false
AllowShortFunctionsOnASingleLine: None
AllowShortIfStatementsOnASingleLine: false
AllowShortLoopsOnASingleLine: false
AlwaysBreakAfterDefinitionReturnType: None
AlwaysBreakAfterReturnType: None
AlwaysBreakBeforeMultilineStrings: false
AlwaysBreakTemplateDeclarations: false
BinPackArguments: true
BinPackParameters: true
BraceWrapping:
AfterClass: false
AfterControlStatement: false
AfterEnum: false
AfterFunction: true
AfterNamespace: true
AfterObjCDeclaration: false
AfterStruct: false
AfterUnion: false
AfterExternBlock: false
BeforeCatch: false
BeforeElse: false
IndentBraces: false
SplitEmptyFunction: true
SplitEmptyRecord: true
SplitEmptyNamespace: true
BreakBeforeBinaryOperators: None
BreakBeforeBraces: Custom
BreakBeforeInheritanceComma: false
BreakBeforeTernaryOperators: false
BreakConstructorInitializersBeforeComma: false
BreakConstructorInitializers: BeforeComma
BreakAfterJavaFieldAnnotations: false
BreakStringLiterals: false
ColumnLimit: 80
CommentPragmas: '^ IWYU pragma:'
CompactNamespaces: false
ConstructorInitializerAllOnOneLineOrOnePerLine: false
ConstructorInitializerIndentWidth: 8
ContinuationIndentWidth: 8
Cpp11BracedListStyle: false
DerivePointerAlignment: false
DisableFormat: false
ExperimentalAutoDetectBinPacking: false
FixNamespaceComments: false
# Taken from:
# git grep -h '^#define [^[:space:]]*for_each[^[:space:]]*(' include/ tools/ \
# | sed "s,^#define \([^[:space:]]*for_each[^[:space:]]*\)(.*$, - '\1'," \
# | LC_ALL=C sort -u
ForEachMacros:
- '__ata_qc_for_each'
- '__bio_for_each_bvec'
- '__bio_for_each_segment'
- '__evlist__for_each_entry'
- '__evlist__for_each_entry_continue'
- '__evlist__for_each_entry_from'
- '__evlist__for_each_entry_reverse'
- '__evlist__for_each_entry_safe'
- '__for_each_mem_range'
- '__for_each_mem_range_rev'
- '__for_each_thread'
- '__hlist_for_each_rcu'
- '__map__for_each_symbol_by_name'
- '__pci_bus_for_each_res0'
- '__pci_bus_for_each_res1'
- '__pci_dev_for_each_res0'
- '__pci_dev_for_each_res1'
- '__perf_evlist__for_each_entry'
- '__perf_evlist__for_each_entry_reverse'
- '__perf_evlist__for_each_entry_safe'
- '__rq_for_each_bio'
- '__shost_for_each_device'
- '__sym_for_each'
- '_for_each_counter'
- 'apei_estatus_for_each_section'
- 'ata_for_each_dev'
- 'ata_for_each_link'
- 'ata_qc_for_each'
- 'ata_qc_for_each_raw'
- 'ata_qc_for_each_with_internal'
- 'ax25_for_each'
- 'ax25_uid_for_each'
- 'bio_for_each_bvec'
- 'bio_for_each_bvec_all'
- 'bio_for_each_folio_all'
- 'bio_for_each_integrity_vec'
- 'bio_for_each_segment'
- 'bio_for_each_segment_all'
- 'bio_list_for_each'
- 'bip_for_each_vec'
- 'bond_for_each_slave'
- 'bond_for_each_slave_rcu'
- 'bpf_for_each'
- 'bpf_for_each_reg_in_vstate'
- 'bpf_for_each_reg_in_vstate_mask'
- 'bpf_for_each_spilled_reg'
- 'bpf_object__for_each_map'
- 'bpf_object__for_each_program'
- 'btree_for_each_safe128'
- 'btree_for_each_safe32'
- 'btree_for_each_safe64'
- 'btree_for_each_safel'
- 'card_for_each_dev'
- 'cgroup_taskset_for_each'
- 'cgroup_taskset_for_each_leader'
- 'cpu_aggr_map__for_each_idx'
- 'cpufreq_for_each_efficient_entry_idx'
- 'cpufreq_for_each_entry'
- 'cpufreq_for_each_entry_idx'
- 'cpufreq_for_each_valid_entry'
- 'cpufreq_for_each_valid_entry_idx'
- 'css_for_each_child'
- 'css_for_each_descendant_post'
- 'css_for_each_descendant_pre'
- 'damon_for_each_region'
- 'damon_for_each_region_from'
- 'damon_for_each_region_safe'
- 'damon_for_each_scheme'
- 'damon_for_each_scheme_safe'
- 'damon_for_each_target'
- 'damon_for_each_target_safe'
- 'damos_for_each_filter'
- 'damos_for_each_filter_safe'
- 'damos_for_each_ops_filter'
- 'damos_for_each_ops_filter_safe'
- 'damos_for_each_quota_goal'
- 'damos_for_each_quota_goal_safe'
- 'data__for_each_file'
- 'data__for_each_file_new'
- 'data__for_each_file_start'
- 'def_for_each_cpu'
- 'device_for_each_child_node'
- 'device_for_each_child_node_scoped'
- 'dma_fence_array_for_each'
- 'dma_fence_chain_for_each'
- 'dma_fence_unwrap_for_each'
- 'dma_resv_for_each_fence'
- 'dma_resv_for_each_fence_unlocked'
- 'do_for_each_ftrace_op'
- 'drm_atomic_crtc_for_each_plane'
- 'drm_atomic_crtc_state_for_each_plane'
- 'drm_atomic_crtc_state_for_each_plane_state'
- 'drm_atomic_for_each_plane_damage'
- 'drm_client_for_each_connector_iter'
- 'drm_client_for_each_modeset'
- 'drm_connector_for_each_possible_encoder'
- 'drm_exec_for_each_locked_object'
- 'drm_exec_for_each_locked_object_reverse'
- 'drm_for_each_bridge_in_chain'
- 'drm_for_each_connector_iter'
- 'drm_for_each_crtc'
- 'drm_for_each_crtc_reverse'
- 'drm_for_each_encoder'
- 'drm_for_each_encoder_mask'
- 'drm_for_each_fb'
- 'drm_for_each_legacy_plane'
- 'drm_for_each_plane'
- 'drm_for_each_plane_mask'
- 'drm_for_each_privobj'
- 'drm_gem_for_each_gpuvm_bo'
- 'drm_gem_for_each_gpuvm_bo_safe'
- 'drm_gpusvm_for_each_range'
- 'drm_gpuva_for_each_op'
- 'drm_gpuva_for_each_op_from_reverse'
- 'drm_gpuva_for_each_op_reverse'
- 'drm_gpuva_for_each_op_safe'
- 'drm_gpuvm_bo_for_each_va'
- 'drm_gpuvm_bo_for_each_va_safe'
- 'drm_gpuvm_for_each_va'
- 'drm_gpuvm_for_each_va_range'
- 'drm_gpuvm_for_each_va_range_safe'
- 'drm_gpuvm_for_each_va_safe'
- 'drm_mm_for_each_hole'
- 'drm_mm_for_each_node'
- 'drm_mm_for_each_node_in_range'
- 'drm_mm_for_each_node_safe'
- 'dsa_switch_for_each_available_port'
- 'dsa_switch_for_each_cpu_port'
- 'dsa_switch_for_each_cpu_port_continue_reverse'
- 'dsa_switch_for_each_port'
- 'dsa_switch_for_each_port_continue_reverse'
- 'dsa_switch_for_each_port_safe'
- 'dsa_switch_for_each_user_port'
- 'dsa_switch_for_each_user_port_continue_reverse'
- 'dsa_tree_for_each_cpu_port'
- 'dsa_tree_for_each_user_port'
- 'dsa_tree_for_each_user_port_continue_reverse'
- 'dso__for_each_symbol'
- 'elf_hash_for_each_possible'
- 'elf_symtab__for_each_symbol'
- 'evlist__for_each_cpu'
- 'evlist__for_each_entry'
- 'evlist__for_each_entry_continue'
- 'evlist__for_each_entry_from'
- 'evlist__for_each_entry_reverse'
- 'evlist__for_each_entry_safe'
- 'flow_action_for_each'
- 'for_each_acpi_consumer_dev'
- 'for_each_acpi_dev_match'
- 'for_each_active_dev_scope'
- 'for_each_active_drhd_unit'
- 'for_each_active_iommu'
- 'for_each_active_irq'
- 'for_each_active_route'
- 'for_each_aggr_pgid'
- 'for_each_alloc_capable_rdt_resource'
- 'for_each_and_bit'
- 'for_each_andnot_bit'
- 'for_each_available_child_of_node'
- 'for_each_available_child_of_node_scoped'
- 'for_each_bench'
- 'for_each_bio'
- 'for_each_board_func_rsrc'
- 'for_each_btf_ext_rec'
- 'for_each_btf_ext_sec'
- 'for_each_bvec'
- 'for_each_capable_rdt_resource'
- 'for_each_card_auxs'
- 'for_each_card_auxs_safe'
- 'for_each_card_components'
- 'for_each_card_dapms'
- 'for_each_card_pre_auxs'
- 'for_each_card_prelinks'
- 'for_each_card_rtds'
- 'for_each_card_rtds_safe'
- 'for_each_card_widgets'
- 'for_each_card_widgets_safe'
- 'for_each_cgroup_storage_type'
- 'for_each_child_of_node'
- 'for_each_child_of_node_scoped'
- 'for_each_child_of_node_with_prefix'
- 'for_each_clear_bit'
- 'for_each_clear_bit_from'
- 'for_each_clear_bitrange'
- 'for_each_clear_bitrange_from'
- 'for_each_cmd'
- 'for_each_cmsghdr'
- 'for_each_collection'
- 'for_each_comp_order'
- 'for_each_compatible_node'
- 'for_each_component_dais'
- 'for_each_component_dais_safe'
- 'for_each_conduit'
- 'for_each_console'
- 'for_each_console_srcu'
- 'for_each_cpu'
- 'for_each_cpu_and'
- 'for_each_cpu_andnot'
- 'for_each_cpu_from'
- 'for_each_cpu_or'
- 'for_each_cpu_wrap'
- 'for_each_dapm_widgets'
- 'for_each_dedup_cand'
- 'for_each_dev_addr'
- 'for_each_dev_scope'
- 'for_each_dma_cap_mask'
- 'for_each_dpcm_be'
- 'for_each_dpcm_be_rollback'
- 'for_each_dpcm_be_safe'
- 'for_each_dpcm_fe'
- 'for_each_drhd_unit'
- 'for_each_dss_dev'
- 'for_each_efi_memory_desc'
- 'for_each_efi_memory_desc_in_map'
- 'for_each_element'
- 'for_each_element_extid'
- 'for_each_element_id'
- 'for_each_enabled_cpu'
- 'for_each_endpoint_of_node'
- 'for_each_event'
- 'for_each_event_tps'
- 'for_each_evictable_lru'
- 'for_each_fib6_node_rt_rcu'
- 'for_each_fib6_walker_rt'
- 'for_each_file_lock'
- 'for_each_free_mem_pfn_range_in_zone_from'
- 'for_each_free_mem_range'
- 'for_each_free_mem_range_reverse'
- 'for_each_func_rsrc'
- 'for_each_gpiochip_node'
- 'for_each_group_evsel'
- 'for_each_group_evsel_head'
- 'for_each_group_member'
- 'for_each_group_member_head'
- 'for_each_hstate'
- 'for_each_hwgpio'
- 'for_each_hwgpio_in_range'
- 'for_each_if'
- 'for_each_inject_fn'
- 'for_each_insn'
- 'for_each_insn_op_loc'
- 'for_each_insn_prefix'
- 'for_each_intid'
- 'for_each_iommu'
- 'for_each_ip_tunnel_rcu'
- 'for_each_irq_desc'
- 'for_each_irq_nr'
- 'for_each_lang'
- 'for_each_link_ch_maps'
- 'for_each_link_codecs'
- 'for_each_link_cpus'
- 'for_each_link_platforms'
- 'for_each_lru'
- 'for_each_matching_node'
- 'for_each_matching_node_and_match'
- 'for_each_media_entity_data_link'
- 'for_each_mem_pfn_range'
- 'for_each_mem_range'
- 'for_each_mem_range_rev'
- 'for_each_mem_region'
- 'for_each_member'
- 'for_each_memory'
- 'for_each_migratetype_order'
- 'for_each_missing_reg'
- 'for_each_mle_subelement'
- 'for_each_mod_mem_type'
- 'for_each_mon_capable_rdt_resource'
- 'for_each_mp_bvec'
- 'for_each_net'
- 'for_each_net_continue_reverse'
- 'for_each_net_rcu'
- 'for_each_netdev'
- 'for_each_netdev_continue'
- 'for_each_netdev_continue_rcu'
- 'for_each_netdev_continue_reverse'
- 'for_each_netdev_dump'
- 'for_each_netdev_feature'
- 'for_each_netdev_in_bond_rcu'
- 'for_each_netdev_rcu'
- 'for_each_netdev_reverse'
- 'for_each_netdev_safe'
- 'for_each_new_connector_in_state'
- 'for_each_new_crtc_in_state'
- 'for_each_new_mst_mgr_in_state'
- 'for_each_new_plane_in_state'
- 'for_each_new_plane_in_state_reverse'
- 'for_each_new_private_obj_in_state'
- 'for_each_new_reg'
- 'for_each_nhlt_endpoint'
- 'for_each_nhlt_endpoint_fmtcfg'
- 'for_each_nhlt_fmtcfg'
- 'for_each_node'
- 'for_each_node_by_name'
- 'for_each_node_by_type'
- 'for_each_node_mask'
- 'for_each_node_numadist'
- 'for_each_node_state'
- 'for_each_node_with_cpus'
- 'for_each_node_with_property'
- 'for_each_nonreserved_multicast_dest_pgid'
- 'for_each_numa_hop_mask'
- 'for_each_of_allnodes'
- 'for_each_of_allnodes_from'
- 'for_each_of_cpu_node'
- 'for_each_of_graph_port'
- 'for_each_of_graph_port_endpoint'
- 'for_each_of_pci_range'
- 'for_each_old_connector_in_state'
- 'for_each_old_crtc_in_state'
- 'for_each_old_mst_mgr_in_state'
- 'for_each_old_plane_in_state'
- 'for_each_old_private_obj_in_state'
- 'for_each_oldnew_connector_in_state'
- 'for_each_oldnew_crtc_in_state'
- 'for_each_oldnew_mst_mgr_in_state'
- 'for_each_oldnew_plane_in_state'
- 'for_each_oldnew_plane_in_state_reverse'
- 'for_each_oldnew_private_obj_in_state'
- 'for_each_online_cpu'
- 'for_each_online_cpu_wrap'
- 'for_each_online_node'
- 'for_each_online_pgdat'
- 'for_each_or_bit'
- 'for_each_page_ext'
- 'for_each_path'
- 'for_each_pci_bridge'
- 'for_each_pci_dev'
- 'for_each_pcm_streams'
- 'for_each_physmem_range'
- 'for_each_populated_zone'
- 'for_each_possible_cpu'
- 'for_each_possible_cpu_wrap'
- 'for_each_present_blessed_reg'
- 'for_each_present_cpu'
- 'for_each_present_section_nr'
- 'for_each_prime_number'
- 'for_each_prime_number_from'
- 'for_each_probe_cache_entry'
- 'for_each_process'
- 'for_each_process_thread'
- 'for_each_prop_codec_conf'
- 'for_each_prop_dai_codec'
- 'for_each_prop_dai_cpu'
- 'for_each_prop_dlc_codecs'
- 'for_each_prop_dlc_cpus'
- 'for_each_prop_dlc_platforms'
- 'for_each_property_of_node'
- 'for_each_rdt_resource'
- 'for_each_reg'
- 'for_each_reg_filtered'
- 'for_each_reloc'
- 'for_each_reloc_from'
- 'for_each_requested_gpio'
- 'for_each_requested_gpio_in_range'
- 'for_each_reserved_child_of_node'
- 'for_each_reserved_mem_range'
- 'for_each_reserved_mem_region'
- 'for_each_rtd_ch_maps'
- 'for_each_rtd_codec_dais'
- 'for_each_rtd_components'
- 'for_each_rtd_cpu_dais'
- 'for_each_rtd_dais'
- 'for_each_rtd_dais_reverse'
- 'for_each_sband_iftype_data'
- 'for_each_script'
- 'for_each_sec'
- 'for_each_set_bit'
- 'for_each_set_bit_from'
- 'for_each_set_bit_wrap'
- 'for_each_set_bitrange'
- 'for_each_set_bitrange_from'
- 'for_each_set_clump8'
- 'for_each_sg'
- 'for_each_sg_dma_page'
- 'for_each_sg_page'
- 'for_each_sgtable_dma_page'
- 'for_each_sgtable_dma_sg'
- 'for_each_sgtable_page'
- 'for_each_sgtable_sg'
- 'for_each_sibling_event'
- 'for_each_sta_active_link'
- 'for_each_subelement'
- 'for_each_subelement_extid'
- 'for_each_subelement_id'
- 'for_each_sublist'
- 'for_each_subsystem'
- 'for_each_suite'
- 'for_each_supported_activate_fn'
- 'for_each_supported_inject_fn'
- 'for_each_sym'
- 'for_each_thread'
- 'for_each_token'
- 'for_each_unicast_dest_pgid'
- 'for_each_valid_link'
- 'for_each_vif_active_link'
- 'for_each_vma'
- 'for_each_vma_range'
- 'for_each_vsi'
- 'for_each_wakeup_source'
- 'for_each_zone'
- 'for_each_zone_zonelist'
- 'for_each_zone_zonelist_nodemask'
- 'func_for_each_insn'
- 'fwnode_for_each_available_child_node'
- 'fwnode_for_each_child_node'
- 'fwnode_for_each_parent_node'
- 'fwnode_graph_for_each_endpoint'
- 'gadget_for_each_ep'
- 'genradix_for_each'
- 'genradix_for_each_from'
- 'genradix_for_each_reverse'
- 'hash_for_each'
- 'hash_for_each_possible'
- 'hash_for_each_possible_rcu'
- 'hash_for_each_possible_rcu_notrace'
- 'hash_for_each_possible_safe'
- 'hash_for_each_rcu'
- 'hash_for_each_safe'
- 'hashmap__for_each_entry'
- 'hashmap__for_each_entry_safe'
- 'hashmap__for_each_key_entry'
- 'hashmap__for_each_key_entry_safe'
- 'hctx_for_each_ctx'
- 'hists__for_each_format'
- 'hists__for_each_sort_list'
- 'hlist_bl_for_each_entry'
- 'hlist_bl_for_each_entry_rcu'
- 'hlist_bl_for_each_entry_safe'
- 'hlist_for_each'
- 'hlist_for_each_entry'
- 'hlist_for_each_entry_continue'
- 'hlist_for_each_entry_continue_rcu'
- 'hlist_for_each_entry_continue_rcu_bh'
- 'hlist_for_each_entry_from'
- 'hlist_for_each_entry_from_rcu'
- 'hlist_for_each_entry_rcu'
- 'hlist_for_each_entry_rcu_bh'
- 'hlist_for_each_entry_rcu_notrace'
- 'hlist_for_each_entry_safe'
- 'hlist_for_each_entry_srcu'
- 'hlist_for_each_safe'
- 'hlist_nulls_for_each_entry'
- 'hlist_nulls_for_each_entry_from'
- 'hlist_nulls_for_each_entry_rcu'
- 'hlist_nulls_for_each_entry_safe'
- 'i3c_bus_for_each_i2cdev'
- 'i3c_bus_for_each_i3cdev'
- 'idr_for_each_entry'
- 'idr_for_each_entry_continue'
- 'idr_for_each_entry_continue_ul'
- 'idr_for_each_entry_ul'
- 'iio_for_each_active_channel'
- 'in_dev_for_each_ifa_rcu'
- 'in_dev_for_each_ifa_rtnl'
- 'in_dev_for_each_ifa_rtnl_net'
- 'inet_bind_bucket_for_each'
- 'interval_tree_for_each_span'
- 'intlist__for_each_entry'
- 'intlist__for_each_entry_safe'
- 'kcore_copy__for_each_phdr'
- 'key_for_each'
- 'key_for_each_safe'
- 'klp_for_each_func'
- 'klp_for_each_func_safe'
- 'klp_for_each_func_static'
- 'klp_for_each_object'
- 'klp_for_each_object_safe'
- 'klp_for_each_object_static'
- 'kunit_suite_for_each_test_case'
- 'kvm_for_each_memslot'
- 'kvm_for_each_memslot_in_gfn_range'
- 'kvm_for_each_vcpu'
- 'libbpf_nla_for_each_attr'
- 'list_for_each'
- 'list_for_each_codec'
- 'list_for_each_codec_safe'
- 'list_for_each_continue'
- 'list_for_each_entry'
- 'list_for_each_entry_continue'
- 'list_for_each_entry_continue_rcu'
- 'list_for_each_entry_continue_reverse'
- 'list_for_each_entry_from'
- 'list_for_each_entry_from_rcu'
- 'list_for_each_entry_from_reverse'
- 'list_for_each_entry_lockless'
- 'list_for_each_entry_rcu'
- 'list_for_each_entry_reverse'
- 'list_for_each_entry_safe'
- 'list_for_each_entry_safe_continue'
- 'list_for_each_entry_safe_from'
- 'list_for_each_entry_safe_reverse'
- 'list_for_each_entry_srcu'
- 'list_for_each_from'
- 'list_for_each_prev'
- 'list_for_each_prev_safe'
- 'list_for_each_rcu'
- 'list_for_each_safe'
- 'llist_for_each'
- 'llist_for_each_entry'
- 'llist_for_each_entry_safe'
- 'llist_for_each_safe'
- 'lwq_for_each_safe'
- 'map__for_each_symbol'
- 'map__for_each_symbol_by_name'
- 'mas_for_each'
- 'mas_for_each_rev'
- 'mci_for_each_dimm'
- 'media_device_for_each_entity'
- 'media_device_for_each_intf'
- 'media_device_for_each_link'
- 'media_device_for_each_pad'
- 'media_entity_for_each_pad'
- 'media_pipeline_for_each_entity'
- 'media_pipeline_for_each_pad'
- 'mlx5_lag_for_each_peer_mdev'
- 'mptcp_for_each_subflow'
- 'msi_domain_for_each_desc'
- 'msi_for_each_desc'
- 'mt_for_each'
- 'nanddev_io_for_each_block'
- 'nanddev_io_for_each_page'
- 'neigh_for_each_in_bucket'
- 'neigh_for_each_in_bucket_rcu'
- 'neigh_for_each_in_bucket_safe'
- 'netdev_for_each_lower_dev'
- 'netdev_for_each_lower_private'
- 'netdev_for_each_lower_private_rcu'
- 'netdev_for_each_mc_addr'
- 'netdev_for_each_synced_mc_addr'
- 'netdev_for_each_synced_uc_addr'
- 'netdev_for_each_uc_addr'
- 'netdev_for_each_upper_dev_rcu'
- 'netdev_hw_addr_list_for_each'
- 'nft_rule_for_each_expr'
- 'nla_for_each_attr'
- 'nla_for_each_attr_type'
- 'nla_for_each_nested'
- 'nla_for_each_nested_type'
- 'nlmsg_for_each_attr'
- 'nlmsg_for_each_msg'
- 'nr_neigh_for_each'
- 'nr_neigh_for_each_safe'
- 'nr_node_for_each'
- 'nr_node_for_each_safe'
- 'of_for_each_phandle'
- 'of_property_for_each_string'
- 'of_property_for_each_u32'
- 'pci_bus_for_each_resource'
- 'pci_dev_for_each_resource'
- 'pcl_for_each_chunk'
- 'pcl_for_each_segment'
- 'pcm_for_each_format'
- 'perf_config_items__for_each_entry'
- 'perf_config_sections__for_each_entry'
- 'perf_config_set__for_each_entry'
- 'perf_cpu_map__for_each_cpu'
- 'perf_cpu_map__for_each_cpu_skip_any'
- 'perf_cpu_map__for_each_idx'
- 'perf_evlist__for_each_entry'
- 'perf_evlist__for_each_entry_reverse'
- 'perf_evlist__for_each_entry_safe'
- 'perf_evlist__for_each_evsel'
- 'perf_evlist__for_each_mmap'
- 'perf_evsel_for_each_per_thread_period_safe'
- 'perf_hpp_list__for_each_format'
- 'perf_hpp_list__for_each_format_safe'
- 'perf_hpp_list__for_each_sort_list'
- 'perf_hpp_list__for_each_sort_list_safe'
- 'plist_for_each'
- 'plist_for_each_continue'
- 'plist_for_each_entry'
- 'plist_for_each_entry_continue'
- 'plist_for_each_entry_safe'
- 'plist_for_each_safe'
- 'pnp_for_each_card'
- 'pnp_for_each_dev'
- 'protocol_for_each_card'
- 'protocol_for_each_dev'
- 'queue_for_each_hw_ctx'
- 'radix_tree_for_each_slot'
- 'radix_tree_for_each_tagged'
- 'rb_for_each'
- 'rbtree_postorder_for_each_entry_safe'
- 'rdma_for_each_block'
- 'rdma_for_each_port'
- 'rdma_umem_for_each_dma_block'
- 'resource_list_for_each_entry'
- 'resource_list_for_each_entry_safe'
- 'rhl_for_each_entry_rcu'
- 'rhl_for_each_rcu'
- 'rht_for_each'
- 'rht_for_each_entry'
- 'rht_for_each_entry_from'
- 'rht_for_each_entry_rcu'
- 'rht_for_each_entry_rcu_from'
- 'rht_for_each_entry_safe'
- 'rht_for_each_from'
- 'rht_for_each_rcu'
- 'rht_for_each_rcu_from'
- 'rq_for_each_bvec'
- 'rq_for_each_segment'
- 'rq_list_for_each'
- 'rq_list_for_each_safe'
- 'sample_read_group__for_each'
- 'scsi_for_each_prot_sg'
- 'scsi_for_each_sg'
- 'sctp_for_each_hentry'
- 'sctp_skb_for_each'
- 'sec_for_each_insn'
- 'sec_for_each_insn_continue'
- 'sec_for_each_insn_from'
- 'sec_for_each_sym'
- 'shdma_for_each_chan'
- 'shost_for_each_device'
- 'sk_for_each'
- 'sk_for_each_bound'
- 'sk_for_each_bound_safe'
- 'sk_for_each_entry_offset_rcu'
- 'sk_for_each_from'
- 'sk_for_each_rcu'
- 'sk_for_each_safe'
- 'sk_nulls_for_each'
- 'sk_nulls_for_each_from'
- 'sk_nulls_for_each_rcu'
- 'snd_array_for_each'
- 'snd_pcm_group_for_each_entry'
- 'snd_soc_dapm_widget_for_each_path'
- 'snd_soc_dapm_widget_for_each_path_safe'
- 'snd_soc_dapm_widget_for_each_sink_path'
- 'snd_soc_dapm_widget_for_each_source_path'
- 'sparsebit_for_each_set_range'
- 'strlist__for_each_entry'
- 'strlist__for_each_entry_safe'
- 'sym_for_each_insn'
- 'sym_for_each_insn_continue_reverse'
- 'symbols__for_each_entry'
- 'tb_property_for_each'
- 'tcf_act_for_each_action'
- 'tcf_exts_for_each_action'
- 'test_suite__for_each_test_case'
- 'tool_pmu__for_each_event'
- 'ttm_bo_lru_for_each_reserved_guarded'
- 'ttm_resource_manager_for_each_res'
- 'udp_lrpa_for_each_entry_rcu'
- 'udp_portaddr_for_each_entry'
- 'udp_portaddr_for_each_entry_rcu'
- 'usb_hub_for_each_child'
- 'v4l2_device_for_each_subdev'
- 'v4l2_m2m_for_each_dst_buf'
- 'v4l2_m2m_for_each_dst_buf_safe'
- 'v4l2_m2m_for_each_src_buf'
- 'v4l2_m2m_for_each_src_buf_safe'
- 'virtio_device_for_each_vq'
- 'vkms_config_for_each_connector'
- 'vkms_config_for_each_crtc'
- 'vkms_config_for_each_encoder'
- 'vkms_config_for_each_plane'
- 'vkms_config_connector_for_each_possible_encoder'
- 'vkms_config_encoder_for_each_possible_crtc'
- 'vkms_config_plane_for_each_possible_crtc'
- 'while_for_each_ftrace_op'
- 'workloads__for_each'
- 'xa_for_each'
- 'xa_for_each_marked'
- 'xa_for_each_range'
- 'xa_for_each_start'
- 'xas_for_each'
- 'xas_for_each_conflict'
- 'xas_for_each_marked'
- 'xbc_array_for_each_value'
- 'xbc_for_each_key_value'
- 'xbc_node_for_each_array_value'
- 'xbc_node_for_each_child'
- 'xbc_node_for_each_key_value'
- 'xbc_node_for_each_subkey'
- 'ynl_attr_for_each'
- 'ynl_attr_for_each_nested'
- 'ynl_attr_for_each_payload'
- 'zorro_for_each_dev'
IncludeBlocks: Preserve
IncludeCategories:
- Regex: '.*'
Priority: 1
IncludeIsMainRegex: '(Test)?$'
IndentCaseLabels: false
IndentGotoLabels: false
IndentPPDirectives: None
IndentWidth: 8
IndentWrappedFunctionNames: false
JavaScriptQuotes: Leave
JavaScriptWrapImports: true
KeepEmptyLinesAtTheStartOfBlocks: false
MacroBlockBegin: ''
MacroBlockEnd: ''
MaxEmptyLinesToKeep: 1
NamespaceIndentation: None
ObjCBinPackProtocolList: Auto
ObjCBlockIndentWidth: 8
ObjCSpaceAfterProperty: true
ObjCSpaceBeforeProtocolList: true
# Taken from git's rules
PenaltyBreakAssignment: 10
PenaltyBreakBeforeFirstCallParameter: 30
PenaltyBreakComment: 10
PenaltyBreakFirstLessLess: 0
PenaltyBreakString: 10
PenaltyExcessCharacter: 100
PenaltyReturnTypeOnItsOwnLine: 60
PointerAlignment: Right
ReflowComments: false
SortIncludes: false
SortUsingDeclarations: false
SpaceAfterCStyleCast: false
SpaceAfterTemplateKeyword: true
SpaceBeforeAssignmentOperators: true
SpaceBeforeCtorInitializerColon: true
SpaceBeforeInheritanceColon: true
SpaceBeforeParens: ControlStatementsExceptForEachMacros
SpaceBeforeRangeBasedForLoopColon: true
SpaceInEmptyParentheses: false
SpacesBeforeTrailingComments: 1
SpacesInAngles: false
SpacesInContainerLiterals: false
SpacesInCStyleCastParentheses: false
SpacesInParentheses: false
SpacesInSquareBrackets: false
Standard: Cpp03
TabWidth: 8
UseTab: Always
...
.gitignore
+5 -10
View File
@@ -50,20 +50,17 @@ fit-dtb.blob*
/SPL*
/System.map
/boards.cfg
/mkimage*mkimage
/mkimage-in-simple-bin*
/simple-bin*
/u-boot*
/*.log
#
# We don't want to ignore the following even if they are dot-files
# git files that we don't want to ignore even it they are dot-files
#
!.clang-format
!.get_maintainer.*
!.gitattributes
!.gitignore
!.mailmap
!.get_maintainer.*
#
# Generated files
@@ -73,16 +70,14 @@ fit-dtb.blob*
/defconfig
/generated_defconfig
/Test*
/capsule*.efi-capsule
/capsule.*.efi-capsule
/capsule*.map
/keep-syms-lto.*
/*imx8mimage*
/*imx8mcst*
/*rcar4-sa0*
/drivers/video/u_boot_logo.S
/test/fdt_overlay/test-fdt-overlay-stacked.dtbo.S
/test/fdt_overlay/test-fdt-overlay.dtbo.S
capsule_esl_file
/test/overlay/test-fdt-overlay.dtbo.S
/test/overlay/test-fdt-overlay-stacked.dtbo.S
#
# Generated include files
.gitlab-ci.yml
+125 -222
View File
@@ -1,24 +1,17 @@
# SPDX-License-Identifier: GPL-2.0+
variables:
DEFAULT_ALL_TAG: "all"
DEFAULT_AMD64_TAG: "amd64"
DEFAULT_FAST_TAG: "fast"
DEFAULT_TAG: ""
MIRROR_DOCKER: docker.io
SJG_LAB: ""
PLATFORM: linux/amd64,linux/arm64
default:
tags:
- ${DEFAULT_ALL_TAG}
workflow:
rules:
- when: always
- ${DEFAULT_TAG}
# Grab our configured image. The source for this is found
# in the u-boot tree at tools/docker/Dockerfile
image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20251013-26Nov2025
image: ${MIRROR_DOCKER}/trini/u-boot-gitlab-ci-runner:jammy-20240808-21Aug2024
# We run some tests in different order, to catch some failures quicker.
stages:
@@ -30,22 +23,24 @@ stages:
.buildman_and_testpy_template: &buildman_and_testpy_dfn
stage: test.py
retry: 2 # QEMU may be too slow, etc.
needs: [ "Run binman, buildman, dtoc, Kconfig and patman testsuites" ]
rules:
- when: always
before_script:
# Clone uboot-test-hooks
- git config --global --add safe.directory "${CI_PROJECT_DIR}"
- git clone --depth=1 https://source.denx.de/u-boot/u-boot-test-hooks /tmp/uboot-test-hooks
# qemu_arm64_lwip_defconfig is the same as qemu_arm64 but with NET_LWIP enabled.
# The test config and the boardenv file from qemu_arm64 can be re-used so create symlinks
- ln -s conf.qemu_arm64 /tmp/uboot-test-hooks/bin/travis-ci/conf.qemu_arm64_lwip_na
- ln -s u_boot_boardenv_qemu_arm64_na.py /tmp/uboot-test-hooks/py/travis-ci/u_boot_boardenv_qemu_arm64_lwip_na.py
- ln -s conf.qemu_arm64_na /tmp/uboot-test-hooks/bin/travis-ci/conf.qemu_arm64_lwip_na
- ln -s travis-ci /tmp/uboot-test-hooks/bin/`hostname`
- ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
- if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]] || [[ "${TEST_PY_BD}" == "xilinx_mbv32_smode" ]]; then
- grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
- grub-mkimage --prefix="" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd
- if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin;
fi
- if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]] || [[ "${TEST_PY_BD}" == "xilinx_mbv64_smode" ]]; then
- if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then
wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.3.1/opensbi-1.3.1-rv-bin.tar.xz | tar -C /tmp -xJ;
export OPENSBI=/tmp/opensbi-1.3.1-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin;
fi
@@ -54,11 +49,6 @@ stages:
wget -O /tmp/fip.bin https://artifacts.codelinaro.org/artifactory/linaro-419-sbsa-ref/latest/tf-a/fip.bin;
export BINMAN_INDIRS=/tmp;
fi
# Prepare python environment
- python3 -m venv /tmp/venv;
. /tmp/venv/bin/activate;
pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
-r tools/buildman/requirements.txt -r tools/u_boot_pylib/requirements.txt
after_script:
- cp -v /tmp/${TEST_PY_BD}/*.{html,css,xml} .
@@ -72,8 +62,8 @@ stages:
fi
- tools/buildman/buildman -o ${UBOOT_TRAVIS_BUILD_DIR} -w -E -W -e
--board ${TEST_PY_BD} ${OVERRIDE}
- cp /opt/grub/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/
- cp /opt/grub/grub_x64.efi $UBOOT_TRAVIS_BUILD_DIR/
- cp ~/grub_x86.efi $UBOOT_TRAVIS_BUILD_DIR/
- cp ~/grub_x64.efi $UBOOT_TRAVIS_BUILD_DIR/
- cp /opt/grub/grubriscv64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_riscv64.efi
- cp /opt/grub/grubaa64.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm64.efi
- cp /opt/grub/grubarm.efi $UBOOT_TRAVIS_BUILD_DIR/grub_arm.efi
@@ -94,66 +84,73 @@ stages:
/opt/coreboot/cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom remove -n fallback/payload;
/opt/coreboot/cbfstool ${UBOOT_TRAVIS_BUILD_DIR}/coreboot.rom add-flat-binary -f ${UBOOT_TRAVIS_BUILD_DIR}/u-boot.bin -n fallback/payload -c LZMA -l 0x1110000 -e 0x1110000;
fi
# If we have TF-A binaries, we need to use them.
- tfa_dir=""
- rm -f /tmp/fip.bin
- rm -f /tmp/bl1.bin
- if [[ -d /opt/tf-a/"${TEST_PY_BD}${TEST_PY_ID//--id /_}" ]]; then
tfa_dir="/opt/tf-a/${TEST_PY_BD}${TEST_PY_ID//--id /_}";
elif [[ -d /opt/tf-a/"${TEST_PY_BD}" ]]; then
tfa_dir="/opt/tf-a/${TEST_PY_BD}";
fi
- if [[ -n "$tfa_dir" ]]; then
cp "$tfa_dir"/fip.bin "$tfa_dir"/bl1.bin /tmp/;
fi
- if [ -f /tmp/fip.bin ] && [ -f /tmp/bl1.bin ]; then
export fip=/tmp/fip.bin;
export bl1=/tmp/bl1.bin;
export PATH=/opt/Base_RevC_AEMvA_pkg/models/Linux64_GCC-9.3:${PATH};
fi
- virtualenv -p /usr/bin/python3 /tmp/venv
- . /tmp/venv/bin/activate
- pip install -r test/py/requirements.txt
# "${var:+"-k $var"}" expands to "" if $var is empty, "-k $var" if not
- export PATH=/opt/qemu/bin:/tmp/uboot-test-hooks/bin:${PATH};
export PYTHONPATH=/tmp/uboot-test-hooks/py/travis-ci;
python3 -m http.server 80 --directory "${UBOOT_TRAVIS_BUILD_DIR}" > /dev/null 2>&1 &
HTTP_PID=$!;
sleep 1;
if ps -p ${HTTP_PID} > /dev/null; then
export HTTP_PID;
else
unset HTTP_PID;
fi;
./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID} ${TEST_PY_EXTRA}
./test/py/test.py -ra --bd ${TEST_PY_BD} ${TEST_PY_ID}
${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"}
--build-dir "$UBOOT_TRAVIS_BUILD_DIR"
--junitxml=/tmp/${TEST_PY_BD}/results.xml;
if [[ -n "${HTTP_PID}" ]]; then
kill ${HTTP_PID};
fi
--junitxml=/tmp/${TEST_PY_BD}/results.xml
artifacts:
when: always
paths:
- "*.html"
- "*.css"
- results.xml
reports:
junit: results.xml
expire_in: 1 week
build all platforms in a single job:
.world_build:
stage: world build
dependencies: []
needs: [ "sandbox test.py" ]
tags:
- ${DEFAULT_FAST_TAG}
rules:
- when: always
build all 32bit ARM platforms:
extends: .world_build
script:
# Prepare python environment
- python3 -m venv /tmp/venv;
. /tmp/venv/bin/activate;
pip install -r tools/binman/requirements.txt
-r tools/buildman/requirements.txt
- ret=0;
git config --global --add safe.directory "${CI_PROJECT_DIR}";
./tools/buildman/buildman -o /tmp -PEWM -x xtensa || ret=$?;
pip install -r tools/buildman/requirements.txt;
./tools/buildman/buildman -o /tmp -PEWM arm -x aarch64 || ret=$?;
if [[ $ret -ne 0 ]]; then
./tools/buildman/buildman -o /tmp -seP;
exit $ret;
fi;
build all 64bit ARM platforms:
extends: .world_build
script:
- virtualenv -p /usr/bin/python3 /tmp/venv
- . /tmp/venv/bin/activate
- ret=0;
git config --global --add safe.directory "${CI_PROJECT_DIR}";
pip install -r tools/buildman/requirements.txt;
./tools/buildman/buildman -o /tmp -PEWM aarch64 || ret=$?;
if [[ $ret -ne 0 ]]; then
./tools/buildman/buildman -o /tmp -seP;
exit $ret;
fi;
build all PowerPC platforms:
extends: .world_build
script:
- ret=0;
git config --global --add safe.directory "${CI_PROJECT_DIR}";
./tools/buildman/buildman -o /tmp -P -E -W powerpc || ret=$?;
if [[ $ret -ne 0 ]]; then
./tools/buildman/buildman -o /tmp -seP;
exit $ret;
fi;
build all other platforms:
extends: .world_build
script:
- ret=0;
git config --global --add safe.directory "${CI_PROJECT_DIR}";
./tools/buildman/buildman -o /tmp -PEWM -x arm,powerpc || ret=$?;
if [[ $ret -ne 0 ]]; then
./tools/buildman/buildman -o /tmp -seP;
exit $ret;
@@ -161,6 +158,8 @@ build all platforms in a single job:
.testsuites:
stage: testsuites
rules:
- when: always
check for new CONFIG symbols outside Kconfig:
extends: .testsuites
@@ -178,9 +177,9 @@ check for new CONFIG symbols outside Kconfig:
docs:
extends: .testsuites
script:
- python3 -m venv /tmp/venvhtml
- virtualenv -p /usr/bin/python3 /tmp/venvhtml
- . /tmp/venvhtml/bin/activate
- pip install -r doc/sphinx/requirements.txt -r test/py/requirements.txt
- pip install -r doc/sphinx/requirements.txt
- make htmldocs KDOC_WERROR=1
- make infodocs
@@ -200,18 +199,15 @@ Build tools-only and envtools:
Run binman, buildman, dtoc, Kconfig and patman testsuites:
extends: .testsuites
tags:
- ${DEFAULT_AMD64_TAG}
script:
- git config --global user.name "GitLab CI Runner";
git config --global user.email trini@konsulko.com;
git config --global --add safe.directory "${CI_PROJECT_DIR}";
export USER=gitlab;
python3 -m venv /tmp/venv;
virtualenv -p /usr/bin/python3 /tmp/venv;
. /tmp/venv/bin/activate;
pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
-r tools/buildman/requirements.txt -r tools/patman/requirements.txt
-r tools/u_boot_pylib/requirements.txt;
pip install -r test/py/requirements.txt;
pip install -r tools/buildman/requirements.txt;
export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only;
export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt";
export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}";
@@ -219,10 +215,7 @@ Run binman, buildman, dtoc, Kconfig and patman testsuites:
./tools/buildman/buildman -T0 -o ${UBOOT_TRAVIS_BUILD_DIR} -w
--board tools-only;
set -e;
export TOOLPATH="--toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools --toolpath /opt/coreboot";
./tools/binman/binman ${TOOLPATH} tool -f missing;
./tools/binman/binman ${TOOLPATH} test;
./tools/binman/binman ${TOOLPATH} test -T;
./tools/binman/binman --toolpath ${UBOOT_TRAVIS_BUILD_DIR}/tools test;
./tools/buildman/buildman -t;
./tools/dtoc/dtoc -t;
./tools/patman/patman test;
@@ -233,11 +226,9 @@ Run pylint:
extends: .testsuites
script:
- git config --global --add safe.directory "${CI_PROJECT_DIR}"
- python3 -m venv /tmp/venv
- . /tmp/venv/bin/activate
- pip install -r test/py/requirements.txt -r tools/binman/requirements.txt
-r tools/buildman/requirements.txt -r tools/patman/requirements.txt
-r tools/u_boot_pylib/requirements.txt asteval pylint==3.3.4 pyopenssl
- pip install -r test/py/requirements.txt
- pip install -r tools/buildman/requirements.txt
- pip install asteval pylint==2.12.2 pyopenssl
- export PATH=${PATH}:~/.local/bin
- echo "[MASTER]" >> .pylintrc
- echo "load-plugins=pylint.extensions.docparams" >> .pylintrc
@@ -250,6 +241,15 @@ Run pylint:
- export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt"
- make pylint_err
# Check for pre-schema driver model tags
Check for pre-schema tags:
extends: .testsuites
script:
- git config --global --add safe.directory "${CI_PROJECT_DIR}";
# If grep succeeds and finds a match the test fails as we should
# have no matches.
- git grep u-boot,dm- -- '*.dts*' && exit 1 || exit 0
# Check we can package the Python tools
Check packing of Python tools:
extends: .testsuites
@@ -258,55 +258,25 @@ Check packing of Python tools:
# Test sandbox with test.py
sandbox test.py:
parallel:
matrix:
- HOST: "arm64"
- HOST: "amd64"
tags:
- ${HOST}
variables:
TEST_PY_BD: "sandbox"
TEST_PY_EXTRA: "--timing"
<<: *buildman_and_testpy_dfn
sandbox with clang test.py:
parallel:
matrix:
- HOST: "arm64"
- HOST: "amd64"
tags:
- ${HOST}
variables:
TEST_PY_BD: "sandbox"
OVERRIDE: "-O clang-18"
OVERRIDE: "-O clang-17"
<<: *buildman_and_testpy_dfn
sandbox64 test.py:
parallel:
matrix:
- HOST: "arm64"
- HOST: "amd64"
tags:
- ${HOST}
variables:
TEST_PY_BD: "sandbox64"
<<: *buildman_and_testpy_dfn
sandbox64 with clang test.py:
parallel:
matrix:
- HOST: "arm64"
- HOST: "amd64"
tags:
- ${HOST}
variables:
TEST_PY_BD: "sandbox64"
OVERRIDE: "-O clang-18"
<<: *buildman_and_testpy_dfn
sandbox64_lwip test.py:
variables:
TEST_PY_BD: "sandbox64_lwip"
OVERRIDE: "-O clang-17"
<<: *buildman_and_testpy_dfn
sandbox_spl test.py:
@@ -350,6 +320,13 @@ evb-ast2500 test.py:
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
evb-ast2600 test.py:
variables:
TEST_PY_BD: "evb-ast2600"
TEST_PY_TEST_SPEC: "not sleep"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
sandbox_flattree test.py:
variables:
TEST_PY_BD: "sandbox_flattree"
@@ -387,13 +364,6 @@ qemu_arm64_lwip test.py:
TEST_PY_TEST_SPEC: "test_net_dhcp or test_net_ping or test_net_tftpboot"
<<: *buildman_and_testpy_dfn
qemu_arm64_tfa_fw_handoff test.py:
variables:
TEST_PY_BD: "qemu_arm64"
TEST_PY_ID: "--id fw_handoff_tfa_optee"
TEST_PY_TEST_SPEC: "test_fw_handoff"
<<: *buildman_and_testpy_dfn
qemu_arm_sbsa test.py:
variables:
TEST_PY_BD: "qemu-arm-sbsa"
@@ -466,18 +436,6 @@ qemu-riscv64_spl test.py:
TEST_PY_TEST_SPEC: "not sleep"
<<: *buildman_and_testpy_dfn
qemu-riscv64_smode test.py:
variables:
TEST_PY_BD: "qemu-riscv64_smode"
TEST_PY_TEST_SPEC: "not sleep"
<<: *buildman_and_testpy_dfn
qemu-riscv64_smode_acpi test.py:
variables:
TEST_PY_BD: "qemu-riscv64_smode_acpi"
TEST_PY_TEST_SPEC: "not sleep"
<<: *buildman_and_testpy_dfn
qemu-x86 test.py:
variables:
TEST_PY_BD: "qemu-x86"
@@ -494,8 +452,6 @@ qemu-xtensa-dc233c test.py:
variables:
TEST_PY_BD: "qemu-xtensa-dc233c"
TEST_PY_TEST_SPEC: "not sleep and not efi"
tags:
- ${DEFAULT_AMD64_TAG}
<<: *buildman_and_testpy_dfn
r2dplus_i82557c test.py:
@@ -526,13 +482,12 @@ r2dplus_tulip test.py:
TEST_PY_ID: "--id tulip_qemu"
<<: *buildman_and_testpy_dfn
# This is broken upsteam: https://gitlab.com/qemu-project/qemu/-/issues/2945
#sifive_unleashed_sdcard test.py:
# variables:
# TEST_PY_BD: "sifive_unleashed"
# TEST_PY_TEST_SPEC: "not sleep"
# TEST_PY_ID: "--id sdcard_qemu"
# <<: *buildman_and_testpy_dfn
sifive_unleashed_sdcard test.py:
variables:
TEST_PY_BD: "sifive_unleashed"
TEST_PY_TEST_SPEC: "not sleep"
TEST_PY_ID: "--id sdcard_qemu"
<<: *buildman_and_testpy_dfn
sifive_unleashed_spi-nor test.py:
variables:
@@ -541,34 +496,6 @@ sifive_unleashed_spi-nor test.py:
TEST_PY_ID: "--id spi-nor_qemu"
<<: *buildman_and_testpy_dfn
xilinx_mbv32 test.py:
variables:
TEST_PY_BD: "xilinx_mbv32"
TEST_PY_TEST_SPEC: "not sleep"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
xilinx_mbv32_smode test.py:
variables:
TEST_PY_BD: "xilinx_mbv32_smode"
TEST_PY_TEST_SPEC: "not sleep"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
xilinx_mbv64 test.py:
variables:
TEST_PY_BD: "xilinx_mbv64"
TEST_PY_TEST_SPEC: "not sleep"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
xilinx_mbv64_smode test.py:
variables:
TEST_PY_BD: "xilinx_mbv64_smode"
TEST_PY_TEST_SPEC: "not sleep"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
xilinx_zynq_virt test.py:
variables:
TEST_PY_BD: "xilinx_zynq_virt"
@@ -581,7 +508,6 @@ xilinx_versal_virt test.py:
TEST_PY_BD: "xilinx_versal_virt"
TEST_PY_TEST_SPEC: "not sleep"
TEST_PY_ID: "--id qemu"
OVERRIDE: "-a ~CONFIG_USB_DWC3"
<<: *buildman_and_testpy_dfn
xtfpga test.py:
@@ -589,8 +515,6 @@ xtfpga test.py:
TEST_PY_BD: "xtfpga"
TEST_PY_TEST_SPEC: "not sleep"
TEST_PY_ID: "--id qemu"
tags:
- ${DEFAULT_AMD64_TAG}
<<: *buildman_and_testpy_dfn
coreboot test.py:
@@ -600,7 +524,7 @@ coreboot test.py:
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
.sjg_lab_template: &sjg_lab_dfn
.lab_template: &lab_dfn
stage: sjg-lab
rules:
- if: $SJG_LAB == "1"
@@ -608,10 +532,11 @@ coreboot test.py:
- if: $SJG_LAB != "1"
when: manual
allow_failure: true
dependencies: []
needs: [ "sandbox test.py" ]
tags: [ 'lab' ]
script:
- if [[ -z "${SJG_LAB}" ]]; then
exit 0;
fi
# Environment:
# SRC - source tree
# OUT - output directory for builds
@@ -626,10 +551,8 @@ coreboot test.py:
- export strategy="-s uboot -e off"
- export USE_LABGRID_SJG=1
# export verbose="-v"
- ${SRC}/test/py/test.py -ra --role ${ROLE} ${TEST_PY_EXTRA:-"--capture=tee-sys"}
--build-dir "${OUT}"
${TEST_PY_TEST_SPEC:+"-k ${TEST_PY_TEST_SPEC}"}
--junitxml=${OUT}/results.xml || ret=$?
- ${SRC}/test/py/test.py --role ${ROLE} --build-dir "${OUT}"
--capture=tee-sys -k "not bootstd" || ret=$?
- U_BOOT_BOARD_IDENTITY="${ROLE}" u-boot-test-release || true
- if [[ $ret -ne 0 ]]; then
exit $ret;
@@ -639,139 +562,119 @@ coreboot test.py:
paths:
- "build/${BOARD}/test-log.html"
- "build/${BOARD}/multiplexed_log.css"
- "build/${BOARD}/results.xml"
reports:
junit: "build/${BOARD}/results.xml"
expire_in: 1 week
rpi3:
variables:
ROLE: rpi3
<<: *sjg_lab_dfn
<<: *lab_dfn
opi_pc:
variables:
ROLE: opi_pc
<<: *sjg_lab_dfn
<<: *lab_dfn
pcduino3_nano:
variables:
ROLE: pcduino3_nano
<<: *sjg_lab_dfn
<<: *lab_dfn
samus:
variables:
ROLE: samus
<<: *sjg_lab_dfn
<<: *lab_dfn
link:
variables:
ROLE: link
<<: *sjg_lab_dfn
<<: *lab_dfn
jerry:
variables:
ROLE: jerry
<<: *sjg_lab_dfn
<<: *lab_dfn
minnowmax:
variables:
ROLE: minnowmax
<<: *sjg_lab_dfn
<<: *lab_dfn
opi_pc2:
variables:
ROLE: opi_pc2
<<: *sjg_lab_dfn
<<: *lab_dfn
bpi:
variables:
ROLE: bpi
<<: *sjg_lab_dfn
<<: *lab_dfn
rpi2:
variables:
ROLE: rpi2
<<: *sjg_lab_dfn
<<: *lab_dfn
bob:
variables:
ROLE: bob
<<: *sjg_lab_dfn
<<: *lab_dfn
ff3399:
variables:
ROLE: ff3399
<<: *sjg_lab_dfn
<<: *lab_dfn
coral:
variables:
ROLE: coral
<<: *sjg_lab_dfn
<<: *lab_dfn
rpi3z:
variables:
ROLE: rpi3z
<<: *sjg_lab_dfn
<<: *lab_dfn
bbb:
variables:
ROLE: bbb
<<: *sjg_lab_dfn
<<: *lab_dfn
kevin:
variables:
ROLE: kevin
<<: *sjg_lab_dfn
<<: *lab_dfn
pine64:
variables:
ROLE: pine64
<<: *sjg_lab_dfn
<<: *lab_dfn
c4:
variables:
ROLE: c4
<<: *sjg_lab_dfn
<<: *lab_dfn
rpi4:
variables:
ROLE: rpi4
<<: *sjg_lab_dfn
<<: *lab_dfn
rpi0:
variables:
ROLE: rpi0
<<: *sjg_lab_dfn
<<: *lab_dfn
snow:
variables:
ROLE: snow
<<: *sjg_lab_dfn
<<: *lab_dfn
pcduino3:
variables:
ROLE: pcduino3
<<: *sjg_lab_dfn
<<: *lab_dfn
nyan-big:
variables:
ROLE: nyan-big
<<: *sjg_lab_dfn
rpi:
variables:
ROLE: rpi
<<: *sjg_lab_dfn
# StarFive VisionFive 2
vf2:
variables:
ROLE: vf2
<<: *sjg_lab_dfn
qemu-x86_64:
variables:
ROLE: qemu-x86_64
TEST_PY_TEST_SPEC: "and not sleep"
<<: *sjg_lab_dfn
<<: *lab_dfn
.mailmap
+4 -27
View File
@@ -28,7 +28,6 @@ Anurag Kumar Vulisha <AnuragKumar.Vulisha@amd.com> <anurag.kumar.vulisha@xilinx.
Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com> <appana.durga.rao@xilinx.com>
Ashok Reddy Soma <ashok.reddy.soma@amd.com> <ashok.reddy.soma@xilinx.com>
Atish Patra <atishp@atishpatra.org> <atish.patra@wdc.com>
Bernhard Messerklinger <bernhard.messerklinger@at.abb.com> <bernhard.messerklinger@br-automation.com>
Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> <bharat.kumar.gogada@xilinx.com>
Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> <bharatku@xilinx.com>
Bhargava Sreekantappa Gayathri <bhargava.sreekantappa-gayathri@amd.com> <bhargava.sreekantappa-gayathri@xilinx.com>
@@ -36,25 +35,15 @@ Bhupesh Sharma <bhupesh.linux@gmail.com> <bhupesh.sharma@linaro.org>
Bin Meng <bmeng.cn@gmail.com> <bin.meng@windriver.com>
Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com>
Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com>
Casey Connolly <casey.connolly@linaro.org> <caleb.connolly@linaro.org>
Chen-Yu Tsai <wens@kernel.org> <wens@csie.org>
Christian Kohn <chris.kohn@amd.com> <christian.kohn@xilinx.com>
Christopher Obbard <christopher.obbard@linaro.org> <chris.obbard@collabora.com>
Dirk Behme <dirk.behme@googlemail.com>
<duje@dujemihanovic.xyz> <duje.mihanovic@skole.hr>
Durga Challa <durga.challa@amd.com> <vnsl.durga.challa@xilinx.com>
Eugen Hristev <eugen.hristev@linaro.org> <eugen.hristev@microchip.com>
Eugen Hristev <eugen.hristev@linaro.org> <eugen.hristev@collabora.com>
Fabio Estevam <fabio.estevam@nxp.com>
Greg Malysa <malysagreg@gmail.com> <greg.malysa@timesys.com>
Harini Katakam <harini.katakam@amd.com> <harini.katakam@xilinx.com>
Harsha <harsha.harsha@amd.com> <harsha.harsha@xilinx.com>
Heiko Stuebner <heiko.stuebner@cherry.de> <heiko.stuebner@theobroma-systems.com>
Heiko Schocher <hs@nabladev.com> <hs@denx.de>
Heiko Schocher <hs@nabladev.com> <hs@pollux.denx.de>
Heiko Schocher <hs@nabladev.com> <heiko.schocher@invitel.hu>
Heiko Schocher <hs@nabladev.com> <[hs@denx.de]>
Heiko Schocher <hs@nabladev.com> <hs@pollux.(none)>
Heinrich Schuchardt <xypron.glpk@gmx.de> <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt <xypron.glpk@gmx.de> xypron.glpk@gmx.de <xypron.glpk@gmx.de>
Ibai Erkiaga <ibai.erkiaga-elorza@amd.com> <ibai.erkiaga-elorza@xilinx.com>
@@ -69,14 +58,12 @@ Jagan Teki <jagannadha.sutradharudu-teki@xilinx.com>
Jakob Unterwurzacher <jakob.unterwurzacher@cherry.de> <jakob.unterwurzacher@theobroma-systems.com>
Jay Buddhabhatti <jay.buddhabhatti@amd.com> <jay.buddhabhatti@xilinx.com>
Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net>
Jerome Forissier <jerome@forissier.org> <jerome.forissier@linaro.org>
John Linn <john.linn@amd.com> <john.linn@xilinx.com>
Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyothee@xilinx.com>
Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <jyotheeswar.reddy.mutthareddyvari@xilinx.com>
Kalyani Akula <kalyani.akula@amd.com> <kalyani.akula@xilinx.com>
Klaus Goger <klaus.goger@cherry.de> <klaus.goger@theobroma-systems.com>
Masahisa Kojima <kojima.masahisa@socionext.com> <masahisa.kojima@linaro.org>
Linus Walleij <linusw@kernel.org> <linus.walleij@linaro.org>
Love Kumar <love.kumar@amd.com> <love.kumar@xilinx.com>
Lukasz Majewski <lukma@denx.de>
Marek Behún <kabel@kernel.org> <marek.behun@nic.cz>
@@ -87,7 +74,6 @@ Marek Vasut <marex@denx.de> <marex at denx.de>
Markus Klotzbuecher <mk@denx.de>
Masahiro Yamada <masahiroy@kernel.org> <yamada.masahiro@socionext.com>
Masahiro Yamada <masahiroy@kernel.org> <yamada.m@jp.panasonic.com>
Mattijs Korpershoek <mkorpershoek@kernel.org> <mkorpershoek@baylibre.com>
Michal Simek <michal.simek@amd.com> <Monstr@seznam.cz>
Michal Simek <michal.simek@amd.com> <michal.simek@xilinx.com>
Michal Simek <michal.simek@amd.com> <monstr@monstr.eu>
@@ -106,8 +92,7 @@ This contributor prefers not to receive mails <noreply@example.com> <pali.rohar@
Padmarao Begari <padmarao.begari@amd.com> <padmarao.begari@microchip.com>
Patrice Chotard <patrice.chotard@foss.st.com> <patrice.chotard@st.com>
Patrick Delaunay <patrick.delaunay@foss.st.com> <patrick.delaunay@st.com>
Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com>
Paul Burton <paulburton@kernel.org> <paul.burton@mips.com>
Paul Burton <paul.burton@mips.com> <paul.burton@imgtec.com>
Philipp Tomsich <philipp.tomsich@vrull.eu> <philipp.tomsich@theobroma-systems.com>
Piyush Mehta <piyush.mehta@amd.com> <piyush.mehta@xilinx.com>
Prabhakar Kushwaha <prabhakar@freescale.com>
@@ -117,7 +102,6 @@ Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> <radhey.shyam.pandey@xilinx.co
Rajeshwari Shinde <rajeshwari.s@samsung.com>
Raju Kumar Pothuraju <rajukumar.pothuraju@amd.com> <raju.kumar-pothuraju@xilinx.com>
Ravi Patel <ravi.patel@amd.com> <ravi.patel@xilinx.com>
Raymond Mao <raymondmaoca@gmail.com> <raymond.mao@linaro.org>
Ricardo Ribalda <ricardo@ribalda.com> <ricardo.ribalda@gmail.com>
Ricardo Ribalda <ricardo@ribalda.com> <ricardo.ribalda@uam.es>
Rohit Visavalia <rohit.visavalia@amd.com> <rohit.visavalia@xilinx.com>
@@ -125,8 +109,6 @@ Ruchika Gupta <ruchika.gupta@nxp.com> <ruchika.gupta@freescale.com>
Saeed Nowshadi <saeed.nowshadi@amd.com> <saeed.nowshadi@xilinx.com>
Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> <lakshmi.sai.krishna.potthuri@xilinx.com>
Sai Pavan Boddu <sai.pavan.boddu@amd.com> <sai.pavan.boddu@xilinx.com>
Sam Protsenko <semen.protsenko@linaro.org>
Sam Protsenko <semen.protsenko@linaro.org> <joe.skb7@gmail.com>
Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com> <sandeep.gundlupet-raju@xilinx.com>
Sandeep Paulraj <s-paulraj@ti.com>
Sandeep Reddy Ghanapuram <sandeep.reddy-ghanapuram@amd.com> <sandeep.reddy-ghanapuram@xilinx.com>
@@ -137,17 +119,14 @@ Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> <siva.durga.pala
Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com> <sivadur@xilinx.com>
Srinivas Goud <srinivas.goud@amd.com> <srinivas.goud@xilinx.com>
Srinivas Neeli <srinivas.neeli@amd.com> <srinivas.neeli@xilinx.com>
Stefan Roese <stefan.roese@mailbox.org> <stroese>
Stefano Babic <sbabic@nabladev.com>
Stefan Roese <sr@denx.de> <stroese>
Stefano Babic <sbabic@denx.de>
Stefano Stabellini <stefano.stabellini@amd.com> <stefano.stabellini@xilinx.com>
No generic patch CC mail please <noreply@example.com> <swarren@wwwdotorg.org>
No generic patch CC mail please <noreply@example.com> <swarren@nvidia.com>
Sumit Garg <sumit.garg@kernel.org> <sumit.garg@linaro.org>
Tom Rini <trini@konsulko.com> <trini@ti.com>
Tomas Thoresen <tomas.thoresen@amd.com> <tomast@xilinx.com>
TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Varalaxmi Bingi <varalaxmi.bingi@amd.com> <varalaxmi.bingi@xilinx.com>
Abbarapu Venkatesh Yadav <venkyada@qti.qualcomm.com>
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> <venkatesh.abbarapu@xilinx.com>
Vikhyat Goyal <vikhyat.goyal@amd.com> <vikhyat.goyal@xilinx.com>
Vishal Patel <vishal.patel@amd.com> <vishal.patel@xilinx.com>
Wolfgang Denk <wd@denx.de> <wd@atlas.denx.de>
@@ -159,8 +138,6 @@ Wolfgang Denk <wd@denx.de> <wd@pollux.(none)>
Wolfgang Denk <wd@denx.de> <wd@pollux.denx.de>
Wolfgang Denk <wd@denx.de> <wd@xpert.denx.de>
Wolfgang Denk <wd@denx.de> <wdenk>
Wolfgang Wallner <wolfgang.wallner@at.abb.com> <wolfgang.wallner@br-automation.com>
Yao Zi <me@ziyao.cc> <ziyao@disroot.org>
York Sun <york.sun@nxp.com>
York Sun <yorksun@freescale.com>
Łukasz Majewski <l.majewski@samsung.com>
.readthedocs.yml
-1
View File
@@ -22,4 +22,3 @@ formats: []
python:
install:
- requirements: doc/sphinx/requirements.txt
- requirements: test/py/requirements.txt
COPYING
-1
View File
@@ -1 +0,0 @@
Licenses/gpl-2.0.txt
Kconfig
+24 -39
View File
@@ -27,31 +27,6 @@ config DEPRECATED
code that relies on deprecated features that will be removed and
the conversion deadline has passed.
config COMPILE_TEST
bool "Compile also drivers which will not load"
help
Some drivers can be compiled on a different platform than they are
intended to be run on. Despite they cannot be loaded there (or even
when they load they cannot be used due to missing HW support),
developers still, opposing to distributors, might want to build such
drivers to compile-test them.
If you are a developer and want to build everything available, say Y
here. If you are a user/distributor, say N here to exclude useless
drivers to be distributed.
config WERROR
bool "Compile U-Boot with warnings as errors"
default COMPILE_TEST
help
A U-Boot build should not cause any compiler warnings, and this
enables the '-Werror' flag to enforce that rule.
However, if you have a new (or very old) compiler or linker with odd
and unusual warnings, or you have some architecture with problems,
you may need to disable this config option in order to
successfully build U-Boot.
config LOCALVERSION
string "Local version - append to U-Boot release"
help
@@ -323,7 +298,7 @@ config SYS_MALLOC_F_LEN
config SYS_MALLOC_LEN
hex "Define memory for Dynamic allocation"
default 0x4000000 if SANDBOX
default 0x2000000 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON || ARCH_K3
default 0x2000000 if ARCH_ROCKCHIP || ARCH_OMAP2PLUS || ARCH_MESON
default 0x200000 if ARCH_BMIPS || X86
default 0x4020000 if SUNXI_MINIMUM_DRAM_MB >= 256
default 0x220000 if SUNXI_MINIMUM_DRAM_MB >= 64
@@ -468,12 +443,6 @@ config TOOLS_DEBUG
it is possible to set breakpoints on particular lines, single-step
debug through the source code, etc.
config SKIP_RELOCATE
bool "Skips relocation of U-Boot to end of RAM"
help
Skips relocation of U-Boot allowing for systems that have extremely
limited RAM to run U-Boot.
endif # EXPERT
config PHYS_64BIT
@@ -511,7 +480,6 @@ config SPL_IMAGE
config REMAKE_ELF
bool "Recreate an ELF image from raw U-Boot binary"
depends on !COMPILE_TEST
help
Enable this to recreate an ELF image (u-boot.elf) from the raw
U-Boot binary (u-boot.bin), which may already have been statically
@@ -538,7 +506,6 @@ config BUILD_TARGET
config HAS_BOARD_SIZE_LIMIT
bool "Define a maximum size for the U-Boot image"
depends on !COMPILE_TEST
default y if RCAR_32 || RCAR_64
help
In some cases, we need to enforce a hard limit on how big the U-Boot
@@ -553,11 +520,10 @@ config BOARD_SIZE_LIMIT
Maximum size of the U-Boot image. When defined, the build system
checks that the actual size does not exceed it. This does not
include SPL nor TPL, on platforms that use that functionality, they
have separate options to restrict size.
have a separate option to restict size.
config SYS_CUSTOM_LDSCRIPT
bool "Use a custom location for the U-Boot linker script"
depends on !COMPILE_TEST
help
Normally when linking U-Boot we will look in the board directory,
the CPU directory and finally the "cpu" directory of the architecture
@@ -612,7 +578,6 @@ config STACK_SIZE
hex "Define max stack size that can be used by U-Boot"
default 0x4000000 if ARCH_VERSAL_NET || ARCH_VERSAL || ARCH_ZYNQMP
default 0x200000 if MICROBLAZE
default 0x4000 if ARCH_STM32
default 0x1000000
help
Define Max stack size that can be used by U-Boot. This value is used
@@ -630,6 +595,27 @@ config SYS_MEM_TOP_HIDE
WARNING: Please make sure that this value is a multiple of the OS
page size.
config SYS_HAS_SRAM
bool
default y if TARGET_PIC32MZDASK
default y if TARGET_DEVKIT8000
help
Enable this to allow support for the on board SRAM.
SRAM base address is controlled by CONFIG_SYS_SRAM_BASE.
SRAM size is controlled by CONFIG_SYS_SRAM_SIZE.
config SYS_SRAM_BASE
hex
default 0x80000000 if TARGET_PIC32MZDASK
default 0x40200000 if TARGET_DEVKIT8000
default 0x0
config SYS_SRAM_SIZE
hex
default 0x00080000 if TARGET_PIC32MZDASK
default 0x10000 if TARGET_DEVKIT8000
default 0x0
config SYS_MONITOR_LEN
int "Maximum size in bytes reserved for U-Boot in memory"
default 1048576 if X86
@@ -721,7 +707,6 @@ config TPL_SYS_MONITOR_BASE
config DYNAMIC_SYS_CLK_FREQ
bool "Determine CPU clock frequency at run-time"
depends on !COMPILE_TEST
help
Implement a get_board_sys_clk function that will determine the CPU
clock frequency at run time, rather than define it statically.
@@ -772,7 +757,7 @@ source "dts/Kconfig"
source "env/Kconfig"
menu "Networking"
menu Networking
choice
prompt "Networking stack"
MAINTAINERS
+40 -157
View File
@@ -66,8 +66,8 @@ F: lib/alist.c
F: test/lib/alist.c
ANDROID AB
M: Mattijs Korpershoek <mkorpershoek@kernel.org>
R: Igor Opaniuk <igor.opaniuk@gmail.com>
M: Igor Opaniuk <igor.opaniuk@gmail.com>
M: Mattijs Korpershoek <mkorpershoek@baylibre.com>
R: Sam Protsenko <semen.protsenko@linaro.org>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-dfu.git
@@ -77,8 +77,8 @@ F: include/android_ab.h
F: test/py/tests/test_android/test_ab.py
ANDROID AVB
M: Mattijs Korpershoek <mkorpershoek@kernel.org>
R: Igor Opaniuk <igor.opaniuk@gmail.com>
M: Igor Opaniuk <igor.opaniuk@gmail.com>
M: Mattijs Korpershoek <mkorpershoek@baylibre.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-dfu.git
F: cmd/avb.c
@@ -151,15 +151,10 @@ F: cmd/arm/
ARM ALTERA SOCFPGA
M: Marek Vasut <marex@denx.de>
M: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
M: Tien Fong Chee <tien.fong.chee@altera.com>
M: Tien Fong Chee <tien.fong.chee@intel.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-socfpga.git
F: arch/arm/dts/socfpga_*
F: arch/arm/mach-socfpga/
F: board/intel/agilex-socdk/
F: configs/socfpga_*
F: drivers/ddr/altera/
F: drivers/power/domain/altr-pmgr-agilex5.c
F: drivers/sysreset/sysreset_socfpga*
ARM AMLOGIC SOC SUPPORT
@@ -299,7 +294,7 @@ F: test/cmd/armffa.c
F: test/dm/ffa.c
ARM FREESCALE IMX
M: Stefano Babic <sbabic@nabladev.com>
M: Stefano Babic <sbabic@denx.de>
M: Fabio Estevam <festevam@gmail.com>
R: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
S: Maintained
@@ -317,10 +312,7 @@ F: arch/arm/include/asm/mach-imx/
F: board/freescale/*mx*/
F: board/freescale/common/
F: common/spl/spl_imx_container.c
F: doc/board/nxp/
F: doc/imx/
F: drivers/mailbox/imx-mailbox.c
F: drivers/remoteproc/imx*
F: drivers/serial/serial_mxc.c
F: include/imx_container.h
@@ -348,6 +340,7 @@ F: drivers/spi/gxp_spi.c
ARM IPQ40XX
M: Robert Marko <robert.marko@sartura.hr>
M: Luka Perkov <luka.perkov@sartura.hr>
S: Maintained
F: arch/arm/mach-ipq40xx/
F: include/dt-bindings/clock/qcom,gcc-ipq4019.h
@@ -364,7 +357,7 @@ S: Maintained
F: drivers/misc/ls2_sfp.c
ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
M: Stefan Roese <stefan.roese@mailbox.org>
M: Stefan Roese <sr@denx.de>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
F: arch/arm/mach-kirkwood/
@@ -387,23 +380,15 @@ F: drivers/watchdog/orion_wdt.c
F: include/configs/mv-common.h
ARM MARVELL PCIE CONTROLLER DRIVERS
M: Stefan Roese <stefan.roese@mailbox.org>
M: Stefan Roese <sr@denx.de>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
F: drivers/pci/pci-aardvark.c
F: drivers/pci/pci_mvebu.c
ARM MARVELL PXA1908
M: Duje Mihanović <duje@dujemihanovic.xyz>
S: Maintained
T: git git://git.dujemihanovic.xyz/u-boot.git
F: arch/arm/dts/pxa1908*
F: arch/arm/mach-mmp/
F: include/configs/pxa1908.h
ARM MARVELL SERIAL DRIVERS
M: Pali Rohár <pali@kernel.org>
M: Stefan Roese <stefan.roese@mailbox.org>
M: Stefan Roese <sr@denx.de>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
F: drivers/serial/serial_mvebu_a3700.c
@@ -412,7 +397,6 @@ ARM MEDIATEK
M: Ryder Lee <ryder.lee@mediatek.com>
M: Weijie Gao <weijie.gao@mediatek.com>
M: Chunfeng Yun <chunfeng.yun@mediatek.com>
M: Igor Belwon <igor.belwon@mentallysanemainliners.org>
R: GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>
S: Maintained
F: arch/arm/mach-mediatek/
@@ -425,25 +409,19 @@ F: drivers/clk/mediatek/
F: drivers/cpu/mtk_cpu.c
F: drivers/i2c/mtk_i2c.c
F: drivers/mmc/mtk-sd.c
F: drivers/net/mtk_eth/
F: drivers/net/phy/mediatek/
F: drivers/phy/phy-mtk-*
F: drivers/pinctrl/mediatek/
F: drivers/power/domain/mtk-power-domain.c
F: drivers/pci/pcie_mediatek_gen3.c
F: drivers/pci/pcie_mediatek.c
F: drivers/pwm/pwm-mtk.c
F: drivers/ram/mediatek/
F: drivers/spi/mtk_snfi_spi.c
F: drivers/spi/mtk_spim.c
F: drivers/spi/mtk_snor.c
F: drivers/timer/mtk_timer.c
F: drivers/ufs/ufs-mediatek*
F: drivers/usb/host/xhci-mtk.c
F: drivers/usb/mtu3/
F: drivers/watchdog/mtk_wdt.c
F: drivers/net/mtk_eth.c
F: drivers/net/mtk_eth.h
F: drivers/reset/reset-mediatek.c
F: drivers/serial/serial_mtk.c
F: include/dt-bindings/clock/mediatek,*
F: include/dt-bindings/power/mediatek,*
F: tools/mtk_image.c
@@ -473,6 +451,7 @@ F: drivers/memory/atmel-ebi.c
F: drivers/misc/microchip_flexcom.c
F: drivers/timer/atmel_tcb_timer.c
F: include/dt-bindings/clk/at91.h
F: include/dt-bindings/clock/at91.h
F: include/dt-bindings/dma/at91.h
F: include/dt-bindings/mfd/at91-usart.h
F: include/dt-bindings/mfd/atmel-flexcom.h
@@ -579,7 +558,6 @@ F: drivers/mmc/rockchip_dw_mmc.c
F: drivers/pinctrl/rockchip/
F: drivers/ram/rockchip/
F: drivers/sysreset/sysreset_rockchip.c
F: drivers/ufs/*rockchip*
F: drivers/video/rockchip/
F: tools/rkcommon.c
F: tools/rkcommon.h
@@ -608,7 +586,6 @@ ARM SAMSUNG EXYNOS850 SOC
M: Sam Protsenko <semen.protsenko@linaro.org>
S: Maintained
F: drivers/clk/exynos/clk-exynos850.c
F: drivers/phy/phy-exynos-usbdrd.c
F: drivers/pinctrl/exynos/pinctrl-exynos850.c
ARM SAMSUNG SOC DRIVERS
@@ -625,7 +602,7 @@ F: arch/arm/dts/am335x-sancloud*
ARM SC5XX
M: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
M: Greg Malysa <malysagreg@gmail.com>
M: Greg Malysa <greg.malysa@timesys.com>
M: Ian Roberts <ian.roberts@timesys.com>
M: Vasileios Bimpikas <vasileios.bimpikas@analog.com>
M: Utsav Agarwal <utsav.agarwal@analog.com>
@@ -639,35 +616,21 @@ F: arch/arm/mach-sc5xx/
F: board/adi/
F: doc/device-tree-bindings/arm/adi/adi,sc5xx.yaml
F: doc/device-tree-bindings/clock/adi,sc5xx-clocks.yaml
F: doc/device-tree-bindings/pinctrl/adi,adsp-pinctrl.yaml
F: doc/device-tree-bindings/timer/adi,sc5xx-gptimer.yaml
F: drivers/clk/adi/
F: drivers/dma/adi_dma.c
F: drivers/gpio/adp5588_gpio.c
F: drivers/gpio/gpio-adi-adsp.c
F: drivers/i2c/adi_i2c.c
F: drivers/mmc/adi_sdhci.c
F: drivers/net/dwc_eth_qos_adi.c
F: drivers/pinctrl/pinctrl-adi-adsp.c
F: drivers/remoteproc/adi_sc5xx_rproc.c
F: drivers/serial/serial_adi_uart4.c
F: drivers/spi/adi_spi3.c
F: drivers/timer/adi_sc5xx_timer.c
F: drivers/usb/musb-new/sc5xx.c
F: drivers/watchdog/adi_wdt.c
F: include/configs/sc5*
F: include/dt-bindings/pinctrl/adi-adsp.h
F: include/env/adi/
ARM SNAPDRAGON
M: Casey Connolly <casey.connolly@linaro.org>
M: Caleb Connolly <caleb.connolly@linaro.org>
M: Neil Armstrong <neil.armstrong@linaro.org>
R: Sumit Garg <sumit.garg@kernel.org>
R: Sumit Garg <sumit.garg@linaro.org>
L: u-boot-qcom@groups.io
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-snapdragon.git
F: configs/qcm6490_defconfig
F: configs/qcs9100_defconfig
F: drivers/*/*/pm8???-*
F: drivers/gpio/msm_gpio.c
F: drivers/mmc/msm_sdhci.c
@@ -694,7 +657,8 @@ F: drivers/reset/sti-reset.c
F: drivers/serial/serial_sti_asc.c
F: drivers/sysreset/sysreset_sti.c
F: drivers/timer/arm_global_timer.c
F: drivers/usb/host/dwc3-sti.c
F: drivers/usb/host/dwc3-sti-glue.c
F: include/dwc3-sti-glue.h
F: include/dt-bindings/clock/stih407-clks.h
F: include/dt-bindings/clock/stih410-clks.h
F: include/dt-bindings/reset/stih407-resets.h
@@ -713,7 +677,6 @@ F: drivers/gpio/stm32_gpio.c
F: drivers/hwspinlock/stm32_hwspinlock.c
F: drivers/i2c/stm32f7_i2c.c
F: drivers/mailbox/stm32-ipcc.c
F: drivers/memory/stm32-omm.c
F: drivers/misc/stm32mp_fuse.c
F: drivers/misc/stm32_rcc.c
F: drivers/mmc/stm32_sdmmc2.c
@@ -725,16 +688,14 @@ F: drivers/power/regulator/stm32-vrefbuf.c
F: drivers/power/regulator/stpmic1.c
F: drivers/ram/stm32mp1/
F: drivers/remoteproc/stm32_copro.c
F: drivers/reset/stm32/
F: drivers/reset/stm32-reset.c
F: drivers/rng/optee_rng.c
F: drivers/rng/stm32_rng.c
F: drivers/rtc/stm32_rtc.c
F: drivers/serial/serial_stm32.*
F: drivers/spi/stm32_ospi.c
F: drivers/spi/stm32_qspi.c
F: drivers/spi/stm32_spi.c
F: drivers/video/stm32/stm32_ltdc.c
F: drivers/video/stm32/stm32_lvds.c
F: drivers/watchdog/stm32mp_wdt.c
F: include/dt-bindings/clock/stm32fx-clock.h
F: include/dt-bindings/clock/stm32mp*
@@ -820,7 +781,7 @@ F: include/linux/soc/ti/
ARM U8500
M: Stephan Gerhold <stephan@gerhold.net>
R: Linus Walleij <linusw@kernel.org>
R: Linus Walleij <linus.walleij@linaro.org>
S: Maintained
F: arch/arm/dts/ste-*
F: arch/arm/mach-u8500/
@@ -997,7 +958,7 @@ F: net/eth_bootdevice.c
F: test/boot/
BOOTMETH_ANDROID
M: Mattijs Korpershoek <mkorpershoek@kernel.org>
M: Mattijs Korpershoek <mkorpershoek@baylibre.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-dfu.git
F: boot/bootmeth_android.c
@@ -1031,7 +992,7 @@ S: Maintained
F: cmd/cat.c
CFI FLASH
M: Stefan Roese <stefan.roese@mailbox.org>
M: Stefan Roese <sr@denx.de>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-cfi-flash.git
F: drivers/mtd/cfi_flash.c
@@ -1039,6 +1000,7 @@ F: drivers/mtd/jedec_flash.c
CLOCK
M: Lukasz Majewski <lukma@denx.de>
M: Sean Anderson <seanga2@gmail.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-clk.git
F: drivers/clk/
@@ -1061,27 +1023,25 @@ F: cmd/cpu.c
F: doc/usage/cpu.rst
CYCLIC
M: Stefan Roese <stefan.roese@mailbox.org>
M: Stefan Roese <sr@denx.de>
S: Maintained
F: cmd/cyclic.c
F: common/cyclic.c
F: include/cyclic.h
DEVICETREE REBASING SUBTREE
M: Sumit Garg <sumit.garg@kernel.org>
M: Sumit Garg <sumit.garg@linaro.org>
S: Maintained
F: dts/upstream/
N: OF_UPSTREAM
DFU
M: Lukasz Majewski <lukma@denx.de>
M: Mattijs Korpershoek <mkorpershoek@kernel.org>
M: Mattijs Korpershoek <mkorpershoek@baylibre.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-dfu.git
F: cmd/dfu.c
F: cmd/usb_*.c
F: common/dfu.c
F: common/spl/spl_dfu.c
F: common/update.c
F: doc/api/dfu.rst
F: doc/usage/dfu.rst
@@ -1101,7 +1061,7 @@ F: drivers/core/
F: include/dm/
F: test/dm/
EFI CLIENT
EFI APP
M: Simon Glass <sjg@chromium.org>
M: Heinrich Schuchardt <xypron.glpk@gmx.de>
S: Maintained
@@ -1111,11 +1071,11 @@ F: configs/efi-x86_app*
F: doc/develop/uefi/u-boot_on_efi.rst
F: drivers/block/efi-media-uclass.c
F: drivers/block/sb_efi_media.c
F: lib/efi_client/
F: lib/efi/efi_app.c
F: scripts/build-efi.sh
F: test/dm/efi_media.c
EFI LOADER
EFI PAYLOAD
M: Heinrich Schuchardt <xypron.glpk@gmx.de>
M: Ilias Apalodimas <ilias.apalodimas@linaro.org>
S: Maintained
@@ -1187,17 +1147,8 @@ F: scripts/event_dump.py
F: test/common/event.c
F: test/py/tests/test_event_dump.py
EXTENSION
M: Kory Maincent <kory.maincent@bootlin.com>
S: Maintained
F: board/sunxi/chip.c
F: board/ti/common/cape_detect.c
F: boot/extension-uclass.c
F: cmd/extension_board.c
F: include/extension_board.h
FASTBOOT
M: Mattijs Korpershoek <mkorpershoek@kernel.org>
M: Mattijs Korpershoek <mkorpershoek@baylibre.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-dfu.git
F: cmd/fastboot.c
@@ -1239,7 +1190,7 @@ S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-freebsd.git
FREESCALE QORIQ
M: Peng Fan <peng.fan@nxp.com>
M: Priyanka Jain <priyanka.jain@nxp.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq.git
F: drivers/watchdog/sp805_wdt.c
@@ -1260,22 +1211,15 @@ F: drivers/misc/gsc.c
F: include/gsc.h
I2C
M: Heiko Schocher <hs@nabladev.com>
M: Heiko Schocher <hs@denx.de>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-i2c.git
F: drivers/i2c/
I3C
M: Dinesh <dinesh.maniyam@altera.com>
S: Maintained
T: git https://source.denx.de/u-boot/u-boot.git
F: cmd/i3c.c
F: drivers/i3c/
KWBIMAGE / KWBOOT TOOLS
M: Pali Rohár <pali@kernel.org>
M: Marek Behún <kabel@kernel.org>
M: Stefan Roese <stefan.roese@mailbox.org>
M: Stefan Roese <sr@denx.de>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
F: doc/README.kwbimage
@@ -1307,18 +1251,6 @@ T: git git://github.com/ARM-software/u-boot.git
F: drivers/video/mali_dp.c
F: drivers/i2c/i2c-versatile.c
MBEDTLS
M: Raymond Mao <raymondmaoca@gmail.com>
S: Maintained
F: lib/mbedtls/
MEMBUF
M: Simon Glass <sjg@chromium.org>
S: Maintained
T: git https://source.denx.de/u-boot/u-boot.git
F: include/membuf.h
F: lib/membuf.c
MICROBLAZE
M: Michal Simek <monstr@monstr.eu>
S: Maintained
@@ -1426,12 +1358,10 @@ M: Jaehoon Chung <jh80.chung@samsung.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-mmc.git
F: drivers/mmc/
N: mmc
NETWORK
M: Joe Hershberger <joe.hershberger@ni.com>
M: Ramon Fried <rfried.dev@gmail.com>
M: Jerome Forissier <jerome@forissier.org>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-net.git
F: drivers/net/
@@ -1439,10 +1369,8 @@ F: include/net.h
F: net/
NETWORK (LWIP)
M: Jerome Forissier <jerome@forissier.org>
M: Jerome Forissier <jerome.forissier@linaro.org>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-net.git
F: cmd/lwip/
F: cmd/net-lwip.c
F: configs/qemu_arm64_lwip_defconfig
F: drivers/net/sandbox-lwip.c
@@ -1510,7 +1438,7 @@ S: Maintained
F: tools/patman/
PCIe DWC IMX
M: Sumit Garg <sumit.garg@kernel.org>
M: Sumit Garg <sumit.garg@linaro.org>
S: Maintained
F: drivers/pci/pcie_dw_imx.c
F: drivers/phy/phy-imx8m-pcie.c
@@ -1522,7 +1450,7 @@ F: drivers/pci_endpoint/
F: include/pci_ep.h
PCI MPC85xx
M: Heiko Schocher <hs@nabladev.com>
M: Heiko Schocher <hs@denx.de>
S: Maintained
F: drivers/pci/pci_mpc85xx.c
@@ -1534,7 +1462,6 @@ F: test/cmd/pci_mps.c
POWER
M: Jaehoon Chung <jh80.chung@samsung.com>
M: Peng Fan <peng.fan@nxp.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-pmic.git
F: drivers/power/
@@ -1604,15 +1531,6 @@ F: drivers/clk/clk_k210.c
F: drivers/pinctrl/pinctrl-k210.c
F: include/k210/
RISC-V T-HEAD TH1520
M: Yao Zi <me@ziyao.cc>
S: Maintained
F: arch/riscv/cpu/th1520/
F: drivers/clk/thead/clk-th1520-ap.c
F: drivers/net/dwmac_thead.c
F: drivers/pinctrl/pinctrl-th1520.c
F: drivers/ram/thead/th1520_ddr.c
RNG
M: Sughosh Ganu <sughosh.ganu@linaro.org>
R: Heinrich Schuchardt <xypron.glpk@gmx.de>
@@ -1640,15 +1558,8 @@ F: drivers/*/*sandbox*.c
F: include/dt-bindings/*/sandbox*.h
F: include/os.h
SCMI
M: Peng Fan <peng.fan@nxp.com>
S: Maintained
F: drivers/firmware/scmi/
F: include/scmi*
N: scmi
SEAMA
M: Linus Walleij <linusw@kernel.org>
M: Linus Walleij <linus.walleij@linaro.org>
S: Maintained
F: cmd/seama.c
F: doc/usage/cmd/seama.rst
@@ -1679,13 +1590,6 @@ F: drivers/gpio/sl28cpld-gpio.c
F: drivers/misc/sl28cpld.c
F: drivers/watchdog/sl28cpld-wdt.c
SLRE
M: Rasmus Villemoes <ravi@prevas.dk>
S: Maintained
F: include/slre.h
F: lib/slre.c
F: test/lib/slre.c
SMCCC TRNG
M: Etienne Carriere <etienne.carriere@linaro.org>
S: Maintained
@@ -1827,16 +1731,11 @@ F: lib/optee
UBI
M: Kyungmin Park <kmpark@infradead.org>
M: Heiko Schocher <hs@nabladev.com>
M: Heiko Schocher <hs@denx.de>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-ubi.git
F: drivers/mtd/ubi/
UFETCH
M: Casey Connolly <casey.connolly@linaro.org>
S: Maintained
F: cmd/ufetch.c
UFS
M: Neil Armstrong <neil.armstrong@linaro.org>
M: Bhupesh Sharma <bhupesh.linux@gmail.com>
@@ -1883,29 +1782,13 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-usb.git topic-xhci
F: drivers/usb/host/xhci*
F: include/usb/xhci.h
UTHREAD
M: Jerome Forissier <jerome@forissier.org>
S: Maintained
F: cmd/spawn.c
F: include/uthread.h
F: lib/uthread.c
F: test/cmd/spawn.c
F: test/lib/uthread.c
UUID testing
M: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
S: Maintained
F: test/lib/uuid.c
VBE
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: boot/vbe*
F: common/spl_reloc.c
F: include/vbe.h
VIDEO
M: Anatolij Gustschin <ag.dev.uboot@gmail.com>
M: Anatolij Gustschin <agust@denx.de>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-video.git
F: drivers/video/
@@ -1924,7 +1807,7 @@ F: test/dm/virtio.c
F: doc/develop/driver-model/virtio.rst
WATCHDOG
M: Stefan Roese <stefan.roese@mailbox.org>
M: Stefan Roese <sr@denx.de>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-watchdog.git
F: cmd/wdt.c
Makefile
+401 -664
View File
File diff suppressed because it is too large Load Diff
README
+71 -1
View File
@@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0+
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000 - 2013
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -300,6 +300,28 @@ The following options need to be configured:
Note that if the GPIO device uses I2C, then the I2C interface
must also be configured. See I2C Support, below.
- I/O tracing:
When CONFIG_IO_TRACE is selected, U-Boot intercepts all I/O
accesses and can checksum them or write a list of them out
to memory. See the 'iotrace' command for details. This is
useful for testing device drivers since it can confirm that
the driver behaves the same way before and after a code
change. Currently this is supported on sandbox and arm. To
add support for your architecture, add '#include <iotrace.h>'
to the bottom of arch/<arch>/include/asm/io.h and test.
Example output from the 'iotrace stats' command is below.
Note that if the trace buffer is exhausted, the checksum will
still continue to operate.
iotrace is enabled
Start: 10000000 (buffer start address)
Size: 00010000 (buffer size)
Offset: 00000120 (current buffer offset)
Output: 10000120 (start + offset)
Count: 00000018 (number of trace records)
CRC32: 9526fb66 (CRC32 of all trace records)
- Timestamp Support:
When CONFIG_TIMESTAMP is selected, the timestamp
@@ -357,6 +379,15 @@ The following options need to be configured:
CONFIG_SH_ETHER
Support for Renesas on-chip Ethernet controller
CFG_SH_ETHER_USE_PORT
Define the number of ports to be used
CFG_SH_ETHER_PHY_ADDR
Define the ETH PHY's address
CFG_SH_ETHER_CACHE_WRITEBACK
If this option is set, the driver enables cache flush.
- TPM Support:
CONFIG_TPM
Support TPM devices.
@@ -368,6 +399,17 @@ The following options need to be configured:
CONFIG_TPM_TIS_I2C_BURST_LIMITATION
Define the burst count bytes upper limit
CONFIG_TPM_ST33ZP24
Support for STMicroelectronics TPM devices. Requires DM_TPM support.
CONFIG_TPM_ST33ZP24_I2C
Support for STMicroelectronics ST33ZP24 I2C devices.
Requires TPM_ST33ZP24 and I2C.
CONFIG_TPM_ST33ZP24_SPI
Support for STMicroelectronics ST33ZP24 SPI devices.
Requires TPM_ST33ZP24 and SPI.
CONFIG_TPM_ATMEL_TWI
Support for Atmel TWI TPM device. Requires I2C support.
@@ -440,6 +482,18 @@ The following options need to be configured:
for your device
- CONFIG_USBD_PRODUCTID 0xFFFF
- ULPI Layer Support:
The ULPI (UTMI Low Pin (count) Interface) PHYs are supported via
the generic ULPI layer. The generic layer accesses the ULPI PHY
via the platform viewport, so you need both the genric layer and
the viewport enabled. Currently only Chipidea/ARC based
viewport is supported.
To enable the ULPI layer support, define CONFIG_USB_ULPI and
CONFIG_USB_ULPI_VIEWPORT in your board configuration file.
If your ULPI phy needs a different reference clock than the
standard 24 MHz then you have to define CFG_ULPI_REF_CLK to
the appropriate value in Hz.
- MMC Support:
CONFIG_SH_MMCIF
Support for Renesas on-chip MMCIF controller
@@ -908,6 +962,15 @@ The following options need to be configured:
the environment like the "source" command or the
boot command first.
CONFIG_DELAY_ENVIRONMENT
Normally the environment is loaded when the board is
initialised so that it is available to U-Boot. This inhibits
that so that the environment is not available until
explicitly loaded later by U-Boot code. With CONFIG_OF_CONTROL
this is instead controlled by the value of
/config/load-environment.
- Automatic software updates via TFTP server
CONFIG_UPDATE_TFTP
CONFIG_UPDATE_TFTP_CNT_MAX
@@ -1216,6 +1279,9 @@ Note: once the monitor has been relocated, then it will complain if
the default environment is used; a new CRC is computed as soon as you
use the "saveenv" command to store a valid environment.
- CONFIG_SYS_FAULT_MII_ADDR:
MII address of the PHY to check for the Ethernet link state.
- CONFIG_DISPLAY_BOARDINFO
Display information about the board that U-Boot is running on
when U-Boot starts up. The board function checkboard() is called
@@ -1358,6 +1424,10 @@ Low Level (hardware related) configuration options:
VPL. Code that needs phase-specific behaviour can check this,
or (where possible) use xpl_phase() instead.
Note that CONFIG_XPL_BUILD *is* always defined when either
of CONFIG_TPL_BUILD / CONFIG_VPL_BUILD is defined. This can be
counter-intuitive and should perhaps be changed.
- CONFIG_TPL_BUILD
Set when the currently running compilation is for an artifact
that will end up in the TPL build (as opposed to SPL, VPL or
api/Kconfig
+20
View File
@@ -19,4 +19,24 @@ config EXAMPLES
U-Boot provides an API for standalone applications. Examples are
provided in directory examples/.
config STANDALONE_LOAD_ADDR
depends on EXAMPLES
hex "Address in memory to link standalone applications to"
default 0xffffffff80200000 if MIPS && 64BIT
default 0x8c000000 if SH
default 0x82000000 if ARC
default 0x80f00000 if MICROBLAZE
default 0x80300000 if ARCH_OMAP2PLUS || FSL_LSCH2 || FSL_LSCH3
default 0x80200000 if MIPS && 32BIT
default 0x0c100000 if ARM
default 0x02000000 if NIOS2
default 0x00040000 if PPC || X86
default 0x00020000 if M68K
default 0x0 if RISCV
default SYS_LOAD_ADDR
help
This option defines a board specific value for the address where
standalone program gets loaded, thus overwriting the architecture
dependent default settings.
endmenu
api/Makefile
+3 -6
View File
@@ -1,11 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2007 Semihalf
obj-y += api.o api_display.o api_net.o api_storage.o
ifeq (CONFIG_PPC,y)
obj-$(CONFIG_ARM) += api_platform-arm.o
obj-$(CONFIG_PPC) += api_platform-powerpc.o
else
obj-y += api_platform.o
endif
obj-$(CONFIG_MIPS) += api_platform-mips.o
api/api_platform-arm.c
+35
View File
@@ -0,0 +1,35 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007 Semihalf
*
* Written by: Rafal Jaworowski <raj@semihalf.com>
*
* This file contains routines that fetch data from ARM-dependent sources
* (bd_info etc.)
*/
#include <config.h>
#include <linux/types.h>
#include <api_public.h>
#include <asm/global_data.h>
#include "api_private.h"
DECLARE_GLOBAL_DATA_PTR;
/*
* Important notice: handling of individual fields MUST be kept in sync with
* include/asm-arm/u-boot.h and include/asm-arm/global_data.h, so any changes
* need to reflect their current state and layout of structures involved!
*/
int platform_sys_info(struct sys_info *si)
{
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
platform_set_mr(si, gd->bd->bi_dram[i].start,
gd->bd->bi_dram[i].size, MR_ATTR_DRAM);
return 1;
}
api/api_platform-mips.c
+29
View File
@@ -0,0 +1,29 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007 Stanislav Galabov <sgalabov@gmail.com>
*
* This file contains routines that fetch data from bd_info sources
*/
#include <config.h>
#include <linux/types.h>
#include <api_public.h>
#include <asm/global_data.h>
#include "api_private.h"
DECLARE_GLOBAL_DATA_PTR;
/*
* Important notice: handling of individual fields MUST be kept in sync with
* include/asm-generic/u-boot.h, so any changes
* need to reflect their current state and layout of structures involved!
*/
int platform_sys_info(struct sys_info *si)
{
platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
return 1;
}
api/api_platform-powerpc.c
+1
View File
@@ -43,6 +43,7 @@ int platform_sys_info(struct sys_info *si)
platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH);
platform_set_mr(si, gd->bd->bi_sramstart, gd->bd->bi_sramsize, MR_ATTR_SRAM);
return 1;
}
api/api_platform.c
-31
View File
@@ -1,31 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* (C) Copyright 2007 Semihalf
*
* Written by: Rafal Jaworowski <raj@semihalf.com>
*
* This file contains a routine to fetch data from the global_data structure.
*/
#include <api_public.h>
#include <asm/global_data.h>
#include "api_private.h"
DECLARE_GLOBAL_DATA_PTR;
int platform_sys_info(struct sys_info *si)
{
int i;
si->clk_bus = gd->bus_clk;
si->clk_cpu = gd->cpu_clk;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
platform_set_mr(si, gd->bd->bi_dram[i].start,
gd->bd->bi_dram[i].size, MR_ATTR_DRAM);
platform_set_mr(si, gd->ram_base, gd->ram_size, MR_ATTR_DRAM);
platform_set_mr(si, gd->bd->bi_flashstart, gd->bd->bi_flashsize, MR_ATTR_FLASH);
return 1;
}
arch/Kconfig
+3 -29
View File
@@ -13,13 +13,6 @@ config HAVE_SETJMP
help
The architecture supports setjmp() and longjmp().
config HAVE_INITJMP
bool
depends on HAVE_SETJMP
help
The architecture supports initjmp(), a non-standard companion to
setjmp() and longjmp().
config SUPPORT_BIG_ENDIAN
bool
@@ -44,14 +37,6 @@ config 32BIT
config 64BIT
bool
help
Indicates that U-Boot proper will be built for a 64 bit
architecture.
config SPL_64BIT
bool
help
Indicates that SPL will be built for a 64 bit architecture.
config SYS_CACHELINE_SIZE
int
@@ -59,17 +44,9 @@ config SYS_CACHELINE_SIZE
default 64 if SYS_CACHE_SHIFT_6
default 32 if SYS_CACHE_SHIFT_5
default 16 if SYS_CACHE_SHIFT_4
# Fall-back for MIPS and RISC-V
default 64 if RISCV
# Fall-back for MIPS
default 32 if MIPS
config SYS_DTC_PAD_BYTES
int "Size in bytes to pad device tree blob"
default 32768 if X86 && EFI_APP
default 4096 if ARC || ARM64 || M68K || MICROBLAZE || NIOS2 \
|| RISCV || SANDBOX || X86
default 0
config LINKER_LIST_ALIGN
int
default 32 if SANDBOX
@@ -102,7 +79,6 @@ config ARC
config ARM
bool "ARM architecture"
select HAVE_SETJMP
select HAVE_INITJMP
select ARCH_SUPPORTS_LTO
select CREATE_ARCH_SYMLINK
select HAVE_PRIVATE_LIBGCC if !ARM64
@@ -160,7 +136,6 @@ config RISCV
bool "RISC-V architecture"
select CREATE_ARCH_SYMLINK
select HAVE_SETJMP
select HAVE_INITJMP
select SUPPORT_ACPI
select SUPPORT_LITTLE_ENDIAN
select SUPPORT_OF_CONTROL
@@ -187,7 +162,6 @@ config RISCV
config SANDBOX
bool "Sandbox"
select HAVE_SETJMP
select HAVE_INITJMP
select ARCH_SUPPORTS_LTO
select BOARD_LATE_INIT
select BZIP2
@@ -198,12 +172,13 @@ config SANDBOX
select DM_GPIO
select DM_I2C
select DM_KEYBOARD
select DM_MMC
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
select GZIP_COMPRESSED
select IO_TRACE
select LZO
select MMC
select MTD
select OF_BOARD_SETUP
select PCI_ENDPOINT
@@ -219,7 +194,6 @@ config SANDBOX
imply BITREVERSE
select BLOBLIST
imply LTO
imply CMD_BOOTEFI_SELFTEST
imply CMD_DM
imply CMD_EXCEPTION
imply CMD_GETTIME
arch/Kconfig.nxp
-22
View File
@@ -84,28 +84,6 @@ config SYS_FSL_SFP_VER_3_4
endchoice
config FSL_SEC_MON
bool
help
Freescale Security Monitor block is responsible for monitoring
system states.
Security Monitor can be transitioned on any security failures,
like software violations or hardware security violations.
choice
prompt "Security monitor interaction endianess"
depends on FSL_SEC_MON
default SYS_FSL_SEC_MON_BE if PPC
default SYS_FSL_SEC_MON_LE
config SYS_FSL_SEC_MON_LE
bool "Security monitor interactions are little endian"
config SYS_FSL_SEC_MON_BE
bool "Security monitor interactions are big endian"
endchoice
config SPL_UBOOT_KEY_HASH
string "Non-SRK key hash for U-Boot public/private key pair"
depends on SPL
arch/arc/dts/Makefile
+1 -1
View File
@@ -11,4 +11,4 @@ dtb-$(CONFIG_TARGET_IOT_DEVKIT) += iot_devkit.dtb
include $(srctree)/scripts/Makefile.dts
# Add any required device tree compiler flags here
DTC_FLAGS += -R 4
DTC_FLAGS += -R 4 -p 0x1000
arch/arc/include/asm/global_data.h
+1 -1
View File
@@ -20,6 +20,6 @@ struct arch_global_data {
#include <asm-generic/global_data.h>
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r25")
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r25")
#endif /* __ASM_ARC_GLOBAL_DATA_H */
arch/arc/lib/cache.c
-6
View File
@@ -8,7 +8,6 @@
#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/compiler.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/log2.h>
#include <asm/arcregs.h>
@@ -820,8 +819,3 @@ void sync_n_cleanup_cache_all(void)
__ic_entire_invalidate();
}
int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
{
return -ENOSYS;
}
arch/arm/Kconfig
+57 -94
View File
@@ -7,7 +7,6 @@ config SYS_ARCH
config ARM64
bool
select 64BIT
select SPL_64BIT if SPL
select PHYS_64BIT
select SYS_CACHE_SHIFT_6
imply SPL_SEPARATE_BSS
@@ -30,7 +29,7 @@ config COUNTER_FREQUENCY
ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036
default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A
default 100000000 if ARCH_ZYNQMP
default 200000000 if TARGET_SOCFPGA_AGILEX5 || TARGET_SOCFPGA_AGILEX7M
default 200000000 if ARCH_SOCFPGA && ARM64 && TARGET_SOCFPGA_AGILEX5
default 0
help
For platforms with ARMv8-A and ARMv7-A which features a system
@@ -68,10 +67,10 @@ config INIT_SP_RELATIVE
SYS_INIT_SP_BSS_OFFSET.
config SYS_INIT_SP_BSS_OFFSET
hex "Early stack offset from the .bss base address"
int "Early stack offset from the .bss base address"
depends on ARM64
depends on INIT_SP_RELATIVE
default 0x80000
default 524288
help
This option's value is the offset added to &_bss_start in order to
calculate the stack pointer. This offset should be large enough so
@@ -108,21 +107,6 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE
The value subtracted from CONFIG_TEXT_BASE to calculate the
TEXT_OFFSET value written to the Linux kernel image header.
config KVM_VIRT_INS
bool "Emit virtualizable instructions"
help
Instructions in the ARM ISA that have multiple output registers,
can't be used if the instruction leads to an exception to the hypervisor.
These instructions cannot be emulated by KVM because they do not produce
syndrome information data that KVM can use to infer the destination
register, the faulting address, whether it was a load or store,
if it's a 32 or 64 bit general-purpose register amongst other things.
Use this to produce virtualizable instructions if you plan to run U-Boot
with KVM.
config NVIC
bool
config GICV2
bool
@@ -132,7 +116,6 @@ config GICV3
config DRIVER_GICV2
bool "ARM GICV2 driver"
select IRQ
depends on !NVIC
help
ARM GICV2 driver.
Basic support for parsing the GICV2 node and generate ACPI tables.
@@ -140,7 +123,6 @@ config DRIVER_GICV2
config GIC_V3_ITS
bool "ARM GICV3 ITS"
select IRQ
depends on !NVIC
help
ARM GICV3 Interrupt translation service (ITS).
Basic support for programming locality specific peripheral
@@ -151,7 +133,6 @@ config GIC_V3_ITS
config GICV3_SUPPORT_GIC600
bool "ARM GICV3 GIC600 SUPPORT"
depends on !NVIC
help
ARM GIC-600 IP complies with ARM GICv3 architecture, but among others,
implements a power control register in the Redistributor frame.This
@@ -211,7 +192,6 @@ config SPL_SYS_DCACHE_OFF
config SYS_ARM_CACHE_CP15
bool "CP15 based cache enabling support"
depends on !CPU_V7M
help
Select this if your processor suports enabling caches by using
CP15 registers.
@@ -219,7 +199,6 @@ config SYS_ARM_CACHE_CP15
config SYS_ARM_MMU
bool "MMU-based Paged Memory Management Support"
select SYS_ARM_CACHE_CP15
depends on !CPU_V7M
help
Select if you want MMU-based virtualised addressing space
support via paged memory management.
@@ -370,7 +349,6 @@ config CPU_V7M
select SYS_CACHE_SHIFT_5
select SYS_THUMB_BUILD
select THUMB2_KERNEL
select NVIC
config CPU_V7R
bool
@@ -445,7 +423,7 @@ config ARCH_CPU_INIT
config SYS_ARCH_TIMER
bool "ARM Generic Timer support"
depends on CPU_V7A || CPU_V7M || ARM64
depends on CPU_V7A || ARM64
default y if ARM64
help
The ARM Generic Timer (aka arch-timer) provides an architected
@@ -612,13 +590,6 @@ choice
prompt "Target select"
default TARGET_HIKEY
config ARCH_AIROHA
bool "Airoha SoCs"
select DM
select OF_CONTROL
help
Support for the Airoha soc.
config ARCH_AT91
bool "Atmel AT91"
select GPIO_EXTRA_HEADER
@@ -667,6 +638,7 @@ config ARCH_MVEBU
select SPL_TIMER if SPL
select TIMER if !ARM64
select OF_CONTROL
select OF_SEPARATE
select SPI
imply CMD_DM
@@ -822,7 +794,6 @@ config ARCH_KEYSTONE
imply CMD_SAVES
imply DM_I2C
imply FIT
imply OF_BOARD_SETUP_EXTENDED
imply SOC_TI
imply TI_KEYSTONE_SERDES
@@ -833,12 +804,7 @@ config ARCH_K3
select FIT
select REGEX
select FIT_SIGNATURE if ARM64
select DMA_ADDR_T_64BIT
select LTO
imply TI_SECURE_DEVICE
imply DM_RNG if ARM64
imply TEE if ARM64
imply OPTEE if ARM64
config ARCH_OMAP2PLUS
bool "TI OMAP2+"
@@ -875,16 +841,6 @@ config ARCH_MEDIATEK
Support for the MediaTek SoCs family developed by MediaTek Inc.
Please refer to doc/README.mediatek for more information.
config ARCH_MMP
bool "Marvell MMP"
select ARM64
select DM
select DM_SERIAL
select OF_CONTROL
select SAVE_PREV_BL_FDT_ADDR
select SAVE_PREV_BL_INITRAMFS_START_ADDR
imply OF_UPSTREAM
config ARCH_LPC32XX
bool "NXP LPC32xx platform"
select CPU_ARM926EJS
@@ -898,7 +854,6 @@ config ARCH_LPC32XX
config ARCH_IMX8
bool "NXP i.MX8 platform"
select ARCH_MISC_INIT if FSL_CAAM
select ARM64
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
@@ -912,7 +867,6 @@ config ARCH_IMX8
config ARCH_IMX8M
bool "NXP i.MX8M platform"
select ARCH_MISC_INIT if FSL_CAAM
select ARM64
select GPIO_EXTRA_HEADER
select MACH_IMX
@@ -962,7 +916,6 @@ config ARCH_IMXRT
config ARCH_MX23
bool "NXP i.MX23 family"
select ARCH_MISC_INIT
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
select MACH_IMX
@@ -970,12 +923,17 @@ config ARCH_MX23
config ARCH_MX28
bool "NXP i.MX28 family"
select ARCH_MISC_INIT
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
select MACH_IMX
select SUPPORT_SPL
config ARCH_MX31
bool "NXP i.MX31 family"
select CPU_ARM1136
select GPIO_EXTRA_HEADER
select MACH_IMX
config ARCH_MX7ULP
bool "NXP MX7ULP"
select BOARD_POSTCLK_INIT
@@ -1084,7 +1042,7 @@ config ARCH_OWL
select CLK
select CLK_OWL
select OF_CONTROL
select ENV_RELOC_GD_ENV_ADDR
select SYS_RELOC_GD_ENV_ADDR
imply CMD_DM
config ARCH_QEMU
@@ -1108,11 +1066,9 @@ config ARCH_QEMU
imply USB_XHCI_PCI
imply USB_KEYBOARD
imply CMD_USB
imply POSITION_INDEPENDENT
config ARCH_RENESAS
bool "Renesas ARM SoCs"
select ARCH_MISC_INIT if DISPLAY_CPUINFO && !(RZA1 || RZN1)
select DM
select DM_SERIAL
select GPIO_EXTRA_HEADER
@@ -1122,6 +1078,7 @@ config ARCH_RENESAS
imply FAT_WRITE
imply OF_UPSTREAM
imply SYS_THUMB_BUILD
imply ARCH_MISC_INIT if DISPLAY_CPUINFO
config ARCH_SNAPDRAGON
bool "Qualcomm Snapdragon SoCs"
@@ -1134,18 +1091,15 @@ config ARCH_SNAPDRAGON
select GPIO_EXTRA_HEADER
select MSM_SMEM
select OF_CONTROL
select OF_SEPARATE
select SMEM
select SPMI
select BOARD_LATE_INIT
select OF_BOARD
select SAVE_PREV_BL_FDT_ADDR if !ENABLE_ARM_SOC_BOOT0_HOOK
select SAVE_PREV_BL_FDT_ADDR
select LINUX_KERNEL_IMAGE_HEADER if !ENABLE_ARM_SOC_BOOT0_HOOK
select SYSRESET
select SYSRESET_PSCI
select ANDROID_BOOT_IMAGE_IGNORE_BLOB_ADDR
imply OF_UPSTREAM
imply CMD_DM
imply DM_USB_GADGET
config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
@@ -1155,9 +1109,9 @@ config ARCH_SOCFPGA
select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select DM
select DM_SERIAL
select GICV2
select GPIO_EXTRA_HEADER
select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select LMB_ARCH_MEM_MAP if TARGET_SOCFPGA_SOC64
select OF_CONTROL
select SPL_DM_RESET if DM_RESET
select SPL_DM_SERIAL
@@ -1176,9 +1130,7 @@ config ARCH_SOCFPGA
select SYSRESET
select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \
TARGET_SOCFPGA_SOC64
select SYSRESET_PSCI if TARGET_SOCFPGA_AGILEX5
select USE_BOOTFILE if SPL_ATF && TARGET_SOCFPGA_SOC64
TARGET_SOCFPGA_SOC64
imply CMD_DM
imply CMD_MTDPARTS
imply CRC32_VERIFY
@@ -1192,6 +1144,8 @@ config ARCH_SOCFPGA
imply SPL_DM_SPI_FLASH
imply SPL_LIBDISK_SUPPORT
imply SPL_MMC
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
imply SPL_SPI_FLASH_SUPPORT
imply SPL_SPI
imply L2X0_CACHE
@@ -1209,10 +1163,11 @@ config ARCH_SUNXI
select DM_SPI if SPI
select DM_SPI_FLASH if SPI && MTD
select DM_KEYBOARD
select DM_MMC if MMC
select DM_SERIAL
select MMU_PGPROT if ARM64
select OF_BOARD_SETUP
select OF_CONTROL
select OF_SEPARATE
select PINCTRL
select SPECIFY_CONSOLE_INDEX
select SPL_SEPARATE_BSS if SPL
@@ -1222,11 +1177,12 @@ config ARCH_SUNXI
select SUNXI_GPIO
select SYS_NS16550
select SYS_THUMB_BUILD if !ARM64
select USB if DISTRO_DEFAULTS
select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
select SPL_USE_TINY_PRINTF if SPL
select USE_PREBOOT
select ENV_RELOC_GD_ENV_ADDR
select SYS_RELOC_GD_ENV_ADDR
imply BOARD_LATE_INIT
imply CMD_DM
imply CMD_GPT
@@ -1247,7 +1203,6 @@ config ARCH_SUNXI
imply SYSRESET
imply SYSRESET_WATCHDOG
imply SYSRESET_WATCHDOG_AUTO
imply USB
imply USB_GADGET
imply WDT
@@ -1256,6 +1211,7 @@ config ARCH_U8500
select CPU_V7A
select DM
select DM_GPIO
select DM_MMC if MMC
select DM_SERIAL
select DM_USB_GADGET if DM_USB
select OF_CONTROL
@@ -1280,6 +1236,7 @@ config ARCH_VERSAL
select ARM64
select CLK
select DM
select DM_MMC if MMC
select DM_SERIAL
select GICV3
select OF_CONTROL
@@ -1292,6 +1249,7 @@ config ARCH_VERSAL2
select ARM64
select CLK
select DM
select DM_MMC if MMC
select DM_SERIAL
select OF_CONTROL
imply BOARD_LATE_INIT
@@ -1303,6 +1261,7 @@ config ARCH_VERSAL_NET
select ARM64
select CLK
select DM
select DM_MMC if MMC
select DM_SERIAL
select OF_CONTROL
imply BOARD_LATE_INIT
@@ -1327,6 +1286,7 @@ config ARCH_ZYNQ
select CPU_V7A
select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
select DM
select DM_MMC if MMC
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
@@ -1355,6 +1315,7 @@ config ARCH_ZYNQMP_R5
select CLK
select CPU_V7R
select DM
select DM_MMC if MMC
select DM_SERIAL
select OF_CONTROL
imply CMD_DM
@@ -1363,11 +1324,11 @@ config ARCH_ZYNQMP_R5
config ARCH_ZYNQMP
bool "Xilinx ZynqMP based platform"
select ARM64
select BINMAN
select CLK
select DM
select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
imply DM_MAILBOX
select DM_MMC if MMC
select DM_SERIAL
select MTD
select DM_SPI if SPI
@@ -1417,11 +1378,10 @@ config ARCH_VEXPRESS64
select PL01X_SERIAL
select OF_CONTROL
select CLK
select BLK
select MTD_NOR_FLASH if MTD
select FLASH_CFI_DRIVER if MTD
select ENV_IS_IN_FLASH if MTD
select SYSRESET
select SYSRESET_PSCI if ARM_PSCI_FW
imply DISTRO_DEFAULTS
config TARGET_CORSTONE1000
@@ -1436,9 +1396,9 @@ config TARGET_TOTAL_COMPUTE
select PL01X_SERIAL
select DM
select DM_SERIAL
select DM_MMC
select DM_GPIO
select MMC
imply OF_HAS_PRIOR_STAGE if !BLOBLIST
imply OF_HAS_PRIOR_STAGE
imply MISC_INIT_R
config TARGET_LS2080A_EMU
@@ -1553,6 +1513,7 @@ config TARGET_LX2160AQDS
config TARGET_LX2162AQDS
bool "Support lx2162aqds"
select ARCH_LX2162A
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
@@ -1942,7 +1903,7 @@ config TARGET_SL28
select DM
select DM_GPIO
select DM_I2C
select MMC
select DM_MMC
select MTD
select DM_SPI_FLASH
select DM_MDIO
@@ -1965,6 +1926,7 @@ config TARGET_SL28
config TARGET_TEN64
bool "Support ten64"
select ARCH_LS1088A
select ARCH_MISC_INIT
select ARM64
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
@@ -1982,10 +1944,10 @@ config ARCH_UNIPHIER
select DM
select DM_GPIO
select DM_I2C
select DM_MMC
select DM_MTD
select DM_RESET
select DM_SERIAL
select MMC
select OF_BOARD_SETUP
select OF_CONTROL
select OF_LIBFDT
@@ -2008,6 +1970,7 @@ config ARCH_SYNQUACER
bool "Socionext SynQuacer SoCs"
select ARM64
select DM
select GIC_V3
select PSCI_RESET
select SYSRESET
select SYSRESET_PSCI
@@ -2025,11 +1988,12 @@ config ARCH_STM32
config ARCH_STI
bool "Support STMicroelectronics SoCs"
select BLK
select CPU_V7A
select DM
select DM_MMC
select DM_RESET
select DM_SERIAL
select MMC
imply CMD_DM
help
Support for STMicroelectronics STiH407/10 SoC family.
@@ -2071,32 +2035,33 @@ config ARCH_STM32MP
config ARCH_ROCKCHIP
bool "Support Rockchip SoCs"
select BLK
select BINMAN if SPL_OPTEE || SPL
select DM
select DM_GPIO
select DM_I2C
select DM_MMC
select DM_PWM
select DM_REGULATOR
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
select DM_USB_GADGET if USB_DWC3_GADGET
select ENABLE_ARM_SOC_BOOT0_HOOK
select OF_CONTROL
select MTD
select SPI
select SPL_DM if SPL
select SPL_DM_SPI if SPL
select SPL_DM_SPI_FLASH if SPL
select SYS_MALLOC_F
select SYS_THUMB_BUILD if !ARM64
imply ADC
imply BOOTSTD_DEFAULTS
imply CMD_DM
imply DEBUG_UART_BOARD_INIT
imply DM_GPIO
imply DM_I2C
imply DM_PWM
imply DM_REGULATOR
imply DM_SERIAL
imply DM_SPI
imply DM_SPI_FLASH
imply BOOTSTD_DEFAULTS
imply FAT_WRITE
imply MMC
imply MTD
imply SARADC_ROCKCHIP
imply SPI
imply SPL_DM_SPI if SPL
imply SPL_DM_SPI_FLASH if SPL
imply SPL_SYSRESET
imply SPL_SYS_MALLOC_SIMPLE
imply SYS_NS16550
@@ -2158,6 +2123,7 @@ config TARGET_POMELO
select AHCI
select SCSI_AHCI
select AHCI_PCI
select BLK
select PCI
select DM_PCI
select SCSI
@@ -2228,7 +2194,6 @@ config SERIAL_TAG
config STATIC_MACH_TYPE
bool "Statically define the Machine ID number"
default y if TARGET_DS109 || TARGET_DS414 || DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac"
depends on SUPPORT_PASSING_ATAGS
help
When booting via ATAGs, enable this option if we know the correct
machine ID number to use at compile time. Some systems will be
@@ -2277,8 +2242,6 @@ config SYS_KWD_CONFIG
Path within the source directory to the kwbimage.cfg file to use
when packaging the U-Boot image for use.
source "arch/arm/mach-airoha/Kconfig"
source "arch/arm/mach-apple/Kconfig"
source "arch/arm/mach-aspeed/Kconfig"
@@ -2321,6 +2284,8 @@ source "arch/arm/mach-octeontx2/Kconfig"
source "arch/arm/cpu/armv7/ls102xa/Kconfig"
source "arch/arm/mach-imx/mx3/Kconfig"
source "arch/arm/mach-imx/mx5/Kconfig"
source "arch/arm/mach-imx/mx6/Kconfig"
@@ -2355,8 +2320,6 @@ source "arch/arm/mach-meson/Kconfig"
source "arch/arm/mach-mediatek/Kconfig"
source "arch/arm/mach-mmp/Kconfig"
source "arch/arm/mach-qemu/Kconfig"
source "arch/arm/mach-rockchip/Kconfig"
arch/arm/Makefile
-2
View File
@@ -51,7 +51,6 @@ PLATFORM_CPPFLAGS += $(arch-y) $(tune-y)
# Machine directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
machine-$(CONFIG_ARCH_AIROHA) += airoha
machine-$(CONFIG_ARCH_APPLE) += apple
machine-$(CONFIG_ARCH_ASPEED) += aspeed
machine-$(CONFIG_ARCH_AT91) += at91
@@ -70,7 +69,6 @@ machine-$(CONFIG_ARCH_KIRKWOOD) += kirkwood
machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
machine-$(CONFIG_ARCH_MESON) += meson
machine-$(CONFIG_ARCH_MMP) += mmp
machine-$(CONFIG_ARCH_MVEBU) += mvebu
machine-$(CONFIG_ARCH_NEXELL) += nexell
machine-$(CONFIG_ARCH_NPCM) += npcm
arch/arm/config.mk
+14 -18
View File
@@ -23,42 +23,38 @@ endif
PLATFORM_RELFLAGS += -fno-common $(FIXED_REG)
PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \
$(call cc-option,-mgeneral-regs-only) \
$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
ifeq ($(CONFIG_ARM64),y)
PLATFORM_RELFLAGS += $(call cc-option,-mgeneral-regs-only)
endif
# LLVM support
LLVM_RELFLAGS := $(call cc-option,-mllvm,)
LLVM_RELFLAGS := $(call cc-option,-mllvm,) \
$(call cc-option,-mno-movt,)
PLATFORM_RELFLAGS += $(LLVM_RELFLAGS)
PLATFORM_CPPFLAGS += -D__ARM__
ifdef CONFIG_ARM64
PLATFORM_ELFFLAGS += -B aarch64 -O elf64-littleaarch64
else
PLATFORM_ELFFLAGS += -B arm -O elf32-littlearm
# no-movt is only available when targeting AArch32
LLVM_RELFLAGS += $(call cc-option,-mno-movt,)
endif
PLATFORM_RELFLAGS += $(LLVM_RELFLAGS)
# Choose between ARM/Thumb instruction sets
ifeq ($(CONFIG_$(PHASE_)SYS_THUMB_BUILD),y)
ifeq ($(CONFIG_$(XPL_)SYS_THUMB_BUILD),y)
AFLAGS_IMPLICIT_IT := $(call as-option,-Wa$(comma)-mimplicit-it=always)
PF_CPPFLAGS_ARM := $(AFLAGS_IMPLICIT_IT) \
$(call cc-option, -mthumb -mthumb-interwork,\
$(call cc-option,-marm,)\
$(call cc-option,-mno-thumb-interwork,)\
)
else ifneq ($(CONFIG_ARM64),y)
else
PF_CPPFLAGS_ARM := $(call cc-option,-marm,) \
$(call cc-option,-mno-thumb-interwork,)
endif
# Only test once
ifeq ($(CONFIG_$(PHASE_)SYS_THUMB_BUILD),y)
archprepare: checkthumb checkgcc10
ifeq ($(CONFIG_$(XPL_)SYS_THUMB_BUILD),y)
archprepare: checkthumb checkgcc6
checkthumb:
@if test "$(call cc-name)" = "gcc" -a \
@@ -69,13 +65,13 @@ checkthumb:
false; \
fi
else
archprepare: checkgcc10
archprepare: checkgcc6
endif
checkgcc10:
checkgcc6:
@if test "$(call cc-name)" = "gcc" -a \
"$(call cc-version)" -lt "1000"; then \
echo '*** Your GCC is older than 10.0 and is not supported'; \
"$(call cc-version)" -lt "0600"; then \
echo '*** Your GCC is older than 6.0 and is not supported'; \
false; \
fi
@@ -120,7 +116,7 @@ LDFLAGS_u-boot += -pie
#
# http://sourceware.org/bugzilla/show_bug.cgi?id=12532
#
ifeq ($(CONFIG_$(PHASE_)SYS_THUMB_BUILD),y)
ifeq ($(CONFIG_$(XPL_)SYS_THUMB_BUILD),y)
ifeq ($(GAS_BUG_12532),)
export GAS_BUG_12532:=$(shell if [ $(call binutils-version) -lt 0222 ] ; \
then echo y; else echo n; fi)
arch/arm/cpu/arm920t/Makefile
+1 -1
View File
@@ -9,6 +9,6 @@ obj-y += cpu.o
# some files can only build in ARM mode
ifdef CONFIG_$(PHASE_)SYS_THUMB_BUILD
ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD
CFLAGS_cpu.o := -marm
endif
arch/arm/cpu/arm926ejs/Makefile
+1 -1
View File
@@ -17,7 +17,7 @@ obj-$(CONFIG_ARCH_SUNXI) += sunxi/
# some files can only build in ARM or THUMB2, not THUMB1
ifdef CONFIG_$(PHASE_)SYS_THUMB_BUILD
ifdef CONFIG_$(XPL_)SYS_THUMB_BUILD
ifndef CONFIG_HAS_THUMB2
CFLAGS_cpu.o := -marm
arch/arm/cpu/arm926ejs/cache.c
-6
View File
@@ -5,7 +5,6 @@
*/
#include <cpu_func.h>
#include <asm/cache.h>
#include <linux/errno.h>
#include <linux/types.h>
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
@@ -89,8 +88,3 @@ void enable_caches(void)
dcache_enable();
#endif
}
int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
{
return -ENOSYS;
}
arch/arm/cpu/armv7/Kconfig
+2 -3
View File
@@ -28,7 +28,7 @@ config ARMV7_BOOT_SEC_DEFAULT
variable to "sec" or "nonsec".
config HAS_ARMV7_SECURE_BASE
bool "Enable support for a hardware secure memory area"
bool "Enable support for a ahardware secure memory area"
default y if ARCH_LS1021A || ARCH_MX7 || ARCH_MX7ULP || ARCH_STM32MP \
|| MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || TEGRA124
@@ -36,8 +36,7 @@ config ARMV7_SECURE_BASE
hex "Base address for secure mode memory"
depends on HAS_ARMV7_SECURE_BASE
default 0xfff00000 if TEGRA124
default 0x2ffe0000 if STM32MP13X
default 0x2ffc0000 if STM32MP15X
default 0x2ffc0000 if ARCH_STM32MP
default 0x2f000000 if ARCH_MX7ULP
default 0x10010000 if ARCH_LS1021A
default 0x00900000 if ARCH_MX7
arch/arm/cpu/armv7/Makefile
+2 -1
View File
@@ -17,7 +17,7 @@ obj-$(CONFIG_EFI_LOADER) += sctlr.o
obj-$(CONFIG_ARMV7_NONSEC) += exception_level.o
endif
ifneq ($(CONFIG_$(PHASE_)SKIP_LOWLEVEL_INIT),y)
ifneq ($(CONFIG_$(XPL_)SKIP_LOWLEVEL_INIT),y)
obj-y += lowlevel_init.o
endif
@@ -32,6 +32,7 @@ ifneq (,$(filter s5pc1xx exynos,$(SOC)))
obj-y += s5p-common/
endif
obj-$(if $(filter bcm235xx,$(SOC)),y) += bcm235xx/
obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
arch/arm/cpu/armv7/bcm235xx/Makefile
+10
View File
@@ -0,0 +1,10 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2013 Broadcom Corporation.
obj-y += clk-core.o
obj-y += clk-bcm235xx.o
obj-y += clk-sdio.o
obj-y += clk-bsc.o
obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
obj-y += clk-usb-otg.o
arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c
+567
View File
@@ -0,0 +1,567 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Broadcom Corporation.
*/
/*
*
* bcm235xx-specific clock tables
*
*/
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include "clk-core.h"
#define CLOCK_1K 1000
#define CLOCK_1M (CLOCK_1K * 1000)
/* declare a reference clock */
#define DECLARE_REF_CLK(clk_name, clk_parent, clk_rate, clk_div) \
static struct refclk clk_name = { \
.clk = { \
.name = #clk_name, \
.parent = clk_parent, \
.rate = clk_rate, \
.div = clk_div, \
.ops = &ref_clk_ops, \
}, \
}
/*
* Reference clocks
*/
/* Declare a list of reference clocks */
DECLARE_REF_CLK(ref_crystal, 0, 26 * CLOCK_1M, 1);
DECLARE_REF_CLK(var_96m, 0, 96 * CLOCK_1M, 1);
DECLARE_REF_CLK(ref_96m, 0, 96 * CLOCK_1M, 1);
DECLARE_REF_CLK(ref_312m, 0, 312 * CLOCK_1M, 0);
DECLARE_REF_CLK(ref_104m, &ref_312m.clk, 104 * CLOCK_1M, 3);
DECLARE_REF_CLK(ref_52m, &ref_104m.clk, 52 * CLOCK_1M, 2);
DECLARE_REF_CLK(ref_13m, &ref_52m.clk, 13 * CLOCK_1M, 4);
DECLARE_REF_CLK(var_312m, 0, 312 * CLOCK_1M, 0);
DECLARE_REF_CLK(var_104m, &var_312m.clk, 104 * CLOCK_1M, 3);
DECLARE_REF_CLK(var_52m, &var_104m.clk, 52 * CLOCK_1M, 2);
DECLARE_REF_CLK(var_13m, &var_52m.clk, 13 * CLOCK_1M, 4);
struct refclk_lkup {
struct refclk *procclk;
const char *name;
};
/* Lookup table for string to clk tranlation */
#define MKSTR(x) {&x, #x}
static struct refclk_lkup refclk_str_tbl[] = {
MKSTR(ref_crystal), MKSTR(var_96m), MKSTR(ref_96m),
MKSTR(ref_312m), MKSTR(ref_104m), MKSTR(ref_52m),
MKSTR(ref_13m), MKSTR(var_312m), MKSTR(var_104m),
MKSTR(var_52m), MKSTR(var_13m),
};
int refclk_entries = sizeof(refclk_str_tbl)/sizeof(refclk_str_tbl[0]);
/* convert ref clock string to clock structure pointer */
struct refclk *refclk_str_to_clk(const char *name)
{
int i;
struct refclk_lkup *tblp = refclk_str_tbl;
for (i = 0; i < refclk_entries; i++, tblp++) {
if (!(strcmp(name, tblp->name)))
return tblp->procclk;
}
return NULL;
}
/* frequency tables indexed by freq_id */
unsigned long master_axi_freq_tbl[8] = {
26 * CLOCK_1M,
52 * CLOCK_1M,
104 * CLOCK_1M,
156 * CLOCK_1M,
156 * CLOCK_1M,
208 * CLOCK_1M,
312 * CLOCK_1M,
312 * CLOCK_1M
};
unsigned long master_ahb_freq_tbl[8] = {
26 * CLOCK_1M,
52 * CLOCK_1M,
52 * CLOCK_1M,
52 * CLOCK_1M,
78 * CLOCK_1M,
104 * CLOCK_1M,
104 * CLOCK_1M,
156 * CLOCK_1M
};
unsigned long slave_axi_freq_tbl[8] = {
26 * CLOCK_1M,
52 * CLOCK_1M,
78 * CLOCK_1M,
104 * CLOCK_1M,
156 * CLOCK_1M,
156 * CLOCK_1M
};
unsigned long slave_apb_freq_tbl[8] = {
26 * CLOCK_1M,
26 * CLOCK_1M,
39 * CLOCK_1M,
52 * CLOCK_1M,
52 * CLOCK_1M,
78 * CLOCK_1M
};
unsigned long esub_freq_tbl[8] = {
78 * CLOCK_1M,
156 * CLOCK_1M,
156 * CLOCK_1M,
156 * CLOCK_1M,
208 * CLOCK_1M,
208 * CLOCK_1M,
208 * CLOCK_1M
};
static struct bus_clk_data bsc1_apb_data = {
.gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
};
static struct bus_clk_data bsc2_apb_data = {
.gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1),
};
static struct bus_clk_data bsc3_apb_data = {
.gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1),
};
/* * Master CCU clocks */
static struct peri_clk_data sdio1_data = {
.gate = HW_SW_GATE(0x0358, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_52m",
"ref_52m",
"var_96m",
"ref_96m"),
.sel = SELECTOR(0x0a28, 0, 3),
.div = DIVIDER(0x0a28, 4, 14),
.trig = TRIGGER(0x0afc, 9),
};
static struct peri_clk_data sdio2_data = {
.gate = HW_SW_GATE(0x035c, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_52m",
"ref_52m",
"var_96m",
"ref_96m"),
.sel = SELECTOR(0x0a2c, 0, 3),
.div = DIVIDER(0x0a2c, 4, 14),
.trig = TRIGGER(0x0afc, 10),
};
static struct peri_clk_data sdio3_data = {
.gate = HW_SW_GATE(0x0364, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_52m",
"ref_52m",
"var_96m",
"ref_96m"),
.sel = SELECTOR(0x0a34, 0, 3),
.div = DIVIDER(0x0a34, 4, 14),
.trig = TRIGGER(0x0afc, 12),
};
static struct peri_clk_data sdio4_data = {
.gate = HW_SW_GATE(0x0360, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_52m",
"ref_52m",
"var_96m",
"ref_96m"),
.sel = SELECTOR(0x0a30, 0, 3),
.div = DIVIDER(0x0a30, 4, 14),
.trig = TRIGGER(0x0afc, 11),
};
static struct peri_clk_data sdio1_sleep_data = {
.clocks = CLOCKS("ref_32k"),
.gate = SW_ONLY_GATE(0x0358, 20, 4),
};
static struct peri_clk_data sdio2_sleep_data = {
.clocks = CLOCKS("ref_32k"),
.gate = SW_ONLY_GATE(0x035c, 20, 4),
};
static struct peri_clk_data sdio3_sleep_data = {
.clocks = CLOCKS("ref_32k"),
.gate = SW_ONLY_GATE(0x0364, 20, 4),
};
static struct peri_clk_data sdio4_sleep_data = {
.clocks = CLOCKS("ref_32k"),
.gate = SW_ONLY_GATE(0x0360, 20, 4),
};
static struct bus_clk_data usb_otg_ahb_data = {
.gate = HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
};
static struct bus_clk_data sdio1_ahb_data = {
.gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
};
static struct bus_clk_data sdio2_ahb_data = {
.gate = HW_SW_GATE_AUTO(0x035c, 16, 0, 1),
};
static struct bus_clk_data sdio3_ahb_data = {
.gate = HW_SW_GATE_AUTO(0x0364, 16, 0, 1),
};
static struct bus_clk_data sdio4_ahb_data = {
.gate = HW_SW_GATE_AUTO(0x0360, 16, 0, 1),
};
/* * Slave CCU clocks */
static struct peri_clk_data bsc1_data = {
.gate = HW_SW_GATE(0x0458, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_104m",
"ref_104m",
"var_13m",
"ref_13m"),
.sel = SELECTOR(0x0a64, 0, 3),
.trig = TRIGGER(0x0afc, 23),
};
static struct peri_clk_data bsc2_data = {
.gate = HW_SW_GATE(0x045c, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_104m",
"ref_104m",
"var_13m",
"ref_13m"),
.sel = SELECTOR(0x0a68, 0, 3),
.trig = TRIGGER(0x0afc, 24),
};
static struct peri_clk_data bsc3_data = {
.gate = HW_SW_GATE(0x0484, 18, 2, 3),
.clocks = CLOCKS("ref_crystal",
"var_104m",
"ref_104m",
"var_13m",
"ref_13m"),
.sel = SELECTOR(0x0a84, 0, 3),
.trig = TRIGGER(0x0b00, 2),
};
/*
* CCU clocks
*/
static struct ccu_clock kpm_ccu_clk = {
.clk = {
.name = "kpm_ccu_clk",
.ops = &ccu_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.num_policy_masks = 1,
.policy_freq_offset = 0x00000008,
.freq_bit_shift = 8,
.policy_ctl_offset = 0x0000000c,
.policy0_mask_offset = 0x00000010,
.policy1_mask_offset = 0x00000014,
.policy2_mask_offset = 0x00000018,
.policy3_mask_offset = 0x0000001c,
.lvm_en_offset = 0x00000034,
.freq_id = 2,
.freq_tbl = master_axi_freq_tbl,
};
static struct ccu_clock kps_ccu_clk = {
.clk = {
.name = "kps_ccu_clk",
.ops = &ccu_clk_ops,
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
},
.num_policy_masks = 1,
.policy_freq_offset = 0x00000008,
.freq_bit_shift = 8,
.policy_ctl_offset = 0x0000000c,
.policy0_mask_offset = 0x00000010,
.policy1_mask_offset = 0x00000014,
.policy2_mask_offset = 0x00000018,
.policy3_mask_offset = 0x0000001c,
.lvm_en_offset = 0x00000034,
.freq_id = 2,
.freq_tbl = slave_axi_freq_tbl,
};
#ifdef CONFIG_BCM_SF2_ETH
static struct ccu_clock esub_ccu_clk = {
.clk = {
.name = "esub_ccu_clk",
.ops = &ccu_clk_ops,
.ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR,
},
.num_policy_masks = 1,
.policy_freq_offset = 0x00000008,
.freq_bit_shift = 8,
.policy_ctl_offset = 0x0000000c,
.policy0_mask_offset = 0x00000010,
.policy1_mask_offset = 0x00000014,
.policy2_mask_offset = 0x00000018,
.policy3_mask_offset = 0x0000001c,
.lvm_en_offset = 0x00000034,
.freq_id = 2,
.freq_tbl = esub_freq_tbl,
};
#endif
/*
* Bus clocks
*/
/* KPM bus clocks */
static struct bus_clock usb_otg_ahb_clk = {
.clk = {
.name = "usb_otg_ahb_clk",
.parent = &kpm_ccu_clk.clk,
.ops = &bus_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.freq_tbl = master_ahb_freq_tbl,
.data = &usb_otg_ahb_data,
};
static struct bus_clock sdio1_ahb_clk = {
.clk = {
.name = "sdio1_ahb_clk",
.parent = &kpm_ccu_clk.clk,
.ops = &bus_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.freq_tbl = master_ahb_freq_tbl,
.data = &sdio1_ahb_data,
};
static struct bus_clock sdio2_ahb_clk = {
.clk = {
.name = "sdio2_ahb_clk",
.parent = &kpm_ccu_clk.clk,
.ops = &bus_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.freq_tbl = master_ahb_freq_tbl,
.data = &sdio2_ahb_data,
};
static struct bus_clock sdio3_ahb_clk = {
.clk = {
.name = "sdio3_ahb_clk",
.parent = &kpm_ccu_clk.clk,
.ops = &bus_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.freq_tbl = master_ahb_freq_tbl,
.data = &sdio3_ahb_data,
};
static struct bus_clock sdio4_ahb_clk = {
.clk = {
.name = "sdio4_ahb_clk",
.parent = &kpm_ccu_clk.clk,
.ops = &bus_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.freq_tbl = master_ahb_freq_tbl,
.data = &sdio4_ahb_data,
};
static struct bus_clock bsc1_apb_clk = {
.clk = {
.name = "bsc1_apb_clk",
.parent = &kps_ccu_clk.clk,
.ops = &bus_clk_ops,
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
},
.freq_tbl = slave_apb_freq_tbl,
.data = &bsc1_apb_data,
};
static struct bus_clock bsc2_apb_clk = {
.clk = {
.name = "bsc2_apb_clk",
.parent = &kps_ccu_clk.clk,
.ops = &bus_clk_ops,
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
},
.freq_tbl = slave_apb_freq_tbl,
.data = &bsc2_apb_data,
};
static struct bus_clock bsc3_apb_clk = {
.clk = {
.name = "bsc3_apb_clk",
.parent = &kps_ccu_clk.clk,
.ops = &bus_clk_ops,
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
},
.freq_tbl = slave_apb_freq_tbl,
.data = &bsc3_apb_data,
};
/* KPM peripheral */
static struct peri_clock sdio1_clk = {
.clk = {
.name = "sdio1_clk",
.parent = &ref_52m.clk,
.ops = &peri_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.data = &sdio1_data,
};
static struct peri_clock sdio2_clk = {
.clk = {
.name = "sdio2_clk",
.parent = &ref_52m.clk,
.ops = &peri_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.data = &sdio2_data,
};
static struct peri_clock sdio3_clk = {
.clk = {
.name = "sdio3_clk",
.parent = &ref_52m.clk,
.ops = &peri_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.data = &sdio3_data,
};
static struct peri_clock sdio4_clk = {
.clk = {
.name = "sdio4_clk",
.parent = &ref_52m.clk,
.ops = &peri_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.data = &sdio4_data,
};
static struct peri_clock sdio1_sleep_clk = {
.clk = {
.name = "sdio1_sleep_clk",
.parent = &kpm_ccu_clk.clk,
.ops = &bus_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.data = &sdio1_sleep_data,
};
static struct peri_clock sdio2_sleep_clk = {
.clk = {
.name = "sdio2_sleep_clk",
.parent = &kpm_ccu_clk.clk,
.ops = &bus_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.data = &sdio2_sleep_data,
};
static struct peri_clock sdio3_sleep_clk = {
.clk = {
.name = "sdio3_sleep_clk",
.parent = &kpm_ccu_clk.clk,
.ops = &bus_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.data = &sdio3_sleep_data,
};
static struct peri_clock sdio4_sleep_clk = {
.clk = {
.name = "sdio4_sleep_clk",
.parent = &kpm_ccu_clk.clk,
.ops = &bus_clk_ops,
.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
},
.data = &sdio4_sleep_data,
};
/* KPS peripheral clock */
static struct peri_clock bsc1_clk = {
.clk = {
.name = "bsc1_clk",
.parent = &ref_13m.clk,
.rate = 13 * CLOCK_1M,
.div = 1,
.ops = &peri_clk_ops,
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
},
.data = &bsc1_data,
};
static struct peri_clock bsc2_clk = {
.clk = {
.name = "bsc2_clk",
.parent = &ref_13m.clk,
.rate = 13 * CLOCK_1M,
.div = 1,
.ops = &peri_clk_ops,
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
},
.data = &bsc2_data,
};
static struct peri_clock bsc3_clk = {
.clk = {
.name = "bsc3_clk",
.parent = &ref_13m.clk,
.rate = 13 * CLOCK_1M,
.div = 1,
.ops = &peri_clk_ops,
.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
},
.data = &bsc3_data,
};
/* public table for registering clocks */
struct clk_lookup arch_clk_tbl[] = {
/* Peripheral clocks */
CLK_LK(sdio1),
CLK_LK(sdio2),
CLK_LK(sdio3),
CLK_LK(sdio4),
CLK_LK(sdio1_sleep),
CLK_LK(sdio2_sleep),
CLK_LK(sdio3_sleep),
CLK_LK(sdio4_sleep),
CLK_LK(bsc1),
CLK_LK(bsc2),
CLK_LK(bsc3),
/* Bus clocks */
CLK_LK(usb_otg_ahb),
CLK_LK(sdio1_ahb),
CLK_LK(sdio2_ahb),
CLK_LK(sdio3_ahb),
CLK_LK(sdio4_ahb),
CLK_LK(bsc1_apb),
CLK_LK(bsc2_apb),
CLK_LK(bsc3_apb),
#ifdef CONFIG_BCM_SF2_ETH
CLK_LK(esub_ccu),
#endif
};
/* public array size */
unsigned int arch_clk_tbl_array_size = ARRAY_SIZE(arch_clk_tbl);
arch/arm/cpu/armv7/bcm235xx/clk-bsc.c
+50
View File
@@ -0,0 +1,50 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Broadcom Corporation.
*/
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include "clk-core.h"
/* Enable appropriate clocks for a BSC/I2C port */
int clk_bsc_enable(void *base)
{
int ret;
char *bscstr, *apbstr;
switch ((u32) base) {
case PMU_BSC_BASE_ADDR:
/* PMU clock is always enabled */
return 0;
case BSC1_BASE_ADDR:
bscstr = "bsc1_clk";
apbstr = "bsc1_apb_clk";
break;
case BSC2_BASE_ADDR:
bscstr = "bsc2_clk";
apbstr = "bsc2_apb_clk";
break;
case BSC3_BASE_ADDR:
bscstr = "bsc3_clk";
apbstr = "bsc3_apb_clk";
break;
default:
printf("%s: base 0x%p not found\n", __func__, base);
return -EINVAL;
}
/* Note that the bus clock must be enabled first */
ret = clk_get_and_enable(apbstr);
if (ret)
return ret;
ret = clk_get_and_enable(bscstr);
if (ret)
return ret;
return 0;
}
arch/arm/cpu/armv7/bcm235xx/clk-core.c
+512
View File
@@ -0,0 +1,512 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Broadcom Corporation.
*/
/*
*
* bcm235xx architecture clock framework
*
*/
#include <log.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <bitfield.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include "clk-core.h"
#define CLK_WR_ACCESS_PASSWORD 0x00a5a501
#define WR_ACCESS_OFFSET 0 /* common to all clock blocks */
#define POLICY_CTL_GO 1 /* Load and refresh policy masks */
#define POLICY_CTL_GO_ATL 4 /* Active Load */
/* Helper function */
int clk_get_and_enable(char *clkstr)
{
int ret = 0;
struct clk *c;
debug("%s: %s\n", __func__, clkstr);
c = clk_get(clkstr);
if (c) {
ret = clk_enable(c);
if (ret)
return ret;
} else {
printf("%s: Couldn't find %s\n", __func__, clkstr);
return -EINVAL;
}
return ret;
}
/*
* Poll a register in a CCU's address space, returning when the
* specified bit in that register's value is set (or clear). Delay
* a microsecond after each read of the register. Returns true if
* successful, or false if we gave up trying.
*
* Caller must ensure the CCU lock is held.
*/
#define CLK_GATE_DELAY_USEC 2000
static inline int wait_bit(void *base, u32 offset, u32 bit, bool want)
{
unsigned int tries;
u32 bit_mask = 1 << bit;
for (tries = 0; tries < CLK_GATE_DELAY_USEC; tries++) {
u32 val;
bool bit_val;
val = readl(base + offset);
bit_val = (val & bit_mask) ? 1 : 0;
if (bit_val == want)
return 0; /* success */
udelay(1);
}
debug("%s: timeout on addr 0x%p, waiting for bit %d to go to %d\n",
__func__, base + offset, bit, want);
return -ETIMEDOUT;
}
/* Enable a peripheral clock */
static int peri_clk_enable(struct clk *c, int enable)
{
int ret = 0;
u32 reg;
struct peri_clock *peri_clk = to_peri_clk(c);
struct peri_clk_data *cd = peri_clk->data;
struct bcm_clk_gate *gate = &cd->gate;
void *base = (void *)c->ccu_clk_mgr_base;
debug("%s: %s\n", __func__, c->name);
clk_get_rate(c); /* Make sure rate and sel are filled in */
/* enable access */
writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
if (enable) {
debug("%s %s set rate %lu div %lu sel %d parent %lu\n",
__func__, c->name, c->rate, c->div, c->sel,
c->parent->rate);
/*
* clkgate - only software controllable gates are
* supported by u-boot which includes all clocks
* that matter. This avoids bringing in a lot of extra
* complexity as done in the kernel framework.
*/
if (gate_exists(gate)) {
reg = readl(base + cd->gate.offset);
reg |= (1 << cd->gate.en_bit);
writel(reg, base + cd->gate.offset);
}
/* div and pll select */
if (divider_exists(&cd->div)) {
reg = readl(base + cd->div.offset);
bitfield_replace(reg, cd->div.shift, cd->div.width,
c->div - 1);
writel(reg, base + cd->div.offset);
}
/* frequency selector */
if (selector_exists(&cd->sel)) {
reg = readl(base + cd->sel.offset);
bitfield_replace(reg, cd->sel.shift, cd->sel.width,
c->sel);
writel(reg, base + cd->sel.offset);
}
/* trigger */
if (trigger_exists(&cd->trig)) {
writel((1 << cd->trig.bit), base + cd->trig.offset);
/* wait for trigger status bit to go to 0 */
ret = wait_bit(base, cd->trig.offset, cd->trig.bit, 0);
if (ret)
return ret;
}
/* wait for running (status_bit = 1) */
ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1);
if (ret)
return ret;
} else {
debug("%s disable clock %s\n", __func__, c->name);
/* clkgate */
reg = readl(base + cd->gate.offset);
reg &= ~(1 << cd->gate.en_bit);
writel(reg, base + cd->gate.offset);
/* wait for stop (status_bit = 0) */
ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0);
}
/* disable access */
writel(0, base + WR_ACCESS_OFFSET);
return ret;
}
/* Set the rate of a peripheral clock */
static int peri_clk_set_rate(struct clk *c, unsigned long rate)
{
int ret = 0;
int i;
unsigned long diff;
unsigned long new_rate = 0, div = 1;
struct peri_clock *peri_clk = to_peri_clk(c);
struct peri_clk_data *cd = peri_clk->data;
const char **clock;
debug("%s: %s\n", __func__, c->name);
diff = rate;
i = 0;
for (clock = cd->clocks; *clock; clock++, i++) {
struct refclk *ref = refclk_str_to_clk(*clock);
if (!ref) {
printf("%s: Lookup of %s failed\n", __func__, *clock);
return -EINVAL;
}
/* round to the new rate */
div = ref->clk.rate / rate;
if (div == 0)
div = 1;
new_rate = ref->clk.rate / div;
/* get the min diff */
if (abs(new_rate - rate) < diff) {
diff = abs(new_rate - rate);
c->sel = i;
c->parent = &ref->clk;
c->rate = new_rate;
c->div = div;
}
}
debug("%s %s set rate %lu div %lu sel %d parent %lu\n", __func__,
c->name, c->rate, c->div, c->sel, c->parent->rate);
return ret;
}
/* Get the rate of a peripheral clock */
static unsigned long peri_clk_get_rate(struct clk *c)
{
struct peri_clock *peri_clk = to_peri_clk(c);
struct peri_clk_data *cd = peri_clk->data;
void *base = (void *)c->ccu_clk_mgr_base;
int div = 1;
const char **clock;
struct refclk *ref;
u32 reg;
debug("%s: %s\n", __func__, c->name);
if (selector_exists(&cd->sel)) {
reg = readl(base + cd->sel.offset);
c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width);
} else {
/*
* For peri clocks that don't have a selector, the single
* reference clock will always exist at index 0.
*/
c->sel = 0;
}
if (divider_exists(&cd->div)) {
reg = readl(base + cd->div.offset);
div = bitfield_extract(reg, cd->div.shift, cd->div.width);
div += 1;
}
clock = cd->clocks;
ref = refclk_str_to_clk(clock[c->sel]);
if (!ref) {
printf("%s: Can't lookup %s\n", __func__, clock[c->sel]);
return 0;
}
c->parent = &ref->clk;
c->div = div;
c->rate = c->parent->rate / c->div;
debug("%s parent rate %lu div %d sel %d rate %lu\n", __func__,
c->parent->rate, div, c->sel, c->rate);
return c->rate;
}
/* Peripheral clock operations */
struct clk_ops peri_clk_ops = {
.enable = peri_clk_enable,
.set_rate = peri_clk_set_rate,
.get_rate = peri_clk_get_rate,
};
/* Enable a CCU clock */
static int ccu_clk_enable(struct clk *c, int enable)
{
struct ccu_clock *ccu_clk = to_ccu_clk(c);
void *base = (void *)c->ccu_clk_mgr_base;
int ret = 0;
u32 reg;
debug("%s: %s\n", __func__, c->name);
if (!enable)
return -EINVAL; /* CCU clock cannot shutdown */
/* enable access */
writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
/* config enable for policy engine */
writel(1, base + ccu_clk->lvm_en_offset);
/* wait for bit to go to 0 */
ret = wait_bit(base, ccu_clk->lvm_en_offset, 0, 0);
if (ret)
return ret;
/* freq ID */
if (!ccu_clk->freq_bit_shift)
ccu_clk->freq_bit_shift = 8;
/* Set frequency id for each of the 4 policies */
reg = ccu_clk->freq_id |
(ccu_clk->freq_id << (ccu_clk->freq_bit_shift)) |
(ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 2)) |
(ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 3));
writel(reg, base + ccu_clk->policy_freq_offset);
/* enable all clock mask */
writel(0x7fffffff, base + ccu_clk->policy0_mask_offset);
writel(0x7fffffff, base + ccu_clk->policy1_mask_offset);
writel(0x7fffffff, base + ccu_clk->policy2_mask_offset);
writel(0x7fffffff, base + ccu_clk->policy3_mask_offset);
if (ccu_clk->num_policy_masks == 2) {
writel(0x7fffffff, base + ccu_clk->policy0_mask2_offset);
writel(0x7fffffff, base + ccu_clk->policy1_mask2_offset);
writel(0x7fffffff, base + ccu_clk->policy2_mask2_offset);
writel(0x7fffffff, base + ccu_clk->policy3_mask2_offset);
}
/* start policy engine */
reg = readl(base + ccu_clk->policy_ctl_offset);
reg |= (POLICY_CTL_GO + POLICY_CTL_GO_ATL);
writel(reg, base + ccu_clk->policy_ctl_offset);
/* wait till started */
ret = wait_bit(base, ccu_clk->policy_ctl_offset, 0, 0);
if (ret)
return ret;
/* disable access */
writel(0, base + WR_ACCESS_OFFSET);
return ret;
}
/* Get the CCU clock rate */
static unsigned long ccu_clk_get_rate(struct clk *c)
{
struct ccu_clock *ccu_clk = to_ccu_clk(c);
debug("%s: %s\n", __func__, c->name);
c->rate = ccu_clk->freq_tbl[ccu_clk->freq_id];
return c->rate;
}
/* CCU clock operations */
struct clk_ops ccu_clk_ops = {
.enable = ccu_clk_enable,
.get_rate = ccu_clk_get_rate,
};
/* Enable a bus clock */
static int bus_clk_enable(struct clk *c, int enable)
{
struct bus_clock *bus_clk = to_bus_clk(c);
struct bus_clk_data *cd = bus_clk->data;
void *base = (void *)c->ccu_clk_mgr_base;
int ret = 0;
u32 reg;
debug("%s: %s\n", __func__, c->name);
/* enable access */
writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
/* enable gating */
reg = readl(base + cd->gate.offset);
if (!!(reg & (1 << cd->gate.status_bit)) == !!enable)
debug("%s already %s\n", c->name,
enable ? "enabled" : "disabled");
else {
int want = (enable) ? 1 : 0;
reg |= (1 << cd->gate.hw_sw_sel_bit);
if (enable)
reg |= (1 << cd->gate.en_bit);
else
reg &= ~(1 << cd->gate.en_bit);
writel(reg, base + cd->gate.offset);
ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit,
want);
if (ret)
return ret;
}
/* disable access */
writel(0, base + WR_ACCESS_OFFSET);
return ret;
}
/* Get the rate of a bus clock */
static unsigned long bus_clk_get_rate(struct clk *c)
{
struct bus_clock *bus_clk = to_bus_clk(c);
struct ccu_clock *ccu_clk;
debug("%s: %s\n", __func__, c->name);
ccu_clk = to_ccu_clk(c->parent);
c->rate = bus_clk->freq_tbl[ccu_clk->freq_id];
c->div = ccu_clk->freq_tbl[ccu_clk->freq_id] / c->rate;
return c->rate;
}
/* Bus clock operations */
struct clk_ops bus_clk_ops = {
.enable = bus_clk_enable,
.get_rate = bus_clk_get_rate,
};
/* Enable a reference clock */
static int ref_clk_enable(struct clk *c, int enable)
{
debug("%s: %s\n", __func__, c->name);
return 0;
}
/* Reference clock operations */
struct clk_ops ref_clk_ops = {
.enable = ref_clk_enable,
};
/*
* clk.h implementation follows
*/
/* Initialize the clock framework */
int clk_init(void)
{
debug("%s:\n", __func__);
return 0;
}
/* Get a clock handle, give a name string */
struct clk *clk_get(const char *con_id)
{
int i;
struct clk_lookup *clk_tblp;
debug("%s: %s\n", __func__, con_id);
clk_tblp = arch_clk_tbl;
for (i = 0; i < arch_clk_tbl_array_size; i++, clk_tblp++) {
if (clk_tblp->con_id) {
if (!con_id || strcmp(clk_tblp->con_id, con_id))
continue;
return clk_tblp->clk;
}
}
return NULL;
}
/* Enable a clock */
int clk_enable(struct clk *c)
{
int ret = 0;
debug("%s: %s\n", __func__, c->name);
if (!c->ops || !c->ops->enable)
return -1;
/* enable parent clock first */
if (c->parent)
ret = clk_enable(c->parent);
if (ret)
return ret;
if (!c->use_cnt)
ret = c->ops->enable(c, 1);
c->use_cnt++;
return ret;
}
/* Disable a clock */
void clk_disable(struct clk *c)
{
debug("%s: %s\n", __func__, c->name);
if (!c->ops || !c->ops->enable)
return;
if (c->use_cnt > 0) {
c->use_cnt--;
if (c->use_cnt == 0)
c->ops->enable(c, 0);
}
/* disable parent */
if (c->parent)
clk_disable(c->parent);
}
/* Get the clock rate */
unsigned long clk_get_rate(struct clk *c)
{
unsigned long rate;
if (!c || !c->ops || !c->ops->get_rate)
return 0;
debug("%s: %s\n", __func__, c->name);
rate = c->ops->get_rate(c);
debug("%s: rate = %ld\n", __func__, rate);
return rate;
}
/* Set the clock rate */
int clk_set_rate(struct clk *c, unsigned long rate)
{
int ret;
if (!c || !c->ops || !c->ops->set_rate)
return -EINVAL;
debug("%s: %s rate=%ld\n", __func__, c->name, rate);
if (c->use_cnt)
return -EINVAL;
ret = c->ops->set_rate(c, rate);
return ret;
}
/* Not required for this arch */
/*
long clk_round_rate(struct clk *clk, unsigned long rate);
int clk_set_parent(struct clk *clk, struct clk *parent);
struct clk *clk_get_parent(struct clk *clk);
*/
arch/arm/cpu/armv7/bcm235xx/clk-core.h
+491
View File
@@ -0,0 +1,491 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2013 Broadcom Corporation.
*/
#include <linux/stddef.h>
#include <linux/stringify.h>
#ifdef CONFIG_CLK_DEBUG
#undef writel
#undef readl
static inline void writel(u32 val, void *addr)
{
printf("Write [0x%p] = 0x%08x\n", addr, val);
*(u32 *)addr = val;
}
static inline u32 readl(void *addr)
{
u32 val = *(u32 *)addr;
printf("Read [0x%p] = 0x%08x\n", addr, val);
return val;
}
#endif
struct clk;
struct clk_lookup {
const char *dev_id;
const char *con_id;
struct clk *clk;
};
extern struct clk_lookup arch_clk_tbl[];
extern unsigned int arch_clk_tbl_array_size;
/**
* struct clk_ops - standard clock operations
* @enable: enable/disable clock, see clk_enable() and clk_disable()
* @set_rate: set the clock rate, see clk_set_rate().
* @get_rate: get the clock rate, see clk_get_rate().
* @round_rate: round a given clock rate, see clk_round_rate().
* @set_parent: set the clock's parent, see clk_set_parent().
*
* Group the common clock implementations together so that we
* don't have to keep setting the same fiels again. We leave
* enable in struct clk.
*
*/
struct clk_ops {
int (*enable)(struct clk *c, int enable);
int (*set_rate)(struct clk *c, unsigned long rate);
unsigned long (*get_rate)(struct clk *c);
unsigned long (*round_rate)(struct clk *c, unsigned long rate);
int (*set_parent)(struct clk *c, struct clk *parent);
};
struct clk {
struct clk *parent;
const char *name;
int use_cnt;
unsigned long rate; /* in HZ */
/* programmable divider. 0 means fixed ratio to parent clock */
unsigned long div;
struct clk_src *src;
struct clk_ops *ops;
unsigned long ccu_clk_mgr_base;
int sel;
};
struct refclk *refclk_str_to_clk(const char *name);
/* The common clock framework uses u8 to represent a parent index */
#define PARENT_COUNT_MAX ((u32)U8_MAX)
#define BAD_CLK_INDEX U8_MAX /* Can't ever be valid */
#define BAD_CLK_NAME ((const char *)-1)
#define BAD_SCALED_DIV_VALUE U64_MAX
/*
* Utility macros for object flag management. If possible, flags
* should be defined such that 0 is the desired default value.
*/
#define FLAG(type, flag) BCM_CLK_ ## type ## _FLAGS_ ## flag
#define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
#define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
#define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
#define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
/* Clock field state tests */
#define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS)
#define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED)
#define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW)
#define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW)
#define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED)
#define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE)
#define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED)
#define divider_exists(div) FLAG_TEST(div, DIV, EXISTS)
#define divider_is_fixed(div) FLAG_TEST(div, DIV, FIXED)
#define divider_has_fraction(div) (!divider_is_fixed(div) && \
(div)->frac_width > 0)
#define selector_exists(sel) ((sel)->width != 0)
#define trigger_exists(trig) FLAG_TEST(trig, TRIG, EXISTS)
/* Clock type, used to tell common block what it's part of */
enum bcm_clk_type {
bcm_clk_none, /* undefined clock type */
bcm_clk_bus,
bcm_clk_core,
bcm_clk_peri
};
/*
* Gating control and status is managed by a 32-bit gate register.
*
* There are several types of gating available:
* - (no gate)
* A clock with no gate is assumed to be always enabled.
* - hardware-only gating (auto-gating)
* Enabling or disabling clocks with this type of gate is
* managed automatically by the hardware. Such clocks can be
* considered by the software to be enabled. The current status
* of auto-gated clocks can be read from the gate status bit.
* - software-only gating
* Auto-gating is not available for this type of clock.
* Instead, software manages whether it's enabled by setting or
* clearing the enable bit. The current gate status of a gate
* under software control can be read from the gate status bit.
* To ensure a change to the gating status is complete, the
* status bit can be polled to verify that the gate has entered
* the desired state.
* - selectable hardware or software gating
* Gating for this type of clock can be configured to be either
* under software or hardware control. Which type is in use is
* determined by the hw_sw_sel bit of the gate register.
*/
struct bcm_clk_gate {
u32 offset; /* gate register offset */
u32 status_bit; /* 0: gate is disabled; 0: gatge is enabled */
u32 en_bit; /* 0: disable; 1: enable */
u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */
u32 flags; /* BCM_CLK_GATE_FLAGS_* below */
};
/*
* Gate flags:
* HW means this gate can be auto-gated
* SW means the state of this gate can be software controlled
* NO_DISABLE means this gate is (only) enabled if under software control
* SW_MANAGED means the status of this gate is under software control
* ENABLED means this software-managed gate is *supposed* to be enabled
*/
#define BCM_CLK_GATE_FLAGS_EXISTS ((u32)1 << 0) /* Gate is valid */
#define BCM_CLK_GATE_FLAGS_HW ((u32)1 << 1) /* Can auto-gate */
#define BCM_CLK_GATE_FLAGS_SW ((u32)1 << 2) /* Software control */
#define BCM_CLK_GATE_FLAGS_NO_DISABLE ((u32)1 << 3) /* HW or enabled */
#define BCM_CLK_GATE_FLAGS_SW_MANAGED ((u32)1 << 4) /* SW now in control */
#define BCM_CLK_GATE_FLAGS_ENABLED ((u32)1 << 5) /* If SW_MANAGED */
/*
* Gate initialization macros.
*
* Any gate initially under software control will be enabled.
*/
/* A hardware/software gate initially under software control */
#define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
{ \
.offset = (_offset), \
.status_bit = (_status_bit), \
.en_bit = (_en_bit), \
.hw_sw_sel_bit = (_hw_sw_sel_bit), \
.flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)| \
FLAG(GATE, EXISTS), \
}
/* A hardware/software gate initially under hardware control */
#define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
{ \
.offset = (_offset), \
.status_bit = (_status_bit), \
.en_bit = (_en_bit), \
.hw_sw_sel_bit = (_hw_sw_sel_bit), \
.flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
FLAG(GATE, EXISTS), \
}
/* A hardware-or-enabled gate (enabled if not under hardware control) */
#define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
{ \
.offset = (_offset), \
.status_bit = (_status_bit), \
.en_bit = (_en_bit), \
.hw_sw_sel_bit = (_hw_sw_sel_bit), \
.flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS), \
}
/* A software-only gate */
#define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \
{ \
.offset = (_offset), \
.status_bit = (_status_bit), \
.en_bit = (_en_bit), \
.flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \
FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS), \
}
/* A hardware-only gate */
#define HW_ONLY_GATE(_offset, _status_bit) \
{ \
.offset = (_offset), \
.status_bit = (_status_bit), \
.flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \
}
/*
* Each clock can have zero, one, or two dividers which change the
* output rate of the clock. Each divider can be either fixed or
* variable. If there are two dividers, they are the "pre-divider"
* and the "regular" or "downstream" divider. If there is only one,
* there is no pre-divider.
*
* A fixed divider is any non-zero (positive) value, and it
* indicates how the input rate is affected by the divider.
*
* The value of a variable divider is maintained in a sub-field of a
* 32-bit divider register. The position of the field in the
* register is defined by its offset and width. The value recorded
* in this field is always 1 less than the value it represents.
*
* In addition, a variable divider can indicate that some subset
* of its bits represent a "fractional" part of the divider. Such
* bits comprise the low-order portion of the divider field, and can
* be viewed as representing the portion of the divider that lies to
* the right of the decimal point. Most variable dividers have zero
* fractional bits. Variable dividers with non-zero fraction width
* still record a value 1 less than the value they represent; the
* added 1 does *not* affect the low-order bit in this case, it
* affects the bits above the fractional part only. (Often in this
* code a divider field value is distinguished from the value it
* represents by referring to the latter as a "divisor".)
*
* In order to avoid dealing with fractions, divider arithmetic is
* performed using "scaled" values. A scaled value is one that's
* been left-shifted by the fractional width of a divider. Dividing
* a scaled value by a scaled divisor produces the desired quotient
* without loss of precision and without any other special handling
* for fractions.
*
* The recorded value of a variable divider can be modified. To
* modify either divider (or both), a clock must be enabled (i.e.,
* using its gate). In addition, a trigger register (described
* below) must be used to commit the change, and polled to verify
* the change is complete.
*/
struct bcm_clk_div {
union {
struct { /* variable divider */
u32 offset; /* divider register offset */
u32 shift; /* field shift */
u32 width; /* field width */
u32 frac_width; /* field fraction width */
u64 scaled_div; /* scaled divider value */
};
u32 fixed; /* non-zero fixed divider value */
};
u32 flags; /* BCM_CLK_DIV_FLAGS_* below */
};
/*
* Divider flags:
* EXISTS means this divider exists
* FIXED means it is a fixed-rate divider
*/
#define BCM_CLK_DIV_FLAGS_EXISTS ((u32)1 << 0) /* Divider is valid */
#define BCM_CLK_DIV_FLAGS_FIXED ((u32)1 << 1) /* Fixed-value */
/* Divider initialization macros */
/* A fixed (non-zero) divider */
#define FIXED_DIVIDER(_value) \
{ \
.fixed = (_value), \
.flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED), \
}
/* A divider with an integral divisor */
#define DIVIDER(_offset, _shift, _width) \
{ \
.offset = (_offset), \
.shift = (_shift), \
.width = (_width), \
.scaled_div = BAD_SCALED_DIV_VALUE, \
.flags = FLAG(DIV, EXISTS), \
}
/* A divider whose divisor has an integer and fractional part */
#define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \
{ \
.offset = (_offset), \
.shift = (_shift), \
.width = (_width), \
.frac_width = (_frac_width), \
.scaled_div = BAD_SCALED_DIV_VALUE, \
.flags = FLAG(DIV, EXISTS), \
}
/*
* Clocks may have multiple "parent" clocks. If there is more than
* one, a selector must be specified to define which of the parent
* clocks is currently in use. The selected clock is indicated in a
* sub-field of a 32-bit selector register. The range of
* representable selector values typically exceeds the number of
* available parent clocks. Occasionally the reset value of a
* selector field is explicitly set to a (specific) value that does
* not correspond to a defined input clock.
*
* We register all known parent clocks with the common clock code
* using a packed array (i.e., no empty slots) of (parent) clock
* names, and refer to them later using indexes into that array.
* We maintain an array of selector values indexed by common clock
* index values in order to map between these common clock indexes
* and the selector values used by the hardware.
*
* Like dividers, a selector can be modified, but to do so a clock
* must be enabled, and a trigger must be used to commit the change.
*/
struct bcm_clk_sel {
u32 offset; /* selector register offset */
u32 shift; /* field shift */
u32 width; /* field width */
u32 parent_count; /* number of entries in parent_sel[] */
u32 *parent_sel; /* array of parent selector values */
u8 clk_index; /* current selected index in parent_sel[] */
};
/* Selector initialization macro */
#define SELECTOR(_offset, _shift, _width) \
{ \
.offset = (_offset), \
.shift = (_shift), \
.width = (_width), \
.clk_index = BAD_CLK_INDEX, \
}
/*
* Making changes to a variable divider or a selector for a clock
* requires the use of a trigger. A trigger is defined by a single
* bit within a register. To signal a change, a 1 is written into
* that bit. To determine when the change has been completed, that
* trigger bit is polled; the read value will be 1 while the change
* is in progress, and 0 when it is complete.
*
* Occasionally a clock will have more than one trigger. In this
* case, the "pre-trigger" will be used when changing a clock's
* selector and/or its pre-divider.
*/
struct bcm_clk_trig {
u32 offset; /* trigger register offset */
u32 bit; /* trigger bit */
u32 flags; /* BCM_CLK_TRIG_FLAGS_* below */
};
/*
* Trigger flags:
* EXISTS means this trigger exists
*/
#define BCM_CLK_TRIG_FLAGS_EXISTS ((u32)1 << 0) /* Trigger is valid */
/* Trigger initialization macro */
#define TRIGGER(_offset, _bit) \
{ \
.offset = (_offset), \
.bit = (_bit), \
.flags = FLAG(TRIG, EXISTS), \
}
struct bus_clk_data {
struct bcm_clk_gate gate;
};
struct core_clk_data {
struct bcm_clk_gate gate;
};
struct peri_clk_data {
struct bcm_clk_gate gate;
struct bcm_clk_trig pre_trig;
struct bcm_clk_div pre_div;
struct bcm_clk_trig trig;
struct bcm_clk_div div;
struct bcm_clk_sel sel;
const char *clocks[]; /* must be last; use CLOCKS() to declare */
};
#define CLOCKS(...) { __VA_ARGS__, NULL, }
#define NO_CLOCKS { NULL, } /* Must use of no parent clocks */
struct refclk {
struct clk clk;
};
struct peri_clock {
struct clk clk;
struct peri_clk_data *data;
};
struct ccu_clock {
struct clk clk;
int num_policy_masks;
unsigned long policy_freq_offset;
int freq_bit_shift; /* 8 for most CCUs */
unsigned long policy_ctl_offset;
unsigned long policy0_mask_offset;
unsigned long policy1_mask_offset;
unsigned long policy2_mask_offset;
unsigned long policy3_mask_offset;
unsigned long policy0_mask2_offset;
unsigned long policy1_mask2_offset;
unsigned long policy2_mask2_offset;
unsigned long policy3_mask2_offset;
unsigned long lvm_en_offset;
int freq_id;
unsigned long *freq_tbl;
};
struct bus_clock {
struct clk clk;
struct bus_clk_data *data;
unsigned long *freq_tbl;
};
struct ref_clock {
struct clk clk;
};
static inline int is_same_clock(struct clk *a, struct clk *b)
{
return a == b;
}
#define to_clk(p) (&((p)->clk))
#define name_to_clk(name) (&((name##_clk).clk))
/* declare a struct clk_lookup */
#define CLK_LK(name) \
{.con_id = __stringify(name##_clk), .clk = name_to_clk(name),}
static inline struct refclk *to_refclk(struct clk *clock)
{
return container_of(clock, struct refclk, clk);
}
static inline struct peri_clock *to_peri_clk(struct clk *clock)
{
return container_of(clock, struct peri_clock, clk);
}
static inline struct ccu_clock *to_ccu_clk(struct clk *clock)
{
return container_of(clock, struct ccu_clock, clk);
}
static inline struct bus_clock *to_bus_clk(struct clk *clock)
{
return container_of(clock, struct bus_clock, clk);
}
static inline struct ref_clock *to_ref_clk(struct clk *clock)
{
return container_of(clock, struct ref_clock, clk);
}
extern struct clk_ops peri_clk_ops;
extern struct clk_ops ccu_clk_ops;
extern struct clk_ops bus_clk_ops;
extern struct clk_ops ref_clk_ops;
int clk_get_and_enable(char *clkstr);
arch/arm/cpu/armv7/bcm235xx/clk-eth.c
+142
View File
@@ -0,0 +1,142 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Broadcom Corporation.
*/
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include "clk-core.h"
#define WR_ACCESS_ADDR ESUB_CLK_BASE_ADDR
#define WR_ACCESS_PASSWORD 0xA5A500
#define PLLE_POST_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C00)
#define PLLE_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C58)
#define PLLE_RESETB_I_PLL_RESETB_PLLE_MASK 0x00010000
#define PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK 0x00000001
#define PLL_LOCK_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C38)
#define PLL_LOCK_PLL_LOCK_PLLE_MASK 0x00000001
#define ESW_SYS_DIV_ADDR (ESUB_CLK_BASE_ADDR + 0x00000A04)
#define ESW_SYS_DIV_PLL_SELECT_MASK 0x00000300
#define ESW_SYS_DIV_DIV_MASK 0x0000001C
#define ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT 0x00000100
#define ESW_SYS_DIV_DIV_SELECT 0x4
#define ESW_SYS_DIV_TRIGGER_MASK 0x00000001
#define ESUB_AXI_DIV_DEBUG_ADDR (ESUB_CLK_BASE_ADDR + 0x00000E04)
#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK 0x0000001C
#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK 0x00000040
#define ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT 0x0
#define ESUB_AXI_DIV_DEBUG_TRIGGER_MASK 0x00000001
#define PLL_MAX_RETRY 100
/* Enable appropriate clocks for Ethernet */
int clk_eth_enable(void)
{
int rc = -1;
int retry_count = 0;
rc = clk_get_and_enable("esub_ccu_clk");
/* Enable Access to CCU registers */
writel((1 | WR_ACCESS_PASSWORD), WR_ACCESS_ADDR);
writel(readl(PLLE_POST_RESETB_ADDR) &
~PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
PLLE_POST_RESETB_ADDR);
/* Take PLL out of reset and put into normal mode */
writel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK,
PLLE_RESETB_ADDR);
/* Wait for PLL lock */
rc = -1;
while (retry_count < PLL_MAX_RETRY) {
udelay(100);
if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) {
rc = 0;
break;
}
retry_count++;
}
if (rc == -1) {
printf("%s: ETH-PLL lock timeout, Ethernet is not enabled!\n",
__func__);
return -1;
}
writel(readl(PLLE_POST_RESETB_ADDR) |
PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
PLLE_POST_RESETB_ADDR);
/* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */
writel((readl(ESW_SYS_DIV_ADDR) &
~(ESW_SYS_DIV_PLL_SELECT_MASK | ESW_SYS_DIV_DIV_MASK)) |
ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT | ESW_SYS_DIV_DIV_SELECT,
ESW_SYS_DIV_ADDR);
writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK,
ESW_SYS_DIV_ADDR);
/* Wait for trigger complete */
rc = -1;
retry_count = 0;
while (retry_count < PLL_MAX_RETRY) {
udelay(100);
if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) {
rc = 0;
break;
}
retry_count++;
}
if (rc == -1) {
printf("%s: SYS CLK Trigger timeout, Ethernet is not enabled!\n",
__func__);
return -1;
}
/* switch Esub AXI clock to 208MHz */
writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) &
~(ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK |
ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK |
ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) |
ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT |
ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK,
ESUB_AXI_DIV_DEBUG_ADDR);
writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) |
ESUB_AXI_DIV_DEBUG_TRIGGER_MASK,
ESUB_AXI_DIV_DEBUG_ADDR);
/* Wait for trigger complete */
rc = -1;
retry_count = 0;
while (retry_count < PLL_MAX_RETRY) {
udelay(100);
if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) &
ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) {
rc = 0;
break;
}
retry_count++;
}
if (rc == -1) {
printf("%s: AXI CLK Trigger timeout, Ethernet is not enabled!\n",
__func__);
return -1;
}
/* Disable Access to CCU registers */
writel(WR_ACCESS_PASSWORD, WR_ACCESS_ADDR);
return rc;
}
arch/arm/cpu/armv7/bcm235xx/clk-sdio.c
+71
View File
@@ -0,0 +1,71 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Broadcom Corporation.
*/
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include "clk-core.h"
/* Enable appropriate clocks for an SDIO port */
int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep)
{
int ret;
struct clk *c;
char *clkstr;
char *slpstr;
char *ahbstr;
switch ((u32) base) {
case CONFIG_SYS_SDIO_BASE0:
clkstr = CONFIG_SYS_SDIO0 "_clk";
ahbstr = CONFIG_SYS_SDIO0 "_ahb_clk";
slpstr = CONFIG_SYS_SDIO0 "_sleep_clk";
break;
case CONFIG_SYS_SDIO_BASE1:
clkstr = CONFIG_SYS_SDIO1 "_clk";
ahbstr = CONFIG_SYS_SDIO1 "_ahb_clk";
slpstr = CONFIG_SYS_SDIO1 "_sleep_clk";
break;
case CONFIG_SYS_SDIO_BASE2:
clkstr = CONFIG_SYS_SDIO2 "_clk";
ahbstr = CONFIG_SYS_SDIO2 "_ahb_clk";
slpstr = CONFIG_SYS_SDIO2 "_sleep_clk";
break;
case CONFIG_SYS_SDIO_BASE3:
clkstr = CONFIG_SYS_SDIO3 "_clk";
ahbstr = CONFIG_SYS_SDIO3 "_ahb_clk";
slpstr = CONFIG_SYS_SDIO3 "_sleep_clk";
break;
default:
printf("%s: base 0x%p not found\n", __func__, base);
return -EINVAL;
}
ret = clk_get_and_enable(ahbstr);
if (ret)
return ret;
ret = clk_get_and_enable(slpstr);
if (ret)
return ret;
c = clk_get(clkstr);
if (c) {
ret = clk_set_rate(c, rate);
if (ret)
return ret;
ret = clk_enable(c);
if (ret)
return ret;
} else {
printf("%s: Couldn't find %s\n", __func__, clkstr);
return -EINVAL;
}
*actual_ratep = rate;
return 0;
}
arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c
+25
View File
@@ -0,0 +1,25 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Broadcom Corporation.
*/
#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include "clk-core.h"
/* Enable appropriate clocks for the USB OTG port */
int clk_usb_otg_enable(void *base)
{
char *ahbstr;
switch ((u32) base) {
case HSOTG_BASE_ADDR:
ahbstr = "usb_otg_ahb_clk";
break;
default:
printf("%s: base 0x%p not found\n", __func__, base);
return -EINVAL;
}
return clk_get_and_enable(ahbstr);
}
arch/arm/cpu/armv7/bcm281xx/Makefile
+1
View File
@@ -7,4 +7,5 @@ obj-y += clk-core.o
obj-y += clk-bcm281xx.o
obj-y += clk-sdio.o
obj-y += clk-bsc.o
obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
obj-y += clk-usb-otg.o
arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
+24
View File
@@ -307,6 +307,27 @@ static struct ccu_clock kps_ccu_clk = {
.freq_tbl = slave_axi_freq_tbl,
};
#ifdef CONFIG_BCM_SF2_ETH
static struct ccu_clock esub_ccu_clk = {
.clk = {
.name = "esub_ccu_clk",
.ops = &ccu_clk_ops,
.ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR,
},
.num_policy_masks = 1,
.policy_freq_offset = 0x00000008,
.freq_bit_shift = 8,
.policy_ctl_offset = 0x0000000c,
.policy0_mask_offset = 0x00000010,
.policy1_mask_offset = 0x00000014,
.policy2_mask_offset = 0x00000018,
.policy3_mask_offset = 0x0000001c,
.lvm_en_offset = 0x00000034,
.freq_id = 2,
.freq_tbl = esub_freq_tbl,
};
#endif
/*
* Bus clocks
*/
@@ -541,6 +562,9 @@ struct clk_lookup arch_clk_tbl[] = {
CLK_LK(bsc1_apb),
CLK_LK(bsc2_apb),
CLK_LK(bsc3_apb),
#ifdef CONFIG_BCM_SF2_ETH
CLK_LK(esub_ccu),
#endif
};
/* public array size */
arch/arm/cpu/armv7/bcm281xx/clk-eth.c
+142
View File
@@ -0,0 +1,142 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Broadcom Corporation.
*/
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/arch/sysmap.h>
#include <asm/kona-common/clk.h>
#include "clk-core.h"
#define WR_ACCESS_ADDR ESUB_CLK_BASE_ADDR
#define WR_ACCESS_PASSWORD 0xA5A500
#define PLLE_POST_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C00)
#define PLLE_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C58)
#define PLLE_RESETB_I_PLL_RESETB_PLLE_MASK 0x00010000
#define PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK 0x00000001
#define PLL_LOCK_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C38)
#define PLL_LOCK_PLL_LOCK_PLLE_MASK 0x00000001
#define ESW_SYS_DIV_ADDR (ESUB_CLK_BASE_ADDR + 0x00000A04)
#define ESW_SYS_DIV_PLL_SELECT_MASK 0x00000300
#define ESW_SYS_DIV_DIV_MASK 0x0000001C
#define ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT 0x00000100
#define ESW_SYS_DIV_DIV_SELECT 0x4
#define ESW_SYS_DIV_TRIGGER_MASK 0x00000001
#define ESUB_AXI_DIV_DEBUG_ADDR (ESUB_CLK_BASE_ADDR + 0x00000E04)
#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK 0x0000001C
#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK 0x00000040
#define ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT 0x0
#define ESUB_AXI_DIV_DEBUG_TRIGGER_MASK 0x00000001
#define PLL_MAX_RETRY 100
/* Enable appropriate clocks for Ethernet */
int clk_eth_enable(void)
{
int rc = -1;
int retry_count = 0;
rc = clk_get_and_enable("esub_ccu_clk");
/* Enable Access to CCU registers */
writel((1 | WR_ACCESS_PASSWORD), WR_ACCESS_ADDR);
writel(readl(PLLE_POST_RESETB_ADDR) &
~PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
PLLE_POST_RESETB_ADDR);
/* Take PLL out of reset and put into normal mode */
writel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK,
PLLE_RESETB_ADDR);
/* Wait for PLL lock */
rc = -1;
while (retry_count < PLL_MAX_RETRY) {
udelay(100);
if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) {
rc = 0;
break;
}
retry_count++;
}
if (rc == -1) {
printf("%s: ETH-PLL lock timeout, Ethernet is not enabled!\n",
__func__);
return -1;
}
writel(readl(PLLE_POST_RESETB_ADDR) |
PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
PLLE_POST_RESETB_ADDR);
/* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */
writel((readl(ESW_SYS_DIV_ADDR) &
~(ESW_SYS_DIV_PLL_SELECT_MASK | ESW_SYS_DIV_DIV_MASK)) |
ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT | ESW_SYS_DIV_DIV_SELECT,
ESW_SYS_DIV_ADDR);
writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK,
ESW_SYS_DIV_ADDR);
/* Wait for trigger complete */
rc = -1;
retry_count = 0;
while (retry_count < PLL_MAX_RETRY) {
udelay(100);
if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) {
rc = 0;
break;
}
retry_count++;
}
if (rc == -1) {
printf("%s: SYS CLK Trigger timeout, Ethernet is not enabled!\n",
__func__);
return -1;
}
/* switch Esub AXI clock to 208MHz */
writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) &
~(ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK |
ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK |
ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) |
ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT |
ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK,
ESUB_AXI_DIV_DEBUG_ADDR);
writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) |
ESUB_AXI_DIV_DEBUG_TRIGGER_MASK,
ESUB_AXI_DIV_DEBUG_ADDR);
/* Wait for trigger complete */
rc = -1;
retry_count = 0;
while (retry_count < PLL_MAX_RETRY) {
udelay(100);
if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) &
ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) {
rc = 0;
break;
}
retry_count++;
}
if (rc == -1) {
printf("%s: AXI CLK Trigger timeout, Ethernet is not enabled!\n",
__func__);
return -1;
}
/* Disable Access to CCU registers */
writel(WR_ACCESS_PASSWORD, WR_ACCESS_ADDR);
return rc;
}
arch/arm/cpu/armv7/cache_v7.c
-6
View File
@@ -6,7 +6,6 @@
*/
#include <cpu_func.h>
#include <asm/cache.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <asm/armv7.h>
#include <asm/utils.h>
@@ -210,8 +209,3 @@ __weak void v7_outer_cache_flush_all(void) {}
__weak void v7_outer_cache_inval_all(void) {}
__weak void v7_outer_cache_flush_range(u32 start, u32 end) {}
__weak void v7_outer_cache_inval_range(u32 start, u32 end) {}
int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
{
return -ENOSYS;
}
arch/arm/cpu/armv7/exception_level.c
+4 -4
View File
@@ -11,9 +11,9 @@
#include <bootm.h>
#include <cpu_func.h>
#include <log.h>
#include <setjmp.h>
#include <asm/armv7.h>
#include <asm/secure.h>
#include <asm/setjmp.h>
/**
* entry_non_secure() - entry point when switching to non-secure mode
@@ -24,7 +24,7 @@
*
* @non_secure_jmp: jump buffer for restoring stack and registers
*/
static void entry_non_secure(jmp_buf non_secure_jmp)
static void entry_non_secure(struct jmp_buf_data *non_secure_jmp)
{
dcache_enable();
debug("Reached non-secure mode\n");
@@ -42,10 +42,10 @@ static void entry_non_secure(jmp_buf non_secure_jmp)
void switch_to_non_secure_mode(void)
{
static bool is_nonsec;
jmp_buf non_secure_jmp;
struct jmp_buf_data non_secure_jmp;
if (armv7_boot_nonsec() && !is_nonsec) {
if (setjmp(non_secure_jmp))
if (setjmp(&non_secure_jmp))
return;
dcache_disable(); /* flush cache before switch to HYP */
armv7_init_nonsec();
arch/arm/cpu/armv7/lowlevel_init.S
+2 -2
View File
@@ -26,8 +26,8 @@ WEAK(lowlevel_init)
/*
* Setup a temporary stack. Global data is not available yet.
*/
#if CONFIG_IS_ENABLED(HAVE_INIT_STACK)
ldr sp, =CONFIG_VAL(STACK)
#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr sp, =CONFIG_SPL_STACK
#else
ldr sp, =SYS_INIT_SP_ADDR
#endif
arch/arm/cpu/armv7/ls102xa/Kconfig
-1
View File
@@ -1,6 +1,5 @@
config ARCH_LS1021A
bool
select ARCH_MISC_INIT if FSL_CAAM
select FSL_DEVICE_DISABLE
select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI
select LS102XA_STREAM_ID
arch/arm/cpu/armv7/start.S
+2 -4
View File
@@ -182,8 +182,6 @@ saved_args:
.word 0
.endr
END(saved_args)
.section .text
#endif
#ifdef CONFIG_ARMV7_LPAE
@@ -281,8 +279,8 @@ ENTRY(cpu_init_cp15)
orr r2, r4, r2 @ r2 has combined CPU variant + revision
/* Early stack for ERRATA that needs into call C code */
#if CONFIG_IS_ENABLED(HAVE_INIT_STACK)
ldr r0, =CONFIG_VAL(STACK)
#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr r0, =(CONFIG_SPL_STACK)
#else
ldr r0, =(SYS_INIT_SP_ADDR)
#endif
arch/arm/cpu/armv7m/cache.c
-6
View File
@@ -11,7 +11,6 @@
#include <asm/cache.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/errno.h>
/* Cache maintenance operation registers */
@@ -371,8 +370,3 @@ void enable_caches(void)
dcache_enable();
#endif
}
int __weak pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
{
return -ENOSYS;
}
arch/arm/cpu/armv7m/cpu.c
+1 -1
View File
@@ -57,7 +57,7 @@ void reset_cpu(void)
| V7M_AIRCR_SYSRESET, &V7M_SCB->aircr);
}
void spl_perform_arch_fixups(struct spl_image_info *spl_image)
void spl_perform_fixups(struct spl_image_info *spl_image)
{
spl_image->entry_point |= 0x1;
}
arch/arm/cpu/armv7m/start.S
+7 -13
View File
@@ -4,19 +4,13 @@
* Kamil Lulko, <kamil.lulko@gmail.com>
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
/*
* Startup code (reset vector)
*/
ENTRY(reset)
W(b) _main @ Jump to _main (C runtime crt0.S)
ENDPROC(reset)
.globl reset
.type reset, %function
reset:
W(b) _main
/*
* Setup CPU for C runtime
*/
ENTRY(c_runtime_cpu_setup)
mov pc, lr @ Jump back to caller
ENDPROC(c_runtime_cpu_setup)
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
mov pc, lr
arch/arm/cpu/armv8/Kconfig
-8
View File
@@ -4,14 +4,6 @@ config CMO_BY_VA_ONLY
bool "Force cache maintenance to be exclusively by VA"
depends on !SYS_DISABLE_DCACHE_OPS
config ARMV8_CNTFRQ_BROKEN
bool "Fix broken ARMv8 generic timer"
depends on SYS_ARCH_TIMER
help
Say Y here if U-Boot depends on a prior stage bootloader, which
does not set the CNTFRQ_EL0 frequency, and its not possible to
set it from U-Boot either.
config ARMV8_SPL_EXCEPTION_VECTORS
bool "Install crash dump exception vectors"
depends on SPL
arch/arm/cpu/armv8/Makefile
+2 -4
View File
@@ -9,7 +9,7 @@ obj-y += cpu.o
ifndef CONFIG_$(PHASE_)TIMER
obj-$(CONFIG_SYS_ARCH_TIMER) += generic_timer.o
endif
ifndef CONFIG_$(PHASE_)SYS_DCACHE_OFF
ifndef CONFIG_$(XPL_)SYS_DCACHE_OFF
obj-y += cache_v8.o
obj-y += cache.o
endif
@@ -33,7 +33,7 @@ obj-$(CONFIG_ACPI_PARKING_PROTOCOL) += acpi_park_v8.o
else
obj-$(CONFIG_ARCH_SUNXI) += fel_utils.o
endif
obj-$(CONFIG_$(PHASE_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o
obj-$(CONFIG_$(XPL_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o
ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_SPL_RECOVER_DATA_SECTION) += spl_data.o
@@ -46,5 +46,3 @@ obj-$(CONFIG_TARGET_BCMNS3) += bcmns3/
obj-$(CONFIG_XEN) += xen/
obj-$(CONFIG_ARMV8_CE_SHA1) += sha1_ce_glue.o sha1_ce_core.o
obj-$(CONFIG_ARMV8_CE_SHA256) += sha256_ce_glue.o sha256_ce_core.o
obj-$(CONFIG_SYSINFO_SMBIOS) += sysinfo.o
arch/arm/cpu/armv8/cache_v8.c
+38 -153
View File
@@ -14,7 +14,6 @@
#include <asm/global_data.h>
#include <asm/system.h>
#include <asm/armv8/mmu.h>
#include <linux/errno.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -58,54 +57,6 @@ static int get_effective_el(void)
return el;
}
int mem_map_from_dram_banks(unsigned int index, unsigned int len, u64 attrs)
{
unsigned int i;
if (index + CONFIG_NR_DRAM_BANKS >= len) {
log_err("%s: Provided mem_map array has insufficient size for DRAM entries\n",
__func__);
return -ENOMEM;
}
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
mem_map[index].virt = gd->bd->bi_dram[i].start;
mem_map[index].phys = gd->bd->bi_dram[i].start;
mem_map[index].size = gd->bd->bi_dram[i].size;
mem_map[index].attrs = attrs;
index++;
}
memset(&mem_map[index], 0, sizeof(mem_map[index]));
return 0;
}
int mmu_unmap_reserved_mem(const char *name, bool check_nomap)
{
void *fdt = (void *)gd->fdt_blob;
char node_path[128];
fdt_addr_t addr;
fdt_size_t size;
int ret;
snprintf(node_path, sizeof(node_path), "/reserved-memory/%s", name);
ret = fdt_path_offset(fdt, node_path);
if (ret < 0)
return ret;
if (check_nomap && !fdtdec_get_bool(fdt, ret, "no-map"))
return -EINVAL;
addr = fdtdec_get_addr_size(fdt, ret, "reg", &size);
if (addr == FDT_ADDR_T_NONE)
return -1;
mmu_change_region_attr_nobreak(addr, size, PTE_TYPE_FAULT);
return 0;
}
u64 get_tcr(u64 *pips, u64 *pva_bits)
{
int el = get_effective_el();
@@ -470,7 +421,7 @@ static int count_ranges(void)
return count;
}
#define ALL_ATTRS (3 << 8 | PMD_ATTRMASK)
#define ALL_ATTRS (3 << 8 | PMD_ATTRINDX_MASK)
#define PTE_IS_TABLE(pte, level) (pte_type(&(pte)) == PTE_TYPE_TABLE && (level) < 3)
enum walker_state {
@@ -617,24 +568,6 @@ static void pretty_print_table_attrs(u64 pte)
static void pretty_print_block_attrs(u64 pte)
{
u64 attrs = pte & PMD_ATTRINDX_MASK;
u64 perm_attrs = pte & PMD_ATTRMASK;
char mem_attrs[16] = { 0 };
int cnt = 0;
if (perm_attrs & PTE_BLOCK_PXN)
cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "PXN ");
if (perm_attrs & PTE_BLOCK_UXN) {
if (get_effective_el() == 1)
cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "UXN ");
else
cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "XN ");
}
if (perm_attrs & PTE_BLOCK_RO)
cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "RO");
if (!mem_attrs[0])
snprintf(mem_attrs, sizeof(mem_attrs), "RWX ");
printf(" | %-10s", mem_attrs);
switch (attrs) {
case PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE):
@@ -680,7 +613,6 @@ static void print_pte(u64 pte, int level)
{
if (PTE_IS_TABLE(pte, level)) {
printf(" %-5s", "Table");
printf(" %-12s", "|");
pretty_print_table_attrs(pte);
} else {
pretty_print_pte_type(pte);
@@ -710,9 +642,9 @@ static bool pagetable_print_entry(u64 start_attrs, u64 end, int va_bits, int lev
printf("%*s", indent * 2, "");
if (PTE_IS_TABLE(start_attrs, level))
printf("[%#016llx]%19s", _addr, "");
printf("[%#011llx]%14s", _addr, "");
else
printf("[%#016llx - %#016llx]", _addr, end);
printf("[%#011llx - %#011llx]", _addr, end);
printf("%*s | ", (3 - level) * 2, "");
print_pte(start_attrs, level);
@@ -878,21 +810,22 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
void dcache_enable(void)
{
/* The data cache is not active unless the mmu is enabled */
if (!mmu_status())
if (!(get_sctlr() & CR_M)) {
invalidate_dcache_all();
__asm_invalidate_tlb_all();
mmu_setup();
}
/* Set up page tables only once (it is done also by mmu_setup()) */
if (!gd->arch.tlb_fillptr)
setup_all_pgtables();
invalidate_dcache_all();
__asm_invalidate_tlb_all();
set_sctlr(get_sctlr() | CR_C);
}
void dcache_disable(void)
{
unsigned long sctlr;
uint32_t sctlr;
sctlr = get_sctlr();
@@ -1019,34 +952,6 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
flush_dcache_range(real_start, real_start + real_size);
}
void mmu_change_region_attr_nobreak(phys_addr_t addr, size_t siz, u64 attrs)
{
int level;
u64 r, size, start;
/*
* Loop through the address range until we find a page granule that fits
* our alignment constraints and set the new permissions
*/
start = addr;
size = siz;
while (size > 0) {
for (level = 1; level < 4; level++) {
/* Set PTE to new attributes */
r = set_one_region(start, size, attrs, true, level);
if (r) {
/* PTE successfully updated */
size -= r;
start += r;
break;
}
}
}
flush_dcache_range(gd->arch.tlb_addr,
gd->arch.tlb_addr + gd->arch.tlb_size);
__asm_invalidate_tlb_all();
}
/*
* Modify MMU table for a region with updated PXN/UXN/Memory type/valid bits.
* The procecess is break-before-make. The target region will be marked as
@@ -1081,47 +986,27 @@ void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs)
gd->arch.tlb_addr + gd->arch.tlb_size);
__asm_invalidate_tlb_all();
mmu_change_region_attr_nobreak(addr, siz, attrs);
}
int pgprot_set_attrs(phys_addr_t addr, size_t size, enum pgprot_attrs perm)
{
u64 attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE | PTE_TYPE_VALID;
switch (perm) {
case MMU_ATTR_RO:
/*
* get_effective_el() will return 1 if
* - Running in EL1 so we assume an EL1 translation regime
* with HCR_EL2.{NV, NV1} != {1,1}
* - Running in EL2 with HCR_EL2.E2H = 1 so we assume an
* EL2&0 translation regime. Since we don't have accesses
* from EL0 we don't have to check HCR_EL2.TGE
*
* Both of these requires PXN to be set
*/
if (get_effective_el() == 1)
attrs |= PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_RO;
else
attrs |= PTE_BLOCK_UXN | PTE_BLOCK_RO;
break;
case MMU_ATTR_RX:
attrs |= PTE_BLOCK_RO;
break;
case MMU_ATTR_RW:
if (get_effective_el() == 1)
attrs |= PTE_BLOCK_PXN | PTE_BLOCK_UXN;
else
attrs |= PTE_BLOCK_UXN;
break;
default:
log_err("Unknown attribute %d\n", perm);
return -EINVAL;
/*
* Loop through the address range until we find a page granule that fits
* our alignment constraints, then set it to the new cache attributes
*/
start = addr;
size = siz;
while (size > 0) {
for (level = 1; level < 4; level++) {
/* Set PTE to new attributes */
r = set_one_region(start, size, attrs, true, level);
if (r) {
/* PTE successfully updated */
size -= r;
start += r;
break;
}
}
}
mmu_change_region_attr_nobreak(addr, size, attrs);
return 0;
flush_dcache_range(gd->arch.tlb_addr,
gd->arch.tlb_addr + gd->arch.tlb_size);
__asm_invalidate_tlb_all();
}
#else /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
@@ -1181,6 +1066,11 @@ int icache_status(void)
return (get_sctlr() & CR_I) != 0;
}
int mmu_status(void)
{
return (get_sctlr() & CR_M) != 0;
}
void invalidate_icache_all(void)
{
__asm_invalidate_icache_all();
@@ -1202,17 +1092,17 @@ int icache_status(void)
return 0;
}
int mmu_status(void)
{
return 0;
}
void invalidate_icache_all(void)
{
}
#endif /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
int mmu_status(void)
{
return (get_sctlr() & CR_M) != 0;
}
/*
* Enable dCache & iCache, whether cache is actually enabled
* depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF
@@ -1222,8 +1112,3 @@ void __weak enable_caches(void)
icache_enable();
dcache_enable();
}
void arch_dump_mem_attrs(void)
{
dump_pagetable(gd->arch.tlb_addr, get_tcr(NULL, NULL));
}
arch/arm/cpu/armv8/cpu.c
-5
View File
@@ -94,8 +94,3 @@ void armv8_setup_psci(void)
secure_ram_addr(psci_arch_init)();
}
#endif
void allow_unaligned(void)
{
set_sctlr(get_sctlr() & ~CR_A);
}
arch/arm/cpu/armv8/exception_level.c
+4 -4
View File
@@ -11,8 +11,8 @@
#include <bootm.h>
#include <cpu_func.h>
#include <log.h>
#include <setjmp.h>
#include <asm/cache.h>
#include <asm/setjmp.h>
/**
* entry_non_secure() - entry point when switching to non-secure mode
@@ -23,7 +23,7 @@
*
* @non_secure_jmp: jump buffer for restoring stack and registers
*/
static void entry_non_secure(jmp_buf non_secure_jmp)
static void entry_non_secure(struct jmp_buf_data *non_secure_jmp)
{
dcache_enable();
debug("Reached non-secure mode\n");
@@ -42,11 +42,11 @@ static void entry_non_secure(jmp_buf non_secure_jmp)
*/
void switch_to_non_secure_mode(void)
{
jmp_buf non_secure_jmp;
struct jmp_buf_data non_secure_jmp;
/* On AArch64 we need to make sure we call our payload in < EL3 */
if (current_el() == 3) {
if (setjmp(non_secure_jmp))
if (setjmp(&non_secure_jmp))
return;
dcache_disable(); /* flush cache before switch to EL2 */
arch/arm/cpu/armv8/fel_utils.S
+5 -16
View File
@@ -41,11 +41,10 @@ ENTRY(return_to_fel)
str w2, [x1]
ldr w0, =0xfa50392f // CPU hotplug magic
#if defined(CONFIG_MACH_SUN50I_H616) || defined(CONFIG_MACH_SUN50I_A133) || \
defined(CONFIG_MACH_SUN55I_A523)
#ifdef CONFIG_MACH_SUN50I_H616
ldr w2, =(SUNXI_R_CPUCFG_BASE + 0x1c0)
str w0, [x2], #0x4
#elif defined(CONFIG_MACH_SUN50I_H6)
#elif CONFIG_MACH_SUN50I_H6
ldr w2, =(SUNXI_RTC_BASE + 0x1b8) // BOOT_CPU_HP_FLAG_REG
str w0, [x2], #0x4
#else
@@ -64,30 +63,20 @@ ENTRY(return_to_fel)
1: wfi
b 1b
fel_stash_addr: // must immediately precede back_in_32:
.word 0x00000000 // receives fel_stash addr, by AA64 code above
/* AArch32 code to restore the state from fel_stash and return back to FEL. */
back_in_32:
.word 0xe51f000c // ldr r0, [pc, #-12] ; load fel_stash address
.word 0xe59f0028 // ldr r0, [pc, #40] ; load fel_stash address
.word 0xe5901008 // ldr r1, [r0, #8]
.word 0xe129f001 // msr CPSR_fc, r1
.word 0xf57ff06f // isb
.word 0xe590d000 // ldr sp, [r0]
.word 0xe590e004 // ldr lr, [r0, #4]
.word 0xe5901014 // ldr r1, [r0, #20]
.word 0xe121f301 // msr SP_irq, r1
.word 0xe5901010 // ldr r1, [r0, #16]
.word 0xee0c1f10 // mcr 15, 0, r1, cr12, cr0, {0} ; VBAR
.word 0xe590100c // ldr r1, [r0, #12]
.word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR
.word 0xf57ff06f // isb
#ifdef CONFIG_MACH_SUN55I_A523
.word 0xe5901018 // ldr r1, [r0, #24]
.word 0xee041f16 // mcr 15, 0, r1, cr4, cr6, {0}; ICC_PMR
.word 0xe590101c // ldr r1, [r0, #28]
.word 0xee0c1ffc // mcr 15, 0, r1, cr12, cr12, {7}; ICC_IGRPEN1
#endif
.word 0xe12fff1e // bx lr ; return to FEL
fel_stash_addr:
.word 0x00000000 // receives fel_stash addr, by AA64 code above
ENDPROC(return_to_fel)
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+3 -4
View File
@@ -77,11 +77,11 @@ config ARCH_LS1043A
select SYS_FSL_DDR_BE
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008850 if !TFABOOT
select SYS_FSL_ERRATUM_A008997 if USB
select SYS_FSL_ERRATUM_A009008 if USB
select SYS_FSL_ERRATUM_A008997
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009660 if !TFABOOT
select SYS_FSL_ERRATUM_A009663 if !TFABOOT
select SYS_FSL_ERRATUM_A009798 if USB
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A009942 if !TFABOOT
select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE
select SYS_FSL_ERRATUM_A010539
@@ -328,7 +328,6 @@ config ARCH_LX2160A
config FSL_LSCH2
bool
select ARCH_MISC_INIT if FSL_CAAM
select SKIP_LOWLEVEL_INIT
select SYS_FSL_CCSR_GUR_BE
select SYS_FSL_CCSR_SCFG_BE
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+1 -1
View File
@@ -802,7 +802,7 @@ enum boot_src get_boot_src(void)
int mmc_get_env_dev(void)
{
enum boot_src src = get_boot_src();
int dev = CONFIG_ENV_MMC_DEVICE_INDEX;
int dev = CONFIG_SYS_MMC_ENV_DEV;
switch (src) {
case BOOT_SOURCE_SD_MMC:
arch/arm/cpu/armv8/fsl-layerscape/fdt.c
-1
View File
@@ -7,7 +7,6 @@
#include <config.h>
#include <clock_legacy.h>
#include <efi_loader.h>
#include <env.h>
#include <log.h>
#include <asm/cache.h>
#include <linux/libfdt.h>
arch/arm/cpu/armv8/generic_timer.c
-4
View File
@@ -19,10 +19,6 @@ DECLARE_GLOBAL_DATA_PTR;
unsigned long notrace get_tbclk(void)
{
unsigned long cntfrq;
if (IS_ENABLED(CONFIG_ARMV8_CNTFRQ_BROKEN) && gd->arch.timer_rate_hz)
return gd->arch.timer_rate_hz;
asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq));
return cntfrq;
}
arch/arm/cpu/armv8/spin_table.c
-1
View File
@@ -4,7 +4,6 @@
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*/
#include <errno.h>
#include <linux/libfdt.h>
#include <asm/spin_table.h>
arch/arm/cpu/armv8/spl_data.c
+4 -9
View File
@@ -5,28 +5,23 @@
#include <spl.h>
char __data_start[0] __section(".__data_start");
char __data_save_start[0] __section(".__data_save_start");
char __data_save_end[0] __section(".__data_save_end");
u32 cold_reboot_flag = 1;
u32 __weak reset_flag(u32 flag)
{
return flag;
}
void spl_save_restore_data(void)
{
u32 data_size = __data_save_end - __data_save_start;
cold_reboot_flag = reset_flag(cold_reboot_flag);
if (cold_reboot_flag == 1) {
/* Save data section to data_save section */
memcpy(__data_save_start, __data_start, data_size);
memcpy(__data_save_start, __data_save_start - data_size,
data_size);
} else {
/* Restore the data_save section to data section */
memcpy(__data_start, __data_save_start, data_size);
memcpy(__data_save_start - data_size, __data_save_start,
data_size);
}
cold_reboot_flag++;
arch/arm/cpu/armv8/start.S
+12 -10
View File
@@ -334,9 +334,6 @@ WEAK(lowlevel_init)
/*
* All slaves will enter EL2 and optionally EL1.
*/
#if defined(CONFIG_ARMV8_PSCI) && !defined(CONFIG_XPL_BUILD)
bl psci_setup_vectors
#endif
adr x4, lowlevel_in_el2
ldr x5, =ES_TO_AARCH64
bl armv8_switch_to_el2
@@ -387,18 +384,23 @@ ENDPROC(c_runtime_cpu_setup)
WEAK(save_boot_params)
#if (IS_ENABLED(CONFIG_BLOBLIST))
/* Calculate the PC-relative address of saved_args */
adrp x9, saved_args
add x9, x9, :lo12:saved_args
stp x0, x1, [x9]
stp x2, x3, [x9, #16]
adr x9, saved_args_offset
ldr w10, saved_args_offset
add x9, x9, w10, sxtw
stp x0, x1, [x9]
stp x2, x3, [x9, #16]
#endif
b save_boot_params_ret /* back to my caller */
ENDPROC(save_boot_params)
#if (IS_ENABLED(CONFIG_BLOBLIST))
.section .data
.align 2
.global saved_args
saved_args_offset:
.long saved_args - . /* offset from current code to save_args */
.section .data
.align 2
.global saved_args
saved_args:
.rept 4
.dword 0
arch/arm/cpu/armv8/sysinfo.c
-292
View File
@@ -1,292 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2024 Linaro Limited
* Author: Raymond Mao <raymond.mao@linaro.org>
*/
#include <dm.h>
#include <smbios_plat.h>
#include <stdio.h>
#include <sysinfo.h>
union ccsidr_el1 {
struct {
u64 linesize:3;
u64 associativity:10;
u64 numsets:15;
u64 unknown:4;
u64 reserved:32;
} no_ccidx;
struct {
u64 linesize:3;
u64 associativity:21;
u64 reserved1:8;
u64 numsets:24;
u64 reserved2:8;
} ccidx_aarch64;
struct {
u64 linesize:3;
u64 associativity:21;
u64 reserved:8;
u64 unallocated:32;
} ccidx_aarch32;
u64 data;
};
union midr_el1 {
struct {
u64 revision:4;
u64 partnum:12;
u64 architecture:4;
u64 variant:4;
u64 implementer:8;
u64 reserved:32;
} fields;
u64 data;
};
enum {
CACHE_NONE,
CACHE_INST_ONLY,
CACHE_DATA_ONLY,
CACHE_INST_WITH_DATA,
CACHE_UNIFIED,
};
enum {
CACHE_ASSOC_DIRECT_MAPPED = 1,
CACHE_ASSOC_2WAY = 2,
CACHE_ASSOC_4WAY = 4,
CACHE_ASSOC_8WAY = 8,
CACHE_ASSOC_16WAY = 16,
CACHE_ASSOC_12WAY = 12,
CACHE_ASSOC_24WAY = 24,
CACHE_ASSOC_32WAY = 32,
CACHE_ASSOC_48WAY = 48,
CACHE_ASSOC_64WAY = 64,
CACHE_ASSOC_20WAY = 20,
};
enum {
VENDOR_RESERVED = 0,
VENDOR_ARM = 0x41,
VENDOR_BROADCOM = 0x42,
VENDOR_CAVIUM = 0x43,
VENDOR_DEC = 0x44,
VENDOR_FUJITSU = 0x46,
VENDOR_INFINEON = 0x49,
VENDOR_FREESCALE = 0x4d,
VENDOR_NVIDIA = 0x4e,
VENDOR_AMCC = 0x50,
VENDOR_QUALCOMM = 0x51,
VENDOR_MARVELL = 0x56,
VENDOR_INTEL = 0x69,
VENDOR_AMPERE = 0xc0,
};
/*
* TODO:
* To support ARMv8.3, we need to read "CCIDX, bits [23:20]" from
* ID_AA64MMFR2_EL1 to get the format of CCSIDR_EL1:
*
* 0b0000 - 32-bit format implemented for all levels of the CCSIDR_EL1.
* 0b0001 - 64-bit format implemented for all levels of the CCSIDR_EL1.
*
* Here we assume to use CCSIDR_EL1 in no CCIDX layout:
* NumSets, bits [27:13]: (Number of sets in cache) - 1
* Associativity, bits [12:3]: (Associativity of cache) - 1
* LineSize, bits [2:0]: (Log2(Number of bytes in cache line)) - 4
*/
int sysinfo_get_cache_info(u8 level, struct cache_info *cinfo)
{
u64 clidr_el1;
u32 csselr_el1;
u32 num_sets;
union ccsidr_el1 creg;
int cache_type;
sysinfo_cache_info_default(cinfo);
/* Read CLIDR_EL1 */
asm volatile("mrs %0, clidr_el1" : "=r" (clidr_el1));
debug("CLIDR_EL1: 0x%llx\n", clidr_el1);
cache_type = (clidr_el1 >> (3 * level)) & 0x7;
if (cache_type == CACHE_NONE) /* level does not exist */
return -1;
switch (cache_type) {
case CACHE_INST_ONLY:
cinfo->cache_type = SMBIOS_CACHE_SYSCACHE_TYPE_INST;
break;
case CACHE_DATA_ONLY:
cinfo->cache_type = SMBIOS_CACHE_SYSCACHE_TYPE_DATA;
break;
case CACHE_UNIFIED:
cinfo->cache_type = SMBIOS_CACHE_SYSCACHE_TYPE_UNIFIED;
break;
case CACHE_INST_WITH_DATA:
cinfo->cache_type = SMBIOS_CACHE_SYSCACHE_TYPE_OTHER;
break;
default:
cinfo->cache_type = SMBIOS_CACHE_SYSCACHE_TYPE_UNKNOWN;
break;
}
/* Select cache level */
csselr_el1 = (level << 1);
asm volatile("msr csselr_el1, %0" : : "r" ((u64)csselr_el1));
/* Read CCSIDR_EL1 */
asm volatile("mrs %0, ccsidr_el1" : "=r" (creg.data));
debug("CCSIDR_EL1 (Level %d): 0x%llx\n", level + 1, creg.data);
/* Extract cache size and associativity */
cinfo->line_size = 1 << (creg.no_ccidx.linesize + 4);
/* Map the associativity value */
switch (creg.no_ccidx.associativity + 1) {
case CACHE_ASSOC_DIRECT_MAPPED:
cinfo->associativity = SMBIOS_CACHE_ASSOC_DMAPPED;
break;
case CACHE_ASSOC_2WAY:
cinfo->associativity = SMBIOS_CACHE_ASSOC_2WAY;
break;
case CACHE_ASSOC_4WAY:
cinfo->associativity = SMBIOS_CACHE_ASSOC_4WAY;
break;
case CACHE_ASSOC_8WAY:
cinfo->associativity = SMBIOS_CACHE_ASSOC_8WAY;
break;
case CACHE_ASSOC_16WAY:
cinfo->associativity = SMBIOS_CACHE_ASSOC_16WAY;
break;
case CACHE_ASSOC_12WAY:
cinfo->associativity = SMBIOS_CACHE_ASSOC_12WAY;
break;
case CACHE_ASSOC_24WAY:
cinfo->associativity = SMBIOS_CACHE_ASSOC_24WAY;
break;
case CACHE_ASSOC_32WAY:
cinfo->associativity = SMBIOS_CACHE_ASSOC_32WAY;
break;
case CACHE_ASSOC_48WAY:
cinfo->associativity = SMBIOS_CACHE_ASSOC_48WAY;
break;
case CACHE_ASSOC_64WAY:
cinfo->associativity = SMBIOS_CACHE_ASSOC_64WAY;
break;
case CACHE_ASSOC_20WAY:
cinfo->associativity = SMBIOS_CACHE_ASSOC_20WAY;
break;
default:
cinfo->associativity = SMBIOS_CACHE_ASSOC_UNKNOWN;
break;
}
num_sets = creg.no_ccidx.numsets + 1;
/* Size in KB */
cinfo->max_size = (cinfo->associativity * num_sets * cinfo->line_size) /
1024;
debug("L%d Cache:\n", level + 1);
debug("Number of bytes in cache line:%u\n", cinfo->line_size);
debug("Associativity of cache:%u\n", cinfo->associativity);
debug("Number of sets in cache:%u\n", num_sets);
debug("Cache size in KB:%u\n", cinfo->max_size);
cinfo->inst_size = cinfo->max_size;
/*
* Below fields with common values are placed under DT smbios node
* socket-design, config
* Other fields are typically specific to the implementation of the ARM
* processor by the silicon vendor:
* supp_sram_type, curr_sram_type, speed, err_corr_type
*/
return 0;
}
int sysinfo_get_processor_info(struct processor_info *pinfo)
{
u64 mpidr, core_count;
union midr_el1 midr;
/* Read the MIDR_EL1 register */
asm volatile("mrs %0, MIDR_EL1" : "=r"(midr.data));
/* Read the MPIDR_EL1 register */
asm volatile("mrs %0, MPIDR_EL1" : "=r"(mpidr));
debug("MIDR: 0x%016llx\n", midr.data);
debug("MPIDR: 0x%016llx\n", mpidr);
debug("CPU Implementer: 0x%02x\n", midr.fields.implementer);
switch (midr.fields.implementer) {
case VENDOR_ARM:
pinfo->manufacturer = "ARM Limited";
break;
case VENDOR_BROADCOM:
pinfo->manufacturer = "Broadcom Corporation";
break;
case VENDOR_CAVIUM:
pinfo->manufacturer = "Cavium Inc";
break;
case VENDOR_DEC:
pinfo->manufacturer = "Digital Equipment Corporation";
break;
case VENDOR_FUJITSU:
pinfo->manufacturer = "Fujitsu Ltd";
break;
case VENDOR_INFINEON:
pinfo->manufacturer = "Infineon Technologies AG";
break;
case VENDOR_FREESCALE:
pinfo->manufacturer = "Freescale Semiconductor Inc";
break;
case VENDOR_NVIDIA:
pinfo->manufacturer = "NVIDIA Corporation";
break;
case VENDOR_AMCC:
pinfo->manufacturer =
"Applied Micro Circuits Corporation";
break;
case VENDOR_QUALCOMM:
pinfo->manufacturer = "Qualcomm Inc";
break;
case VENDOR_MARVELL:
pinfo->manufacturer = "Marvell International Ltd";
break;
case VENDOR_INTEL:
pinfo->manufacturer = "Intel Corporation";
break;
case VENDOR_AMPERE:
pinfo->manufacturer = "Ampere Computing";
break;
default:
pinfo->manufacturer = "Unknown";
break;
}
debug("CPU part number: 0x%x\n", midr.fields.partnum);
debug("CPU revision: 0x%x\n", midr.fields.revision);
debug("CPU architecture: 0x%x\n", midr.fields.architecture);
debug("CPU variant: 0x%x\n", midr.fields.variant);
/* Extract number of cores */
core_count = (mpidr >> 0) & 0xFF;
pinfo->core_count = core_count + 1;
debug("CPU Core Count: %d\n", pinfo->core_count);
pinfo->core_enabled = pinfo->core_count;
pinfo->characteristics = SMBIOS_PROCESSOR_64BIT |
SMBIOS_PROCESSOR_ARM64_SOCID;
if (pinfo->core_count > 1)
pinfo->characteristics |= SMBIOS_PROCESSOR_MULTICORE;
/*
* Below fields with common values are placed under DT smbios node
* version, processor-type, processor-status, upgrade, family2,
* socket-design, serial, asset-tag, part-number
*/
return 0;
}
arch/arm/cpu/armv8/transition.S
-8
View File
@@ -9,16 +9,8 @@
#include <linux/linkage.h>
#include <asm/macro.h>
.pushsection .text.armv8_switch_to_el2_prep, "ax"
WEAK(armv8_switch_to_el2_prep)
ret
ENDPROC(armv8_switch_to_el2_prep)
.popsection
.pushsection .text.armv8_switch_to_el2, "ax"
ENTRY(armv8_switch_to_el2)
bl armv8_switch_to_el2_prep
nop
switch_el x6, 1f, 0f, 0f
0:
cmp x5, #ES_TO_AARCH64
arch/arm/cpu/armv8/u-boot-spl.lds
-1
View File
@@ -37,7 +37,6 @@ SECTIONS
.data : {
. = ALIGN(8);
*(.__data_start)
*(.data*)
} >.sram
arch/arm/cpu/armv8/u-boot.lds
+20 -41
View File
@@ -36,18 +36,9 @@ SECTIONS
__efi_runtime_stop = .;
}
#ifdef CONFIG_MMU_PGPROT
.text_rest ALIGN(CONSTANT(COMMONPAGESIZE)) :
#else
.text_rest :
#endif
{
__text_start = .;
*(.text*)
#ifdef CONFIG_MMU_PGPROT
. = ALIGN(CONSTANT(COMMONPAGESIZE));
#endif
__text_end = .;
}
#ifdef CONFIG_ARMV8_PSCI
@@ -106,6 +97,24 @@ SECTIONS
LONG(0x1d1071c); /* Must output something to reset LMA */
}
#endif
. = ALIGN(8);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(8);
.data : {
*(.data*)
}
. = ALIGN(8);
. = .;
. = ALIGN(8);
__u_boot_list : {
KEEP(*(SORT(__u_boot_list*)));
}
.efi_runtime_rel : {
__efi_runtime_rel_start = .;
*(.rel*.efi_runtime)
@@ -113,36 +122,10 @@ SECTIONS
__efi_runtime_rel_stop = .;
}
#ifdef CONFIG_MMU_PGPROT
.rodata ALIGN(CONSTANT(COMMONPAGESIZE)): {
#else
.rodata ALIGN(8) : {
#endif
__start_rodata = .;
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
__u_boot_list ALIGN(8) : {
KEEP(*(SORT(__u_boot_list*)));
#ifdef CONFIG_MMU_PGPROT
. = ALIGN(CONSTANT(COMMONPAGESIZE));
#endif
__end_rodata = .;
}
#ifdef CONFIG_MMU_PGPROT
.data ALIGN(CONSTANT(COMMONPAGESIZE)) : {
#else
.data ALIGN(8) : {
#endif
__start_data = .;
*(.data*)
}
. = ALIGN(8);
__image_copy_end = .;
.rela.dyn ALIGN(8) : {
.rela.dyn : {
__rel_dyn_start = .;
*(.rela*)
__rel_dyn_end = .;
@@ -153,15 +136,11 @@ SECTIONS
/*
* arch/arm/lib/crt0_64.S assumes __bss_start - __bss_end % 8 == 0
*/
.bss ADDR(.rela.dyn) (OVERLAY) : {
.bss ALIGN(8) : {
__bss_start = .;
*(.bss*)
. = ALIGN(8);
__bss_end = .;
#ifdef CONFIG_MMU_PGPROT
. = ALIGN(CONSTANT(COMMONPAGESIZE));
#endif
__end_data = .;
}
/DISCARD/ : { *(.dynsym) }
arch/arm/cpu/u-boot-spl.lds
+1 -2
View File
@@ -53,14 +53,13 @@ SECTIONS
__rel_dyn_end = .;
}
. = ALIGN(8);
_image_binary_end = .;
_end = .;
.bss __rel_dyn_start (OVERLAY) : {
__bss_start = .;
*(.bss*)
. = ALIGN(8);
. = ALIGN(4);
__bss_end = .;
}
__bss_size = __bss_end - __bss_start;
arch/arm/cpu/u-boot.lds
+22 -13
View File
@@ -153,14 +153,14 @@ SECTIONS
__efi_runtime_rel_stop = .;
}
. = ALIGN(8);
. = ALIGN(4);
__image_copy_end = .;
/*
* if CONFIG_USE_ARCH_MEMSET is not selected __bss_end - __bss_start
* needs to be a multiple of 8 and we overlay .bss with .rel.dyn
* needs to be a multiple of 4 and we overlay .bss with .rel.dyn
*/
.rel.dyn ALIGN(8) : {
.rel.dyn ALIGN(4) : {
__rel_dyn_start = .;
*(.rel*)
__rel_dyn_end = .;
@@ -169,6 +169,15 @@ SECTIONS
_end = .;
_image_binary_end = .;
/*
* Deprecated: this MMU section is used by pxa at present but
* should not be used by new boards/CPUs.
*/
. = ALIGN(4096);
.mmutable : {
*(.mmutable)
}
/*
* These sections occupy the same memory, but their lifetimes do
* not overlap: U-Boot initializes .bss only after applying dynamic
@@ -181,14 +190,14 @@ SECTIONS
__bss_end = .;
}
/DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynbss) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu.hash) }
/DISCARD/ : { *(.gnu*) }
/DISCARD/ : { *(.ARM.exidx*) }
/DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
.dynsym _image_binary_end : { *(.dynsym) }
.dynbss : { *(.dynbss) }
.dynstr : { *(.dynstr*) }
.dynamic : { *(.dynamic*) }
.plt : { *(.plt*) }
.interp : { *(.interp*) }
.gnu.hash : { *(.gnu.hash) }
.gnu : { *(.gnu*) }
.ARM.exidx : { *(.ARM.exidx*) }
.gnu.linkonce.armexidx : { *(.gnu.linkonce.armexidx.*) }
}
arch/arm/dts/Makefile
+126 -54
View File
@@ -52,17 +52,30 @@ dtb-$(CONFIG_MACH_S900) += \
dtb-$(CONFIG_MACH_S700) += \
s700-cubieboard7.dtb
dtb-$(CONFIG_ROCKCHIP_RK3036) += \
rk3036-sdk.dtb
dtb-$(CONFIG_ROCKCHIP_RK3066) += \
rk3066a-mk808.dtb
dtb-$(CONFIG_ROCKCHIP_RK3128) += \
rk3128-evb.dtb
dtb-$(CONFIG_ROCKCHIP_RK3188) += \
rk3188-radxarock.dtb
dtb-$(CONFIG_ROCKCHIP_RK322X) += \
rk3229-evb.dtb
dtb-$(CONFIG_ROCKCHIP_RK3288) += \
rk3288-evb.dtb \
rk3288-firefly.dtb \
rk3288-miqi.dtb \
rk3288-popmetal.dtb \
rk3288-rock2-square.dtb \
rk3288-rock-pi-n8.dtb \
rk3288-tinker.dtb \
rk3288-tinker-s.dtb \
rk3288-veyron-jerry.dtb \
rk3288-veyron-mickey.dtb \
rk3288-veyron-minnie.dtb \
@@ -81,19 +94,13 @@ dtb-$(CONFIG_ARCH_MESON) += \
meson-a1-ad401.dtb
dtb-$(CONFIG_ARCH_TEGRA) += \
tegra20-acer-a500-picasso.dtb \
tegra20-asus-sl101.dtb \
tegra20-asus-tf101.dtb \
tegra20-asus-tf101g.dtb \
tegra20-harmony.dtb \
tegra20-lg-star.dtb \
tegra20-medcom-wide.dtb \
tegra20-motorola-daytona.dtb \
tegra20-motorola-olympus.dtb \
tegra20-paz00.dtb \
tegra20-plutux.dtb \
tegra20-samsung-bose.dtb \
tegra20-samsung-n1.dtb \
tegra20-seaboard.dtb \
tegra20-tec.dtb \
tegra20-trimslice.dtb \
@@ -118,21 +125,14 @@ dtb-$(CONFIG_ARCH_TEGRA) += \
tegra30-lg-p880.dtb \
tegra30-lg-p895.dtb \
tegra30-microsoft-surface-rt.dtb \
tegra30-ouya.dtb \
tegra30-pegatron-chagall.dtb \
tegra30-tec-ng.dtb \
tegra30-wexler-qc750.dtb \
tegra114-asus-tf701t.dtb \
tegra114-dalmore.dtb \
tegra114-microsoft-surface-2-0b.dtb \
tegra114-microsoft-surface-2-13.dtb \
tegra114-nvidia-tegratab.dtb \
tegra124-apalis.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
tegra124-cei-tk1-som.dtb \
tegra124-venice2.dtb \
tegra124-xiaomi-mocha.dtb \
tegra186-p2771-0000-000.dtb \
tegra186-p2771-0000-500.dtb \
tegra210-p2371-0000.dtb \
@@ -275,7 +275,6 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-mini-qspi-x1-stacked.dtb \
zynqmp-mini-qspi-x2-single.dtb \
zynqmp-mini-qspi-x2-stacked.dtb \
zynqmp-binman-mini.dtb \
zynqmp-sc-revB.dtb \
zynqmp-sc-revC.dtb \
zynqmp-sm-k24-revA.dtb \
@@ -309,13 +308,6 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-zc1751-xm017-dc3.dtb \
zynqmp-zc1751-xm018-dc4.dtb \
zynqmp-zc1751-xm019-dc5.dtb
dtb-$(CONFIG_TARGET_ZYNQ_BR) += \
zynq-brcp1_2r.dtb \
zynq-brcp1_1r.dtb \
zynq-brcp1_1r_switch.dtb \
zynq-brsmarc2.dtb \
zynq-brcp150.dtb \
zynq-brcp170.dtb
zynqmp-p-a2197-00-revA-x-prc-01-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-01-revA.dtbo
zynqmp-p-a2197-00-revA-x-prc-02-revA-dtbs := zynqmp-p-a2197-00-revA.dtb zynqmp-p-a2197-00-revA-x-prc-02-revA.dtbo
@@ -328,7 +320,6 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-02-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-03-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-04-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-p-a2197-00-revA-x-prc-05-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-binman.dtb
zynqmp-sc-vek280-revA-dtbs := zynqmp-sc-revB.dtb zynqmp-sc-vek280-revA.dtbo
zynqmp-sc-vek280-revB-dtbs := zynqmp-sc-revC.dtb zynqmp-sc-vek280-revB.dtbo
@@ -379,7 +370,6 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kv-g-revB.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kv-g-revB.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k24-revA-sck-kr-g-revB.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k24-revA-sck-kr-g-revB.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-binman-som.dtb
dtb-$(CONFIG_ARCH_VERSAL) += \
versal-mini.dtb \
@@ -425,7 +415,6 @@ dtb-$(CONFIG_AM33XX) += \
am335x-evm.dtb \
am335x-evmsk.dtb \
am335x-bonegreen.dtb \
am335x-bonegreen-eco.dtb \
am335x-bonegreen-wireless.dtb \
am335x-icev2.dtb \
am335x-pocketbeagle.dtb \
@@ -450,6 +439,7 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \
dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_agilex_socdk.dtb \
socfpga_agilex5_socdk.dtb \
socfpga_arria5_secu1.dtb \
socfpga_arria5_socdk.dtb \
@@ -536,12 +526,67 @@ dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb \
stm32429i-eval.dtb \
stm32f469-disco.dtb
dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \
stm32f769-disco.dtb \
stm32746g-eval.dtb
dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
stm32h743i-eval.dtb \
stm32h750i-art-pi.dtb
dtb-$(CONFIG_MACH_SUNIV) += \
suniv-f1c100s-licheepi-nano.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun4i-a10-ba10-tvbox.dtb \
sun4i-a10-chuwi-v7-cw0825.dtb \
sun4i-a10-cubieboard.dtb \
sun4i-a10-dserve-dsrv9703c.dtb \
sun4i-a10-gemei-g9.dtb \
sun4i-a10-hackberry.dtb \
sun4i-a10-hyundai-a7hd.dtb \
sun4i-a10-inet1.dtb \
sun4i-a10-inet-3f.dtb \
sun4i-a10-inet-3w.dtb
sun4i-a10-inet-3w.dtb \
sun4i-a10-inet97fv2.dtb \
sun4i-a10-inet9f-rev03.dtb \
sun4i-a10-itead-iteaduino-plus.dtb \
sun4i-a10-jesurun-q5.dtb \
sun4i-a10-marsboard.dtb \
sun4i-a10-mini-xplus.dtb \
sun4i-a10-mk802.dtb \
sun4i-a10-mk802ii.dtb \
sun4i-a10-olinuxino-lime.dtb \
sun4i-a10-pcduino.dtb \
sun4i-a10-pcduino2.dtb \
sun4i-a10-pov-protab2-ips9.dtb \
sun4i-a10-topwise-a721.dtb
dtb-$(CONFIG_MACH_SUN5I) += \
sun5i-a10s-auxtek-t003.dtb \
sun5i-a10s-auxtek-t004.dtb \
sun5i-a10s-mk802.dtb \
sun5i-a10s-olinuxino-micro.dtb \
sun5i-a10s-r7-tv-dongle.dtb \
sun5i-a10s-wobo-i5.dtb \
sun5i-a13-ampe-a76.dtb \
sun5i-a13-inet-86vs.dtb
sun5i-a13-difrnce-dit4350.dtb \
sun5i-a13-empire-electronix-d709.dtb \
sun5i-a13-empire-electronix-m712.dtb \
sun5i-a13-hsg-h702.dtb \
sun5i-a13-inet-86vs.dtb \
sun5i-a13-inet-98v-rev2.dtb \
sun5i-a13-licheepi-one.dtb \
sun5i-a13-olinuxino.dtb \
sun5i-a13-olinuxino-micro.dtb \
sun5i-a13-pocketbook-touch-lux-3.dtb \
sun5i-a13-q8-tablet.dtb \
sun5i-a13-utoo-p66.dtb \
sun5i-gr8-chip-pro.dtb \
sun5i-gr8-evb.dtb \
sun5i-r8-chip.dtb
dtb-$(CONFIG_MACH_SUN6I) += \
sun6i-a31-app4-evb1.dtb \
sun6i-a31-colombus.dtb \
@@ -650,6 +695,13 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \
sun8i-r40-oka40i-c.dtb \
sun8i-t3-cqa3t-bv3.dtb \
sun8i-v40-bananapi-m2-berry.dtb
dtb-$(CONFIG_MACH_SUN8I_V3S) += \
sun8i-s3-elimo-initium.dtb \
sun8i-s3-pinecube.dtb \
sun8i-v3-sl631-imx179.dtb \
sun8i-v3s-licheepi-zero.dtb
dtb-$(CONFIG_MACH_SUN8I_R528) += \
sun8i-t113s-mangopi-mq-r-t113.dtb
dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-bananapi-m2-plus.dtb \
sun50i-h5-emlid-neutis-n5-devboard.dtb \
@@ -691,6 +743,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-sopine-baseboard.dtb \
sun50i-a64-teres-i.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb \
sun9i-a80-cx-a99.dtb
dtb-$(CONFIG_VF610) += vf610-colibri-eval-v3.dtb \
@@ -755,6 +809,7 @@ dtb-y += \
imx6dl-riotboard.dtb \
imx6dl-sabreauto.dtb \
imx6dl-sabresd.dtb \
imx6dl-sielaff.dtb \
imx6dl-wandboard-revd1.dtb
endif
@@ -793,6 +848,7 @@ dtb-y += \
imx6q-icore-rqs.dtb \
imx6q-kp.dtb \
imx6q-logicpd.dtb \
imx6q-lxr.dtb \
imx6q-marsboard.dtb \
imx6q-mccmon6.dtb\
imx6q-nitrogen6x.dtb \
@@ -831,7 +887,9 @@ dtb-$(CONFIG_MX6UL) += \
imx6ul-liteboard.dtb \
imx6ul-phytec-segin-ff-rdk-nand.dtb \
imx6ul-pico-hobbit.dtb \
imx6ul-pico-pi.dtb
imx6ul-pico-pi.dtb \
imx6ul-kontron-bl.dtb \
imx6ull-kontron-bl.dtb
dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \
@@ -878,7 +936,8 @@ dtb-$(CONFIG_ARCH_IMX8) += \
fsl-imx8qxp-ai_ml.dtb \
fsl-imx8qxp-colibri.dtb \
fsl-imx8qxp-mek.dtb \
imx8-capricorn-cxg3.dtb \
imx8-deneb.dtb \
imx8-giedi.dtb
dtb-$(CONFIG_ARCH_IMX8ULP) += \
imx8ulp-evk.dtb
@@ -887,6 +946,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-data-modul-edm-sbc.dtb \
imx8mm-icore-mx8mm-ctouch2.dtb \
imx8mm-icore-mx8mm-edimm2.2.dtb \
imx8mm-kontron-bl.dtb \
imx8mm-kontron-bl-osm-s.dtb \
imx8mm-mx8menlo.dtb \
imx8mm-phg.dtb \
imx8mq-cm.dtb \
@@ -908,23 +969,20 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-librem5-r4.dtb
dtb-$(CONFIG_ARCH_IMX9) += \
imx93-11x11-frdm.dtb \
imx93-var-som-symphony.dtb
imx93-var-som-symphony.dtb \
imx93-phyboard-segin.dtb
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1020-evk.dtb \
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
imxrt1020-evk.dtb \
imxrt1170-evk.dtb \
dtb-$(CONFIG_RZA1) += \
r7s72100-genmai.dtb \
r7s72100-gr-peach.dtb
dtb-$(CONFIG_RCAR_GEN5) += \
r8a78000-ironhide.dtb
ifdef CONFIG_RCAR_GEN5
ifdef CONFIG_RCAR_64
DTC_FLAGS += -R 4 -p 0x1000
endif
dtb-$(CONFIG_RZA1) += \
r7s72100-gr-peach.dtb
dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb
dtb-$(CONFIG_TARGET_PM9261) += at91sam9261ek.dtb
@@ -1073,29 +1131,49 @@ dtb-$(CONFIG_BCM6878) += \
dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb
dtb-$(CONFIG_ASPEED_AST2600) += \
ast2600-evb.dtb \
ast2600-sbp1.dtb \
ast2600-x4tf.dtb
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
dtb-$(CONFIG_STM32MP13X) += \
stm32mp135f-dk.dtb
dtb-$(CONFIG_STM32MP15X) += \
stm32mp157a-dk1.dtb \
stm32mp157a-dk1-scmi.dtb \
stm32mp157a-icore-stm32mp1-ctouch2.dtb \
stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
stm32mp157c-dk2.dtb \
stm32mp157c-dk2-scmi.dtb \
stm32mp157c-ed1.dtb \
stm32mp157c-ed1-scmi.dtb \
stm32mp157c-ev1.dtb \
stm32mp157c-ev1-scmi.dtb \
stm32mp157c-odyssey.dtb
dtb-$(CONFIG_STM32MP25X) += \
stm32mp257f-ev1.dtb
dtb-$(CONFIG_SOC_K3_AM654) += \
k3-am654-r5-base-board.dtb
k3-am654-base-board.dtb \
k3-am654-r5-base-board.dtb \
k3-am654-icssg2.dtbo
dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-r5-common-proc-board.dtb \
k3-j7200-r5-common-proc-board.dtb \
k3-j721e-r5-sk.dtb \
k3-j721e-beagleboneai64.dtb \
k3-j721e-r5-beagleboneai64.dtb
dtb-$(CONFIG_SOC_K3_J7200) += k3-j7200-r5-common-proc-board.dtb
dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-r5-base-board.dtb\
k3-j721s2-r5-common-proc-board.dtb
dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-sk.dtb \
k3-j784s4-r5-evm.dtb
dtb-$(CONFIG_SOC_K3_J722S) += k3-j722s-r5-evm.dtb \
k3-am67a-r5-beagley-ai.dtb
dtb-$(CONFIG_SOC_K3_J722S) += k3-j722s-r5-evm.dtb
dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-r5-evm.dtb \
k3-am642-r5-sk.dtb \
@@ -1106,20 +1184,16 @@ dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-r5-sk.dtb \
k3-am625-verdin-r5.dtb \
k3-am625-r5-phycore-som-2gb.dtb
dtb-$(CONFIG_SOC_K3_AM62A7) += \
k3-am62a7-r5-sk.dtb \
k3-am62a7-r5-phycore-som-2gb.dtb
dtb-$(CONFIG_SOC_K3_AM62A7) += k3-am62a7-r5-sk.dtb
dtb-$(CONFIG_SOC_K3_AM62D2) += k3-am62d2-r5-evm.dtb
dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-r5-sk.dtb \
k3-am62p5-verdin-r5.dtb
dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-r5-sk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-rfb.dtb \
mt7623a-unielec-u7623-02-emmc.dtb \
mt7622-bananapi-bpi-r64.dtb \
mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \
mt7981-rfb.dtb \
mt7981-emmc-rfb.dtb \
mt7981-sd-rfb.dtb \
@@ -1209,8 +1283,6 @@ dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb
dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \
corstone1000-fvp.dtb
dtb-$(CONFIG_TARGET_COREPRIMEVELTE) += pxa1908-samsung-coreprimevelte.dtb
include $(srctree)/scripts/Makefile.dts
# Add any required device tree compiler flags here
arch/arm/dts/am335x-bonegreen-eco.dts
-53
View File
@@ -1,53 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2025 Bootlin
*/
/dts-v1/;
#include "am33xx.dtsi"
#include "am335x-bone-common.dtsi"
#include "am335x-bonegreen-common.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
model = "TI AM335x BeagleBone Green Eco";
compatible = "ti,am335x-bone-green-eco", "ti,am335x-bone-green",
"ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
cpus {
cpu@0 {
/delete-property/ cpu0-supply;
};
};
};
&usb0 {
interrupts-extended = <&intc 18>;
interrupt-names = "mc";
};
&cpsw_emac0 {
phy-mode = "rgmii-id";
phy-handle = <&dp83867_0>;
};
&davinci_mdio {
/delete-node/ ethernet-phy@0;
dp83867_0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-impedance;
ti,dp83867-rxctrl-strap-quirk;
};
};
&baseboard_eeprom {
/delete-property/ vcc-supply;
};
&i2c0 {
/delete-node/ tps@24;
};
arch/arm/dts/am335x-evm.dts
+4
View File
@@ -27,6 +27,10 @@
reg = <0x80000000 0x10000000>; /* 256 MB */
};
chosen {
stdout-path = &uart0;
};
vbat: fixedregulator0 {
compatible = "regulator-fixed";
regulator-name = "vbat";
arch/arm/dts/an7581-u-boot.dtsi
-108
View File
@@ -1,108 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
#include <dt-bindings/reset/airoha,en7581-reset.h>
/ {
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
atf-reserved-memory@80000000 {
no-map;
reg = <0x0 0x80000000 0x0 0x40000>;
};
};
clk25m: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "clkxtal";
};
vmmc_3v3: regulator-vmmc-3v3 {
compatible = "regulator-fixed";
regulator-name = "vmmc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
soc {
chip_scu: syscon@1fa20000 {
compatible = "airoha,en7581-chip-scu", "syscon";
reg = <0x0 0x1fa20000 0x0 0x388>;
};
eth: ethernet@1fb50000 {
compatible = "airoha,en7581-eth";
reg = <0 0x1fb50000 0 0x2600>,
<0 0x1fb54000 0 0x2000>,
<0 0x1fb56000 0 0x2000>;
reg-names = "fe", "qdma0", "qdma1";
resets = <&scuclk EN7581_FE_RST>,
<&scuclk EN7581_FE_PDMA_RST>,
<&scuclk EN7581_FE_QDMA_RST>,
<&scuclk EN7581_DUAL_HSI0_MAC_RST>,
<&scuclk EN7581_DUAL_HSI1_MAC_RST>,
<&scuclk EN7581_HSI_MAC_RST>,
<&scuclk EN7581_XFP_MAC_RST>;
reset-names = "fe", "pdma", "qdma",
"hsi0-mac", "hsi1-mac", "hsi-mac",
"xfp-mac";
};
switch: switch@1fb58000 {
compatible = "airoha,en7581-switch";
reg = <0 0x1fb58000 0 0x8000>;
};
snfi: spi@1fa10000 {
compatible = "airoha,en7581-snand";
reg = <0x0 0x1fa10000 0x0 0x140>,
<0x0 0x1fa11000 0x0 0x600>;
clocks = <&scuclk EN7523_CLK_SPI>;
clock-names = "spi";
#address-cells = <1>;
#size-cells = <0>;
spi_nand: nand@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <50000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <2>;
};
};
mmc0: mmc@1fa0e000 {
compatible = "mediatek,mt7622-mmc";
reg = <0x0 0x1fa0e000 0x0 0x1000>,
<0x0 0x1fa0c000 0x0 0x60>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scuclk EN7581_CLK_EMMC>, <&clk25m>;
clock-names = "source", "hclk";
bus-width = <4>;
max-frequency = <52000000>;
vmmc-supply = <&vmmc_3v3>;
disable-wp;
cap-mmc-highspeed;
non-removable;
assigned-clocks = <&scuclk EN7581_CLK_EMMC>;
assigned-clock-rates = <200000000>;
};
};
};
&scuclk {
compatible = "airoha,en7581-scu", "syscon";
};
&uart1 {
bootph-all;
};
arch/arm/dts/apq8016-sbc-u-boot.dtsi
+10 -1
View File
@@ -6,6 +6,15 @@
/ {
/* When running as a first-stage bootloader this isn't filled in automatically */
memory@80000000 {
reg = <0 0x80000000 0 0x40000000>;
reg = <0 0x80000000 0 0x3da00000>;
};
};
/*
* When running as a first-stage bootloader, we need to re-configure the UART pins
* because SBL de-initialises them. Indicate that the UART pins should be configured
* during all boot stages.
*/
&blsp_uart2_default {
bootph-all;
};
arch/arm/dts/apq8016-schneider-hmibsc.dts
+1 -1
View File
@@ -463,7 +463,7 @@
drive-strength = <16>;
};
&blsp_uart1_console_default {
&blsp_uart1_default {
bootph-all;
};
arch/arm/dts/ast2600-sbp1.dts
-5908
View File
File diff suppressed because it is too large Load Diff
arch/arm/dts/ast2600.dtsi
+1 -1
View File
@@ -794,7 +794,7 @@
uart11: serial@1e790500 {
compatible = "ns16550a";
reg = <0x1e790500 0x20>;
reg = <0x1e790400 0x20>;
reg-shift = <2>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scu ASPEED_CLK_GATE_UART11CLK>;
arch/arm/dts/at91-sam9x60_curiosity-u-boot.dtsi
-4
View File
@@ -95,7 +95,3 @@
&slow_xtal {
bootph-all;
};
&watchdog {
timeout-sec = <16>;
};
arch/arm/dts/at91-sam9x60_curiosity.dts
-79
View File
@@ -82,11 +82,6 @@
};
};
&dbgu {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
};
&ebi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
@@ -176,20 +171,10 @@
&macb0 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_rmii>;
status = "okay";
};
&pinctrl {
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins =
<AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
ebi {
pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
atmel,pins =
@@ -232,22 +217,6 @@
};
};
macb0 {
pinctrl_macb0_rmii: macb0_rmii-0 {
atmel,pins =
<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
};
};
nand {
pinctrl_nand_oe_we: nand-oe-we-0 {
atmel,pins =
@@ -271,36 +240,6 @@
<AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
sdhci0 {
pinctrl_sdhci0: sdhci0 {
atmel,pins =
<AT91_PIOA 17 AT91_PERIPH_A
(AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA17 CK periph A with pullup */
AT91_PIOA 16 AT91_PERIPH_A
(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA16 CMD periph A with pullup */
AT91_PIOA 15 AT91_PERIPH_A
(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA15 DAT0 periph A */
AT91_PIOA 18 AT91_PERIPH_A
(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA18 DAT1 periph A with pullup */
AT91_PIOA 19 AT91_PERIPH_A
(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA) /* PA19 DAT2 periph A with pullup */
AT91_PIOA 20 AT91_PERIPH_A
(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>; /* PA20 DAT3 periph A with pullup */
};
};
sdhci1 {
pinctrl_sdhci1: sdhci1 {
atmel,pins =
<AT91_PIOA 13 AT91_PERIPH_B (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA13 CK periph B */
AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA12 CMD periph B with pullup */
AT91_PIOA 11 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA11 DAT0 periph B with pullup */
AT91_PIOA 2 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA2 DAT1 periph B with pullup */
AT91_PIOA 3 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA3 DAT2 periph B with pullup */
AT91_PIOA 4 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA4 DAT3 periph B with pullup */
};
};
usb1 {
pinctrl_usb_default: usb_default {
atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
@@ -309,20 +248,6 @@
};
};
&sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci0>;
};
&sdhci1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci1>;
};
&usb0 {
status = "okay";
};
&usb1 {
num-ports = <3>;
atmel,vbus-gpio = <0
@@ -336,7 +261,3 @@
&usb2 {
status = "okay";
};
&watchdog {
status = "okay";
};
arch/arm/dts/at91-sam9x75_curiosity-u-boot.dtsi
-95
View File
@@ -1,95 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* at91-sam9x75_curiosity-u-boot.dtsi - Device Tree file for SAM9X75
* CURIOSITY board.
*
* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
*
* Author: Manikandan Muralidharan <manikandan.m@microchip.com>
*/
/ {
cpus {
cpu@0 {
clocks = <&pmc PMC_TYPE_CORE 25>, <&pmc PMC_TYPE_CORE 17>, <&main_xtal>;
clock-names = "cpu", "master", "xtal";
};
};
clocks {
slow_rc_osc: slow_rc_osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <18500>;
};
};
ahb {
bootph-all;
apb {
bootph-all;
pinctrl {
bootph-all;
};
};
};
chosen {
bootph-all;
};
};
&clk32k {
bootph-all;
clocks = <&slow_rc_osc>, <&slow_xtal>;
};
&dbgu {
bootph-all;
};
&gmac {
compatible = "microchip,sam9x7-gem", "cdns,sama7g5-gem";
};
&main_xtal {
bootph-all;
};
&pinctrl_dbgu_default {
bootph-all;
};
&pinctrl_sdmmc0_default {
bootph-all;
};
&pioA {
bootph-all;
};
&pioB {
bootph-all;
};
&pit64b0 {
bootph-all;
};
&pmc {
bootph-all;
};
&sdmmc0 {
bootph-all;
};
&slow_xtal {
bootph-all;
};
&slow_rc_osc {
bootph-all;
};
arch/arm/dts/at91-sama7d65_curiosity-u-boot.dtsi
-80
View File
@@ -1,80 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* at91-sama7d65_curiosity-u-boot.dtsi - Device Tree Include file for
* SAMA7D65 CURIOSITY.
*
* Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries
*
* Author: Ryan Wanner <ryan.wanner@microchip.com>
*/
/{
aliases {
serial0 = &uart6;
};
chosen {
bootph-all;
};
clocks {
slow_rc_osc: slow_rc_osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
};
};
cpus {
cpu@0 {
clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_CORE 26>, <&main_xtal>;
clock-names = "cpu", "master", "xtal";
};
};
soc {
bootph-all;
};
};
&clk32k {
clocks = <&slow_rc_osc>, <&slow_xtal>;
};
&main_xtal {
bootph-all;
};
&pioa {
bootph-all;
};
&pinctrl_uart6_default {
bootph-all;
};
&pit64b0 {
bootph-all;
};
&pmc {
bootph-all;
};
&sdmmc1 {
assigned-clock-parents = <&pmc PMC_TYPE_CORE 27>; /* MCK1 div */
microchip,sdcal-inverted;
no-1-8-v;
};
&slow_rc_osc {
bootph-all;
};
&slow_xtal {
bootph-all;
};
&uart6 {
bootph-all;
};
arch/arm/dts/at91sam9260.dtsi
+40 -36
View File
@@ -401,11 +401,51 @@
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
pioA: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
bootph-all;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
bootph-all;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
bootph-all;
};
pinctrl: pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff400 0xfffff400 0x600>;
reg = <0xfffff400 0x200 /* pioA */
0xfffff600 0x200 /* pioB */
0xfffff800 0x200 /* pioC */
>;
atmel,mux-mask = <
/* A B */
@@ -727,42 +767,6 @@
atmel,pins = <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
pioA: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
bootph-all;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
bootph-all;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
bootph-all;
};
};
dbgu: serial@fffff200 {
arch/arm/dts/at91sam9261.dtsi
+40 -37
View File
@@ -286,12 +286,51 @@
status = "disabled";
};
pioA: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
bootph-all;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
bootph-all;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
bootph-all;
};
pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff400 0xfffff400 0x600>;
reg = <0xfffff400 0x200 /* pioA */
0xfffff600 0x200 /* pioB */
0xfffff800 0x200 /* pioC */
>;
atmel,mux-mask =
/* A B */
<0xffffffff 0xfffffff7>, /* pioA */
@@ -534,42 +573,6 @@
<AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
pioA: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
bootph-all;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
bootph-all;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
bootph-all;
};
};
pmc: pmc@fffffc00 {
arch/arm/dts/at91sam9263.dtsi
+62 -55
View File
@@ -404,6 +404,12 @@
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff200 0xfffff200 0xa00>;
reg = <0xfffff200 0x200
0xfffff400 0x200
0xfffff600 0x200
0xfffff800 0x200
0xfffffa00 0x200
>;
atmel,mux-mask = <
/* A B */
@@ -713,65 +719,66 @@
};
};
pioA: gpio@fffff200 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff200 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
bootph-all;
};
};
pioB: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
bootph-all;
};
pioA: gpio@fffff200 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff200 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
bootph-all;
};
pioC: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCDE_clk>;
bootph-all;
};
pioB: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
bootph-all;
};
pioD: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCDE_clk>;
bootph-all;
};
pioC: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCDE_clk>;
bootph-all;
};
pioE: gpio@fffffa00 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCDE_clk>;
bootph-all;
};
pioD: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCDE_clk>;
bootph-all;
};
pioE: gpio@fffffa00 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCDE_clk>;
bootph-all;
};
dbgu: serial@ffffee00 {
arch/arm/dts/at91sam9g45.dtsi
+56 -50
View File
@@ -435,6 +435,12 @@
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff200 0xfffff200 0xa00>;
reg = <0xfffff200 0x200
0xfffff400 0x200
0xfffff600 0x200
0xfffff800 0x200
0xfffffa00 0x200
>;
bootph-all;
atmel,mux-mask = <
@@ -848,61 +854,61 @@
AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
};
};
};
pioA: gpio@fffff200 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff200 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
};
pioA: gpio@fffff200 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff200 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
};
pioB: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
};
pioB: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
};
pioC: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
};
pioC: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
};
pioD: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioDE_clk>;
};
pioD: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioDE_clk>;
};
pioE: gpio@fffffa00 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioDE_clk>;
};
pioE: gpio@fffffa00 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioDE_clk>;
};
dbgu: serial@ffffee00 {
arch/arm/dts/at91sam9n12.dtsi
+49 -44
View File
@@ -492,6 +492,11 @@
#size-cells = <1>;
compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff400 0xfffff400 0x800>;
reg = <0xfffff400 0x200
0xfffff600 0x200
0xfffff800 0x200
0xfffffa00 0x200
>;
atmel,mux-mask = <
/* A B C */
@@ -790,54 +795,54 @@
atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
};
};
};
pioA: gpio@fffff400 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioAB_clk>;
bootph-all;
};
pioA: gpio@fffff400 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioAB_clk>;
bootph-all;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioAB_clk>;
bootph-all;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioAB_clk>;
bootph-all;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCD_clk>;
bootph-all;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCD_clk>;
bootph-all;
};
pioD: gpio@fffffa00 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCD_clk>;
bootph-all;
};
pioD: gpio@fffffa00 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCD_clk>;
bootph-all;
};
dbgu: serial@fffff200 {
arch/arm/dts/at91sam9rl.dtsi
+49 -44
View File
@@ -386,6 +386,11 @@
#size-cells = <1>;
compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff400 0xfffff400 0x800>;
reg = <0xfffff400 0x200
0xfffff600 0x200
0xfffff800 0x200
0xfffffa00 0x200
>;
atmel,mux-mask =
/* A B */
@@ -763,54 +768,54 @@
<AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
};
pioA: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
bootph-all;
};
pioA: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioA_clk>;
bootph-all;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
bootph-all;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioB_clk>;
bootph-all;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
bootph-all;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioC_clk>;
bootph-all;
};
pioD: gpio@fffffa00 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioD_clk>;
bootph-all;
};
pioD: gpio@fffffa00 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioD_clk>;
bootph-all;
};
pmc: pmc@fffffc00 {
arch/arm/dts/at91sam9x5.dtsi
+48 -42
View File
@@ -461,8 +461,14 @@
#size-cells = <1>;
compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
ranges = <0xfffff400 0xfffff400 0x800>;
reg = <0xfffff400 0x200 /* pioA */
0xfffff600 0x200 /* pioB */
0xfffff800 0x200 /* pioC */
0xfffffa00 0x200 /* pioD */
>;
bootph-all;
/* shared pinctrl settings */
dbgu {
bootph-all;
@@ -825,52 +831,52 @@
atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
};
};
};
pioA: gpio@fffff400 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioAB_clk>;
};
pioA: gpio@fffff400 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioAB_clk>;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
#gpio-lines = <19>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioAB_clk>;
};
pioB: gpio@fffff600 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff600 0x200>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
#gpio-lines = <19>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioAB_clk>;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCD_clk>;
};
pioC: gpio@fffff800 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffff800 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCD_clk>;
};
pioD: gpio@fffffa00 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
#gpio-lines = <22>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCD_clk>;
};
pioD: gpio@fffffa00 {
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
reg = <0xfffffa00 0x200>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
#gpio-cells = <2>;
gpio-controller;
#gpio-lines = <22>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&pioCD_clk>;
};
ssc0: ssc@f0010000 {
arch/arm/dts/bcm4908.dtsi
+127
View File
@@ -0,0 +1,127 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/dts-v1/;
/ {
compatible = "brcm,bcm4908", "brcm,bcmbca";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "brcm,brahma-b53";
reg = <0x0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0xfff8>;
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "brcm,brahma-b53";
reg = <0x1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0xfff8>;
next-level-cache = <&l2>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "brcm,brahma-b53";
reg = <0x2>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0xfff8>;
next-level-cache = <&l2>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "brcm,brahma-b53";
reg = <0x3>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0xfff8>;
next-level-cache = <&l2>;
};
l2: l2-cache0 {
compatible = "cache";
};
};
axi@81000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0x81000000 0x4000>;
gic: interrupt-controller@1000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x1000 0x1000>,
<0x2000 0x2000>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
clocks {
periph_clk: periph_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "periph";
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00 0x00 0xff800000 0x3000>;
uart0: serial@640 {
compatible = "brcm,bcm6345-uart";
reg = <0x640 0x18>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&periph_clk>;
clock-names = "refclk";
status = "disabled";
};
};
};
arch/arm/dts/bcm63138.dtsi
+149
View File
@@ -0,0 +1,149 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Broadcom BCM63138 DSL SoCs Device Tree
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "brcm,bcm63138", "brcm,bcmbca";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0>;
enable-method = "brcm,bcm63138";
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <1>;
enable-method = "brcm,bcm63138";
};
};
clocks {
/* UBUS peripheral clock */
periph_clk: periph_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
clock-output-names = "periph";
};
/* peripheral clock for system timer */
axi_clk: axi_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&armpll>;
clock-div = <2>;
clock-mult = <1>;
};
/* APB bus clock */
apb_clk: apb_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&armpll>;
clock-div = <4>;
clock-mult = <1>;
};
};
/* ARM bus */
axi@80000000 {
compatible = "simple-bus";
ranges = <0 0x80000000 0x784000>;
#address-cells = <1>;
#size-cells = <1>;
L2: cache-controller@1d000 {
compatible = "arm,pl310-cache";
reg = <0x1d000 0x1000>;
cache-unified;
cache-level = <2>;
cache-size = <524288>;
cache-sets = <1024>;
cache-line-size = <32>;
interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
scu: scu@1e000 {
compatible = "arm,cortex-a9-scu";
reg = <0x1e000 0x100>;
};
gic: interrupt-controller@1f000 {
compatible = "arm,cortex-a9-gic";
reg = <0x1f000 0x1000
0x1e100 0x100>;
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
};
global_timer: timer@1e200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x1e200 0x20>;
interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
clocks = <&axi_clk>;
};
local_timer: local-timer@1e600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x1e600 0x20>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_EDGE_RISING)>;
clocks = <&axi_clk>;
};
twd_watchdog: watchdog@1e620 {
compatible = "arm,cortex-a9-twd-wdt";
reg = <0x1e620 0x20>;
interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
};
armpll: armpll@20000 {
#clock-cells = <0>;
compatible = "brcm,bcm63138-armpll";
clocks = <&periph_clk>;
reg = <0x20000 0xf00>;
};
};
/* Legacy UBUS base */
bus@fffe8000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xfffe8000 0x8000>;
timer0: timer@80 {
compatible = "brcm,bcmbca-periph-timer";
reg = <0x80 0x28>;
clocks = <&periph_clk>;
};
uart0: serial@600 {
compatible = "brcm,bcm6345-uart";
reg = <0x600 0x20>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&periph_clk>;
clock-names = "refclk";
status = "disabled";
};
};
};
arch/arm/dts/bcm63148.dtsi
+103
View File
@@ -0,0 +1,103 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "brcm,bcm63148", "brcm,bcmbca";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
B15_0: cpu@0 {
device_type = "cpu";
compatible = "brcm,brahma-b15";
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
B15_1: cpu@1 {
device_type = "cpu";
compatible = "brcm,brahma-b15";
reg = <0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
};
L2_0: l2-cache0 {
compatible = "cache";
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu: pmu {
compatible = "arm,cortex-a15-pmu";
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&B15_0>, <&B15_1>;
};
clocks: clocks {
periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
axi@80030000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x80030000 0x8000>;
gic: interrupt-controller@1000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x1000 0x1000>,
<0x2000 0x2000>,
<0x4000 0x2000>,
<0x6000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
};
};
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xfffe8000 0x8000>;
uart0: serial@600 {
compatible = "brcm,bcm6345-uart";
reg = <0x600 0x20>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&periph_clk>;
clock-names = "refclk";
status = "disabled";
};
};
};
arch/arm/dts/bcm94908.dts
+30
View File
@@ -0,0 +1,30 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm4908.dtsi"
/ {
model = "Broadcom BCM94908 Reference Board";
compatible = "brcm,bcm94908", "brcm,bcm4908", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};
arch/arm/dts/bcm963138.dts
+30
View File
@@ -0,0 +1,30 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm63138.dtsi"
/ {
model = "Broadcom BCM963138 Reference Board";
compatible = "brcm,bcm963138", "brcm,bcm63138", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};
arch/arm/dts/bcm963148.dts
+30
View File
@@ -0,0 +1,30 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 Broadcom Ltd.
*/
/dts-v1/;
#include "bcm63148.dtsi"
/ {
model = "Broadcom BCM963148 Reference Board";
compatible = "brcm,bcm963148", "brcm,bcm63148", "brcm,bcmbca";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x08000000>;
};
};
&uart0 {
status = "okay";
};
arch/arm/dts/bcm96753ref.dts
+11 -7
View File
@@ -64,15 +64,19 @@
status = "okay";
};
&nand_controller {
brcm,wp-not-connected;
&nand {
status = "okay";
};
write-protect = <0>;
#address-cells = <1>;
#size-cells = <0>;
&nandcs {
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
brcm,nand-oob-sector-size = <16>;
nandcs@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
brcm,nand-oob-sector-size = <16>;
};
};
&leds {
arch/arm/dts/bcm968360bg.dts
+11 -7
View File
@@ -62,15 +62,19 @@
status = "okay";
};
&nand_controller {
brcm,wp-not-connected;
&nand {
status = "okay";
};
write-protect = <0>;
#address-cells = <1>;
#size-cells = <0>;
&nandcs {
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
brcm,nand-oob-sector-size = <16>;
nandcs@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
brcm,nand-oob-sector-size = <16>;
};
};
&leds {
arch/arm/dts/bcm968580xref.dts
+11 -7
View File
@@ -62,15 +62,19 @@
status = "okay";
};
&nand_controller {
brcm,wp-not-connected;
&nand {
status = "okay";
};
write-protect = <0>;
#address-cells = <1>;
#size-cells = <0>;
&nandcs {
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
brcm,nand-oob-sector-size = <16>;
nandcs@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
brcm,nand-oob-sector-size = <16>;
};
};
&leds {
arch/arm/dts/en7523-evb-u-boot.dtsi
-11
View File
@@ -1,11 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/ {
/* When running as a first-stage bootloader this isn't filled in automatically */
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
};
#include "en7523-u-boot.dtsi"
arch/arm/dts/en7523-u-boot.dtsi
-70
View File
@@ -1,70 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
#include <dt-bindings/reset/airoha,en7523-reset.h>
/ {
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
atf-reserved-memory@80000000 {
no-map;
reg = <0x80000000 0x40000>;
};
};
scu: system-controller@1fa20000 {
compatible = "airoha,en7523-scu";
reg = <0x1fa20000 0x400>,
<0x1fb00000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
eth: ethernet@1fb50000 {
compatible = "airoha,en7523-eth";
reg = <0x1fb50000 0x2600>,
<0x1fb54000 0x2000>,
<0x1fb56000 0x2000>;
reg-names = "fe", "qdma0", "qdma1";
resets = <&scu EN7523_FE_RST>,
<&scu EN7523_FE_PDMA_RST>,
<&scu EN7523_FE_QDMA_RST>,
<&scu EN7523_DUAL_HSI0_MAC_RST>,
<&scu EN7523_DUAL_HSI1_MAC_RST>,
<&scu EN7523_HSI_MAC_RST>;
reset-names = "fe", "pdma", "qdma",
"hsi0-mac", "hsi1-mac", "hsi-mac";
};
switch: switch@1fb58000 {
compatible = "airoha,en7523-switch";
reg = <0x1fb58000 0x8000>;
};
snfi: spi@1fa10000 {
compatible = "airoha,en7523-snand", "airoha,en7581-snand";
reg = <0x1fa10000 0x140>,
<0x1fa11000 0x600>;
clocks = <&scu EN7523_CLK_SPI>;
clock-names = "spi";
#address-cells = <1>;
#size-cells = <0>;
spi_nand: nand@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <50000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <2>;
};
};
};
&uart1 {
bootph-all;
};

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