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SPECS: linux: Bump to 7.0.2 & refresh patchset & refresh config

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Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
This commit is contained in:
Han Gao
2026-04-28 02:50:29 +08:00
committed by Z572
parent f410941a42
commit b915012196
279 changed files with 10675 additions and 15272 deletions
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200
SPECS/linux/0001-UPSTREAM-PCI-MSI-Convert-the-boolean-no_64bit_msi-fl.patch
View File

@@ -1,200 +0,0 @@
From 040ee72cd826180c9f6eeb708aaa12f015762edc Mon Sep 17 00:00:00 2001
From: Vivian Wang <wangruikang@iscas.ac.cn>
Date: Thu, 29 Jan 2026 09:56:06 +0800
Subject: [PATCH 001/197] UPSTREAM: PCI/MSI: Convert the boolean no_64bit_msi
flag to a DMA address mask
Some PCI devices have PCI_MSI_FLAGS_64BIT in the MSI capability, but
implement less than 64 address bits. This breaks on platforms where such
a device is assigned an MSI address higher than what's supported.
Currently, no_64bit_msi bit is set for these devices, meaning that only
32-bit MSI addresses are allowed for them. However, on some platforms the
MSI doorbell address is above the 32-bit limit but within the addressable
range of the device.
As a first step to enable MSI on those combinations of devices and
platforms, convert the boolean no_64bit_msi flag to a DMA mask and fixup
the affected usage sites:
- no_64bit_msi = 1 -> msi_addr_mask = DMA_BIT_MASK(32)
- no_64bit_msi = 0 -> msi_addr_mask = DMA_BIT_MASK(64)
- if (no_64bit_msi) -> if (msi_addr_mask < DMA_BIT_MASK(64))
Since no values other than DMA_BIT_MASK(32) and DMA_BIT_MASK(64) are used,
this is functionally equivalent.
This prepares for changing the binary decision between 32 and 64 bit to a
DMA mask based decision which allows to support systems which have a DMA
address space less than 64bit but a MSI doorbell address above the 32-bit
limit.
[ tglx: Massaged changelog ]
Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Reviewed-by: Brett Creeley <brett.creeley@amd.com> # ionic
Reviewed-by: Thomas Gleixner <tglx@kernel.org>
Acked-by: Takashi Iwai <tiwai@suse.de> # sound
Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-1-70da998f2750@iscas.ac.cn
(cherry picked from commit 386ced19e9a348e8131d20f009e692fa8fcc4568)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/powerpc/platforms/powernv/pci-ioda.c | 2 +-
arch/powerpc/platforms/pseries/msi.c | 4 ++--
drivers/gpu/drm/radeon/radeon_irq_kms.c | 2 +-
drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c | 2 +-
drivers/pci/msi/msi.c | 2 +-
drivers/pci/msi/pcidev_msi.c | 2 +-
drivers/pci/probe.c | 7 +++++++
include/linux/pci.h | 8 +++++++-
sound/hda/controllers/intel.c | 2 +-
9 files changed, 22 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index b0c1d9d16fb5..1c78fdfb7b03 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -1666,7 +1666,7 @@ static int __pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
return -ENXIO;
/* Force 32-bit MSI on some broken devices */
- if (dev->no_64bit_msi)
+ if (dev->msi_addr_mask < DMA_BIT_MASK(64))
is_64 = 0;
/* Assign XIVE to PE */
diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/pseries/msi.c
index 56f17296545a..67bc001688c6 100644
--- a/arch/powerpc/platforms/pseries/msi.c
+++ b/arch/powerpc/platforms/pseries/msi.c
@@ -388,7 +388,7 @@ static int rtas_prepare_msi_irqs(struct pci_dev *pdev, int nvec_in, int type,
*/
again:
if (type == PCI_CAP_ID_MSI) {
- if (pdev->no_64bit_msi) {
+ if (pdev->msi_addr_mask < DMA_BIT_MASK(64)) {
rc = rtas_change_msi(pdn, RTAS_CHANGE_32MSI_FN, nvec);
if (rc < 0) {
/*
@@ -414,7 +414,7 @@ static int rtas_prepare_msi_irqs(struct pci_dev *pdev, int nvec_in, int type,
if (use_32bit_msi_hack && rc > 0)
rtas_hack_32bit_msi_gen2(pdev);
} else {
- if (pdev->no_64bit_msi)
+ if (pdev->msi_addr_mask < DMA_BIT_MASK(64))
rc = rtas_change_msi(pdn, RTAS_CHANGE_32MSIX_FN, nvec);
else
rc = rtas_change_msi(pdn, RTAS_CHANGE_MSIX_FN, nvec);
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index 9961251b44ba..d550554a6f3f 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -252,7 +252,7 @@ static bool radeon_msi_ok(struct radeon_device *rdev)
*/
if (rdev->family < CHIP_BONAIRE) {
dev_info(rdev->dev, "radeon: MSI limited to 32-bit\n");
- rdev->pdev->no_64bit_msi = 1;
+ rdev->pdev->msi_addr_mask = DMA_BIT_MASK(32);
}
/* force MSI on */
diff --git a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
index 70d86c5f52fb..0671deae9a28 100644
--- a/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
+++ b/drivers/net/ethernet/pensando/ionic/ionic_bus_pci.c
@@ -331,7 +331,7 @@ static int ionic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
#ifdef CONFIG_PPC64
/* Ensure MSI/MSI-X interrupts lie within addressable physical memory */
- pdev->no_64bit_msi = 1;
+ pdev->msi_addr_mask = DMA_BIT_MASK(32);
#endif
err = ionic_setup_one(ionic);
diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c
index e010ecd9f90d..fb9a42bec62e 100644
--- a/drivers/pci/msi/msi.c
+++ b/drivers/pci/msi/msi.c
@@ -322,7 +322,7 @@ static int msi_verify_entries(struct pci_dev *dev)
{
struct msi_desc *entry;
- if (!dev->no_64bit_msi)
+ if (dev->msi_addr_mask == DMA_BIT_MASK(64))
return 0;
msi_for_each_desc(entry, &dev->dev, MSI_DESC_ALL) {
diff --git a/drivers/pci/msi/pcidev_msi.c b/drivers/pci/msi/pcidev_msi.c
index 5520aff53b56..0b0346813092 100644
--- a/drivers/pci/msi/pcidev_msi.c
+++ b/drivers/pci/msi/pcidev_msi.c
@@ -24,7 +24,7 @@ void pci_msi_init(struct pci_dev *dev)
}
if (!(ctrl & PCI_MSI_FLAGS_64BIT))
- dev->no_64bit_msi = 1;
+ dev->msi_addr_mask = DMA_BIT_MASK(32);
}
void pci_msix_init(struct pci_dev *dev)
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index cd1cd044aaf9..08f7dcbc92a4 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -2045,6 +2045,13 @@ int pci_setup_device(struct pci_dev *dev)
*/
dev->dma_mask = 0xffffffff;
+ /*
+ * Assume 64-bit addresses for MSI initially. Will be changed to 32-bit
+ * if MSI (rather than MSI-X) capability does not have
+ * PCI_MSI_FLAGS_64BIT. Can also be overridden by driver.
+ */
+ dev->msi_addr_mask = DMA_BIT_MASK(64);
+
dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
dev->bus->number, PCI_SLOT(dev->devfn),
PCI_FUNC(dev->devfn));
diff --git a/include/linux/pci.h b/include/linux/pci.h
index e958ff744335..973dfba3e91b 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -377,6 +377,13 @@ struct pci_dev {
0xffffffff. You only need to change
this if your device has broken DMA
or supports 64-bit transfers. */
+ u64 msi_addr_mask; /* Mask of the bits of bus address for
+ MSI that this device implements.
+ Normally set based on device
+ capabilities. You only need to
+ change this if your device claims
+ to support 64-bit MSI but implements
+ fewer than 64 address bits. */
struct device_dma_parameters dma_parms;
@@ -442,7 +449,6 @@ struct pci_dev {
unsigned int is_busmaster:1; /* Is busmaster */
unsigned int no_msi:1; /* May not use MSI */
- unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
unsigned int block_cfg_access:1; /* Config space access blocked */
unsigned int broken_parity_status:1; /* Generates false positive parity */
unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
diff --git a/sound/hda/controllers/intel.c b/sound/hda/controllers/intel.c
index f8919cb521a1..9aea3fbc22cf 100644
--- a/sound/hda/controllers/intel.c
+++ b/sound/hda/controllers/intel.c
@@ -1907,7 +1907,7 @@ static int azx_first_init(struct azx *chip)
if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) {
dev_dbg(card->dev, "Disabling 64bit MSI\n");
- pci->no_64bit_msi = true;
+ pci->msi_addr_mask = DMA_BIT_MASK(32);
}
pci_set_master(pci);
--
2.53.0

16
SPECS/linux/0097-FROMLIST-rust-clk-implement-Send-and-Sync.patch → SPECS/linux/0001-UPSTREAM-rust-clk-implement-Send-and-Sync.patch
View File

@@ -1,7 +1,7 @@
From 4d13fef536d136b83f38909cd20438d88e8cd1a0 Mon Sep 17 00:00:00 2001
From e51848c57d5d984d8dfa0f02a48361dcd92d097c Mon Sep 17 00:00:00 2001
From: Alice Ryhl <aliceryhl@google.com>
Date: Thu, 18 Dec 2025 13:27:40 +0000
Subject: [PATCH 097/197] FROMLIST: rust: clk: implement Send and Sync
Date: Mon, 23 Feb 2026 10:08:25 +0000
Subject: [PATCH 001/189] UPSTREAM: rust: clk: implement Send and Sync
These traits are required for drivers to embed the Clk type in their own
data structures because driver data structures are usually required to
@@ -12,18 +12,22 @@ Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Reviewed-by: Danilo Krummrich <dakr@kernel.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Boqun Feng <boqun.feng@gmail.com>
Reviewed-by: Gary Guo <gary@garyguo.net>
Signed-off-by: Alice Ryhl <aliceryhl@google.com>
Link: https://lore.kernel.org/r/20251218-clk-send-sync-v3-1-e48b2e2f1eac@google.com
Acked-by: Brian Masney <bmasney@redhat.com> # Active contributor to clk
Link: https://patch.msgid.link/20260223-clk-send-sync-v5-1-181bf2f35652@google.com
Signed-off-by: Miguel Ojeda <ojeda@kernel.org>
(cherry picked from commit 0c0695a9d8c97f63d71dc890faa6999eef728f57)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
rust/kernel/clk.rs | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/rust/kernel/clk.rs b/rust/kernel/clk.rs
index c1cfaeaa36a2..d192fbd97861 100644
index 4059aff34d09..7abbd0767d8c 100644
--- a/rust/kernel/clk.rs
+++ b/rust/kernel/clk.rs
@@ -129,6 +129,13 @@ mod common_clk {
@@ -128,6 +128,13 @@ mod common_clk {
#[repr(transparent)]
pub struct Clk(*mut bindings::clk);

52
SPECS/linux/0002-UPSTREAM-PCI-MSI-Check-the-device-specific-address-m.patch
View File

@@ -1,52 +0,0 @@
From 01b75e553f66626f3d18ae77223de6edfcbd4c23 Mon Sep 17 00:00:00 2001
From: Vivian Wang <wangruikang@iscas.ac.cn>
Date: Thu, 29 Jan 2026 09:56:07 +0800
Subject: [PATCH 002/197] UPSTREAM: PCI/MSI: Check the device specific address
mask in msi_verify_entries()
Instead of a 32-bit/64-bit dichotomy, check the MSI address against
the device specific address mask.
This allows platforms with an MSI doorbell address above the 32-bit limit
to work with devices without full 64-bit MSI address support, as long as
the doorbell is within the addressable range of the device.
[ tglx: Massaged changelog ]
Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Reviewed-by: Thomas Gleixner <tglx@kernel.org>
Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-2-70da998f2750@iscas.ac.cn
(cherry picked from commit 52f0d862f595a2fa18ef44532619a080c24fe4cb)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/pci/msi/msi.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c
index fb9a42bec62e..e2412175d7af 100644
--- a/drivers/pci/msi/msi.c
+++ b/drivers/pci/msi/msi.c
@@ -321,14 +321,16 @@ static int msi_setup_msi_desc(struct pci_dev *dev, int nvec,
static int msi_verify_entries(struct pci_dev *dev)
{
struct msi_desc *entry;
+ u64 address;
if (dev->msi_addr_mask == DMA_BIT_MASK(64))
return 0;
msi_for_each_desc(entry, &dev->dev, MSI_DESC_ALL) {
- if (entry->msg.address_hi) {
- pci_err(dev, "arch assigned 64-bit MSI address %#x%08x but device only supports 32 bits\n",
- entry->msg.address_hi, entry->msg.address_lo);
+ address = (u64)entry->msg.address_hi << 32 | entry->msg.address_lo;
+ if (address & ~dev->msi_addr_mask) {
+ pci_err(dev, "arch assigned 64-bit MSI address %#llx above device MSI address mask %#llx\n",
+ address, dev->msi_addr_mask);
break;
}
}
--
2.53.0

15
SPECS/linux/0098-FROMLIST-tyr-remove-impl-Send-Sync-for-TyrData.patch → SPECS/linux/0002-UPSTREAM-tyr-remove-impl-Send-Sync-for-TyrData.patch
View File

@@ -1,7 +1,7 @@
From f563d70b72a697e9f90596f6a136143d27e26f70 Mon Sep 17 00:00:00 2001
From 7ac524579b5834b815d7f19744753d5578577c90 Mon Sep 17 00:00:00 2001
From: Alice Ryhl <aliceryhl@google.com>
Date: Thu, 18 Dec 2025 13:27:41 +0000
Subject: [PATCH 098/197] FROMLIST: tyr: remove impl Send/Sync for TyrData
Date: Mon, 23 Feb 2026 10:08:26 +0000
Subject: [PATCH 002/189] UPSTREAM: tyr: remove impl Send/Sync for TyrData
Now that clk implements Send and Sync, we no longer need to manually
implement these traits for TyrData. Thus remove the implementations.
@@ -12,16 +12,19 @@ and Sync for Regulator<T>"), which is already in mainline.
Reviewed-by: Danilo Krummrich <dakr@kernel.org>
Reviewed-by: Boqun Feng <boqun.feng@gmail.com>
Signed-off-by: Alice Ryhl <aliceryhl@google.com>
Reviewed-by: Gary Guo <gary@garyguo.net>
Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Link: https://lore.kernel.org/r/20251218-clk-send-sync-v3-2-e48b2e2f1eac@google.com
Signed-off-by: Alice Ryhl <aliceryhl@google.com>
Link: https://patch.msgid.link/20260223-clk-send-sync-v5-2-181bf2f35652@google.com
Signed-off-by: Miguel Ojeda <ojeda@kernel.org>
(cherry picked from commit ef90b103e8f767ffc31b1ddfef012358ea873d85)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/gpu/drm/tyr/driver.rs | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/tyr/driver.rs b/drivers/gpu/drm/tyr/driver.rs
index 3047fd12fd84..a104a70cf135 100644
index beeffe36b6cb..e833e9f537b0 100644
--- a/drivers/gpu/drm/tyr/driver.rs
+++ b/drivers/gpu/drm/tyr/driver.rs
@@ -53,18 +53,6 @@ pub(crate) struct TyrData {

74
SPECS/linux/0003-UPSTREAM-drm-radeon-Make-MSI-address-limit-based-on-.patch
View File

@@ -1,74 +0,0 @@
From e90bb29afee2953c2941e3e3a0337f4a1e5b5416 Mon Sep 17 00:00:00 2001
From: Vivian Wang <wangruikang@iscas.ac.cn>
Date: Thu, 29 Jan 2026 09:56:08 +0800
Subject: [PATCH 003/197] UPSTREAM: drm/radeon: Make MSI address limit based on
the device DMA limit
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The radeon driver restricts the MSI message address for devices older than
the BONAIR generation to 32-bit MSI addresses due to the former
restrictions of the PCI/MSI code which only allowed either 32-bit or full
64-bit address range.
This does not work on platforms which have a MSI doorbell address above the
32-bit boundary but do not support the full 64 bit address range.
The PCI/MSI core converted this binary decision to a DMA_BIT_MASK() based
decision, which allows to describe the device limitations precisely.
Convert the driver to provide the exact DMA address limitations to the
PCI/MSI core. That allows devices which do not support the full 64-bit
address space to work on platforms which have a MSI doorbell address above
the 32-bit limit as long as it is within the hardware's addressable range.
[ tglx: Massage changelog ]
Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Reviewed-by: Christian König <christian.koenig@amd.com>
Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-3-70da998f2750@iscas.ac.cn
(cherry picked from commit 617562bbe12df796fc21df5fbf262eadf083a90f)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/gpu/drm/radeon/radeon_device.c | 1 +
drivers/gpu/drm/radeon/radeon_irq_kms.c | 10 ----------
2 files changed, 1 insertion(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 60afaa8e56b4..5faae0361361 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1374,6 +1374,7 @@ int radeon_device_init(struct radeon_device *rdev,
pr_warn("radeon: No suitable DMA available\n");
return r;
}
+ rdev->pdev->msi_addr_mask = DMA_BIT_MASK(dma_bits);
rdev->need_swiotlb = drm_need_swiotlb(dma_bits);
/* Registers mapping */
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index d550554a6f3f..839d619e5602 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -245,16 +245,6 @@ static bool radeon_msi_ok(struct radeon_device *rdev)
if (rdev->flags & RADEON_IS_AGP)
return false;
- /*
- * Older chips have a HW limitation, they can only generate 40 bits
- * of address for "64-bit" MSIs which breaks on some platforms, notably
- * IBM POWER servers, so we limit them
- */
- if (rdev->family < CHIP_BONAIRE) {
- dev_info(rdev->dev, "radeon: MSI limited to 32-bit\n");
- rdev->pdev->msi_addr_mask = DMA_BIT_MASK(32);
- }
-
/* force MSI on */
if (radeon_msi == 1)
return true;
--
2.53.0

20
SPECS/linux/0099-FROMLIST-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch → SPECS/linux/0003-UPSTREAM-pwm-th1520-remove-impl-Send-Sync-for-Th1520.patch
View File

@@ -1,23 +1,31 @@
From 73a6036726de9af39038fb1e292aae2b78ecb8cf Mon Sep 17 00:00:00 2001
From f5ea398610ed7436a684a02d0d39c30cee5bba1b Mon Sep 17 00:00:00 2001
From: Alice Ryhl <aliceryhl@google.com>
Date: Thu, 18 Dec 2025 13:27:42 +0000
Subject: [PATCH 099/197] FROMLIST: pwm: th1520: remove impl Send/Sync for
Date: Mon, 23 Feb 2026 10:08:27 +0000
Subject: [PATCH 003/189] UPSTREAM: pwm: th1520: remove impl Send/Sync for
Th1520PwmDriverData
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Now that clk implements Send and Sync, we no longer need to manually
implement these traits for Th1520PwmDriverData. Thus remove the
implementations.
Signed-off-by: Alice Ryhl <aliceryhl@google.com>
Reviewed-by: Gary Guo <gary@garyguo.net>
Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Link: https://lore.kernel.org/r/20251218-clk-send-sync-v3-3-e48b2e2f1eac@google.com
Acked-by: Uwe Kleine-König <ukleinek@kernel.org>
Reviewed-by: Michal Wilczynski <m.wilczynski@samsung.com>
Signed-off-by: Alice Ryhl <aliceryhl@google.com>
Link: https://patch.msgid.link/20260223-clk-send-sync-v5-3-181bf2f35652@google.com
Signed-off-by: Miguel Ojeda <ojeda@kernel.org>
(cherry picked from commit 96f4e74cab632ea5c7e7fa996a28337283ecca11)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/pwm/pwm_th1520.rs | 15 ---------------
1 file changed, 15 deletions(-)
diff --git a/drivers/pwm/pwm_th1520.rs b/drivers/pwm/pwm_th1520.rs
index 8ae8f852ec02..2c8afda2fc7f 100644
index 36567fc17dcc..ddd44a5ce497 100644
--- a/drivers/pwm/pwm_th1520.rs
+++ b/drivers/pwm/pwm_th1520.rs
@@ -96,21 +96,6 @@ struct Th1520PwmDriverData {

65
SPECS/linux/0004-UPSTREAM-ALSA-hda-intel-Make-MSI-address-limit-based.patch
View File

@@ -1,65 +0,0 @@
From 78b7e3c01469c1005d160428a6eb3ed6fa6a27b2 Mon Sep 17 00:00:00 2001
From: Vivian Wang <wangruikang@iscas.ac.cn>
Date: Thu, 29 Jan 2026 09:56:09 +0800
Subject: [PATCH 004/197] UPSTREAM: ALSA: hda/intel: Make MSI address limit
based on the device DMA limit
The hda/intel driver restricts the MSI message address for devices which do
not advertise full 64-bit DMA address space support to 32-bit due to the
former restrictions of the PCI/MSI code which only allowed either 32-bit or
a full 64-bit address range.
This does not work on platforms which have a MSI doorbell address above the
32-bit boundary but do not support the full 64 bit address range.
The PCI/MSI core converted this binary decision to a DMA_BIT_MASK() based
decision, which allows to describe the device limitations precisely.
Convert the driver to provide the exact DMA address limitations to the
PCI/MSI core. That allows devices which do not support the full 64-bit
address space to work on platforms which have a MSI doorbell address above
the 32-bit limit as long as it is within the hardware's addressable range.
[ tglx: Massage changelog ]
Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Acked-by: Takashi Iwai <tiwai@suse.de>
Link: https://patch.msgid.link/20260129-pci-msi-addr-mask-v4-4-70da998f2750@iscas.ac.cn
(cherry picked from commit cb9b6f9d2be6bda1b0117b147df40f982ce06888)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
sound/hda/controllers/intel.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/sound/hda/controllers/intel.c b/sound/hda/controllers/intel.c
index 9aea3fbc22cf..c8fa4e500fc0 100644
--- a/sound/hda/controllers/intel.c
+++ b/sound/hda/controllers/intel.c
@@ -1905,11 +1905,6 @@ static int azx_first_init(struct azx *chip)
chip->gts_present = true;
#endif
- if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) {
- dev_dbg(card->dev, "Disabling 64bit MSI\n");
- pci->msi_addr_mask = DMA_BIT_MASK(32);
- }
-
pci_set_master(pci);
gcap = azx_readw(chip, GCAP);
@@ -1960,6 +1955,11 @@ static int azx_first_init(struct azx *chip)
dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
dma_set_max_seg_size(&pci->dev, UINT_MAX);
+ if (chip->msi && chip->driver_caps & AZX_DCAPS_NO_MSI64) {
+ dev_dbg(card->dev, "Restricting MSI to %u-bit\n", dma_bits);
+ pci->msi_addr_mask = DMA_BIT_MASK(dma_bits);
+ }
+
/* read number of streams from GCAP register instead of using
* hardcoded value
*/
--
2.53.0

21
SPECS/linux/0123-FROMLIST-net-spacemit-Remove-unused-buff_addr-fields.patch → SPECS/linux/0004-UPSTREAM-net-spacemit-Remove-unused-buff_addr-fields.patch
View File

@@ -1,24 +1,27 @@
From 7229dc8b0f06bec686e105dfde2c8a0b97146932 Mon Sep 17 00:00:00 2001
From 449c3654235a6f4213741bf0b3a0fcde8a17d1da Mon Sep 17 00:00:00 2001
From: Vivian Wang <wangruikang@iscas.ac.cn>
Date: Tue, 3 Mar 2026 17:24:18 +0800
Subject: [PATCH 123/197] FROMLIST: net: spacemit: Remove unused buff_addr
Date: Thu, 5 Mar 2026 15:00:29 +0800
Subject: [PATCH 004/189] UPSTREAM: net: spacemit: Remove unused buff_addr
fields
These were never used. Just remove them.
Fixes: bfec6d7f2001 ("net: spacemit: Add K1 Ethernet MAC")
No functional change intended.
Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
Link: https://lore.kernel.org/r/20260303-k1-ethernet-more-fixes-v1-1-0ab0122fdd14@iscas.ac.cn
Link: https://patch.msgid.link/20260305-k1-ethernet-cleanup-buff_addr-v1-1-e978ef119231@iscas.ac.cn
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
(cherry picked from commit 70eba59f92076d84264762d63d30532685943017)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/net/ethernet/spacemit/k1_emac.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/net/ethernet/spacemit/k1_emac.c b/drivers/net/ethernet/spacemit/k1_emac.c
index 52c0c00a471f..359b409f8203 100644
index 15d43e4a748b..f7f16397a2c2 100644
--- a/drivers/net/ethernet/spacemit/k1_emac.c
+++ b/drivers/net/ethernet/spacemit/k1_emac.c
@@ -59,7 +59,6 @@
@@ -57,7 +57,6 @@
struct desc_buf {
u64 dma_addr;
@@ -26,7 +29,7 @@ index 52c0c00a471f..359b409f8203 100644
u16 dma_len;
u8 map_as_page;
};
@@ -72,7 +71,6 @@ struct emac_tx_desc_buffer {
@@ -70,7 +69,6 @@ struct emac_tx_desc_buffer {
struct emac_rx_desc_buffer {
struct sk_buff *skb;
u64 dma_addr;
@@ -34,7 +37,7 @@ index 52c0c00a471f..359b409f8203 100644
u16 dma_len;
u8 map_as_page;
};
@@ -355,7 +353,6 @@ static void emac_free_tx_buf(struct emac_priv *priv, int i)
@@ -340,7 +338,6 @@ static void emac_free_tx_buf(struct emac_priv *priv, int i)
buf->dma_addr = 0;
buf->map_as_page = false;

16
SPECS/linux/0135-FROMLIST-dt-bindings-net-Add-support-for-Spacemit-K3.patch → SPECS/linux/0005-UPSTREAM-dt-bindings-net-Add-support-for-Spacemit-K3.patch
View File

@@ -1,7 +1,7 @@
From 2b7acee8046eef1ca4ab77acfef49da330b173e1 Mon Sep 17 00:00:00 2001
From 2c07c1823ecbd6b82b7ec042065c7f703140d97e Mon Sep 17 00:00:00 2001
From: Inochi Amaoto <inochiama@gmail.com>
Date: Thu, 12 Mar 2026 09:22:23 +0800
Subject: [PATCH 135/197] FROMLIST: dt-bindings: net: Add support for Spacemit
Date: Mon, 16 Mar 2026 09:00:37 +0800
Subject: [PATCH 005/189] UPSTREAM: dt-bindings: net: Add support for Spacemit
K3 dwmac
The GMAC IP on Spacemit K3 is almost a standard Synopsys DesignWare
@@ -11,7 +11,9 @@ Add necessary compatible string for this device.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20260312012232.373713-2-inochiama@gmail.com
Link: https://patch.msgid.link/20260316010041.164360-2-inochiama@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
(cherry picked from commit bb30400a566c7a6a9355873344ec63e2c6310e2c)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../devicetree/bindings/net/snps,dwmac.yaml | 2 +
@@ -20,10 +22,10 @@ Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
create mode 100644 Documentation/devicetree/bindings/net/spacemit,k3-dwmac.yaml
diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
index dd3c72e8363e..faa598c19bf7 100644
index 38bc34dc4f09..98ebb6276bc6 100644
--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
@@ -108,6 +108,7 @@ properties:
@@ -109,6 +109,7 @@ properties:
- snps,dwmac-5.10a
- snps,dwmac-5.20
- snps,dwmac-5.30a
@@ -31,7 +33,7 @@ index dd3c72e8363e..faa598c19bf7 100644
- snps,dwxgmac
- snps,dwxgmac-2.10
- sophgo,sg2042-dwmac
@@ -653,6 +654,7 @@ allOf:
@@ -656,6 +657,7 @@ allOf:
- snps,dwmac-5.10a
- snps,dwmac-5.20
- snps,dwmac-5.30a

64
SPECS/linux/0005-UPSTREAM-riscv-dts-sophgo-enable-hardware-clock-RTC-.patch
View File

@@ -1,64 +0,0 @@
From 7a901579383a362861888e45a0a7dd1771f1ab22 Mon Sep 17 00:00:00 2001
From: Michael Orlitzky <michael@orlitzky.com>
Date: Wed, 7 Jan 2026 06:29:22 -0500
Subject: [PATCH 005/197] UPSTREAM: riscv: dts: sophgo: enable hardware clock
(RTC) on the Milk-V Pioneer
These boards have a working hardware clock if you put a CR-1220
battery in them. We enable it using information from a 6.1.x vendor
kernel.
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Michael Orlitzky <michael@orlitzky.com>
Link: https://lore.kernel.org/r/20260107112922.20013-2-michael@orlitzky.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
(cherry picked from commit 9e81c522680db5998c872fb91ff7877cf3d8ff42)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
index 54d8386bf9c0..ecf8c1e29079 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
@@ -52,6 +52,17 @@ &emmc {
status = "okay";
};
+&i2c0 {
+ pinctrl-0 = <&i2c0_cfg>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ rtc: rtc@68 {
+ compatible = "dallas,ds1307";
+ reg = <0x68>;
+ };
+};
+
&i2c1 {
pinctrl-0 = <&i2c1_cfg>;
pinctrl-names = "default";
@@ -89,6 +100,16 @@ sdhci-emmc-rst-pwr-pins {
};
};
+ i2c0_cfg: i2c0-cfg {
+ i2c0-pins {
+ pinmux = <PINMUX(PIN_IIC0_SDA, 0)>,
+ <PINMUX(PIN_IIC0_SCL, 0)>;
+ bias-pull-up;
+ drive-strength-microamp = <26800>;
+ input-schmitt-enable;
+ };
+ };
+
i2c1_cfg: i2c1-cfg {
i2c1-pins {
pinmux = <PINMUX(PIN_IIC1_SDA, 0)>,
--
2.53.0

10
SPECS/linux/0136-FROMLIST-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch → SPECS/linux/0006-UPSTREAM-net-stmmac-platform-Add-snps-dwmac-5.40a-IP.patch
View File

@@ -1,7 +1,7 @@
From 694274523c17134135aab0e1bfa76ba8ca797fea Mon Sep 17 00:00:00 2001
From 8fba87a4a682273e6c2a8964363c3cc0e5e8e649 Mon Sep 17 00:00:00 2001
From: Inochi Amaoto <inochiama@gmail.com>
Date: Thu, 12 Mar 2026 09:22:24 +0800
Subject: [PATCH 136/197] FROMLIST: net: stmmac: platform: Add snps,dwmac-5.40a
Date: Mon, 16 Mar 2026 09:00:38 +0800
Subject: [PATCH 006/189] UPSTREAM: net: stmmac: platform: Add snps,dwmac-5.40a
IP compatible string
Add compatible string for 5.40a version that can avoid to define some
@@ -9,7 +9,9 @@ platform data in the glue layer.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://lore.kernel.org/r/20260312012232.373713-3-inochiama@gmail.com
Link: https://patch.msgid.link/20260316010041.164360-3-inochiama@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
(cherry picked from commit d35aa97ea908a17809358a981bef6cd752f2e8a0)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 +

654
SPECS/linux/0006-UPSTREAM-riscv-dts-sophgo-Move-PLIC-and-CLINT-node-i.patch
View File

@@ -1,654 +0,0 @@
From 107a16b85bc5b3e1fc3f301fd6e83054dc3e6a62 Mon Sep 17 00:00:00 2001
From: Inochi Amaoto <inochiama@gmail.com>
Date: Tue, 13 Jan 2026 10:38:26 +0800
Subject: [PATCH 006/197] UPSTREAM: riscv: dts: sophgo: Move PLIC and CLINT
node into CPU dtsi
As we have a separate CPU dtsi file, move the PLIC and CLINT
node to the CPU dtsi file. This will make the sg2042.dtsi focus
on peripheral devices, and make the CPU dtsi force CPU related
devices.
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/20260113023828.790136-1-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
(cherry picked from commit 5e6836e735f9c9c5e8e1d1dce02dfed5fe566e8f)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 305 ++++++++++++++++++++
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 303 -------------------
2 files changed, 305 insertions(+), 303 deletions(-)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
index 94a4b71acad3..509488eee432 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
@@ -2189,4 +2189,309 @@ l2_cache15: cache-controller-15 {
cache-unified;
};
};
+
+ soc {
+ intc: interrupt-controller@7090000000 {
+ compatible = "sophgo,sg2042-plic", "thead,c900-plic";
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
+ interrupt-controller;
+ interrupts-extended =
+ <&cpu0_intc 11>, <&cpu0_intc 9>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>,
+ <&cpu2_intc 11>, <&cpu2_intc 9>,
+ <&cpu3_intc 11>, <&cpu3_intc 9>,
+ <&cpu4_intc 11>, <&cpu4_intc 9>,
+ <&cpu5_intc 11>, <&cpu5_intc 9>,
+ <&cpu6_intc 11>, <&cpu6_intc 9>,
+ <&cpu7_intc 11>, <&cpu7_intc 9>,
+ <&cpu8_intc 11>, <&cpu8_intc 9>,
+ <&cpu9_intc 11>, <&cpu9_intc 9>,
+ <&cpu10_intc 11>, <&cpu10_intc 9>,
+ <&cpu11_intc 11>, <&cpu11_intc 9>,
+ <&cpu12_intc 11>, <&cpu12_intc 9>,
+ <&cpu13_intc 11>, <&cpu13_intc 9>,
+ <&cpu14_intc 11>, <&cpu14_intc 9>,
+ <&cpu15_intc 11>, <&cpu15_intc 9>,
+ <&cpu16_intc 11>, <&cpu16_intc 9>,
+ <&cpu17_intc 11>, <&cpu17_intc 9>,
+ <&cpu18_intc 11>, <&cpu18_intc 9>,
+ <&cpu19_intc 11>, <&cpu19_intc 9>,
+ <&cpu20_intc 11>, <&cpu20_intc 9>,
+ <&cpu21_intc 11>, <&cpu21_intc 9>,
+ <&cpu22_intc 11>, <&cpu22_intc 9>,
+ <&cpu23_intc 11>, <&cpu23_intc 9>,
+ <&cpu24_intc 11>, <&cpu24_intc 9>,
+ <&cpu25_intc 11>, <&cpu25_intc 9>,
+ <&cpu26_intc 11>, <&cpu26_intc 9>,
+ <&cpu27_intc 11>, <&cpu27_intc 9>,
+ <&cpu28_intc 11>, <&cpu28_intc 9>,
+ <&cpu29_intc 11>, <&cpu29_intc 9>,
+ <&cpu30_intc 11>, <&cpu30_intc 9>,
+ <&cpu31_intc 11>, <&cpu31_intc 9>,
+ <&cpu32_intc 11>, <&cpu32_intc 9>,
+ <&cpu33_intc 11>, <&cpu33_intc 9>,
+ <&cpu34_intc 11>, <&cpu34_intc 9>,
+ <&cpu35_intc 11>, <&cpu35_intc 9>,
+ <&cpu36_intc 11>, <&cpu36_intc 9>,
+ <&cpu37_intc 11>, <&cpu37_intc 9>,
+ <&cpu38_intc 11>, <&cpu38_intc 9>,
+ <&cpu39_intc 11>, <&cpu39_intc 9>,
+ <&cpu40_intc 11>, <&cpu40_intc 9>,
+ <&cpu41_intc 11>, <&cpu41_intc 9>,
+ <&cpu42_intc 11>, <&cpu42_intc 9>,
+ <&cpu43_intc 11>, <&cpu43_intc 9>,
+ <&cpu44_intc 11>, <&cpu44_intc 9>,
+ <&cpu45_intc 11>, <&cpu45_intc 9>,
+ <&cpu46_intc 11>, <&cpu46_intc 9>,
+ <&cpu47_intc 11>, <&cpu47_intc 9>,
+ <&cpu48_intc 11>, <&cpu48_intc 9>,
+ <&cpu49_intc 11>, <&cpu49_intc 9>,
+ <&cpu50_intc 11>, <&cpu50_intc 9>,
+ <&cpu51_intc 11>, <&cpu51_intc 9>,
+ <&cpu52_intc 11>, <&cpu52_intc 9>,
+ <&cpu53_intc 11>, <&cpu53_intc 9>,
+ <&cpu54_intc 11>, <&cpu54_intc 9>,
+ <&cpu55_intc 11>, <&cpu55_intc 9>,
+ <&cpu56_intc 11>, <&cpu56_intc 9>,
+ <&cpu57_intc 11>, <&cpu57_intc 9>,
+ <&cpu58_intc 11>, <&cpu58_intc 9>,
+ <&cpu59_intc 11>, <&cpu59_intc 9>,
+ <&cpu60_intc 11>, <&cpu60_intc 9>,
+ <&cpu61_intc 11>, <&cpu61_intc 9>,
+ <&cpu62_intc 11>, <&cpu62_intc 9>,
+ <&cpu63_intc 11>, <&cpu63_intc 9>;
+ riscv,ndev = <224>;
+ };
+
+ clint_mswi: interrupt-controller@7094000000 {
+ compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
+ reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
+ interrupts-extended = <&cpu0_intc 3>,
+ <&cpu1_intc 3>,
+ <&cpu2_intc 3>,
+ <&cpu3_intc 3>,
+ <&cpu4_intc 3>,
+ <&cpu5_intc 3>,
+ <&cpu6_intc 3>,
+ <&cpu7_intc 3>,
+ <&cpu8_intc 3>,
+ <&cpu9_intc 3>,
+ <&cpu10_intc 3>,
+ <&cpu11_intc 3>,
+ <&cpu12_intc 3>,
+ <&cpu13_intc 3>,
+ <&cpu14_intc 3>,
+ <&cpu15_intc 3>,
+ <&cpu16_intc 3>,
+ <&cpu17_intc 3>,
+ <&cpu18_intc 3>,
+ <&cpu19_intc 3>,
+ <&cpu20_intc 3>,
+ <&cpu21_intc 3>,
+ <&cpu22_intc 3>,
+ <&cpu23_intc 3>,
+ <&cpu24_intc 3>,
+ <&cpu25_intc 3>,
+ <&cpu26_intc 3>,
+ <&cpu27_intc 3>,
+ <&cpu28_intc 3>,
+ <&cpu29_intc 3>,
+ <&cpu30_intc 3>,
+ <&cpu31_intc 3>,
+ <&cpu32_intc 3>,
+ <&cpu33_intc 3>,
+ <&cpu34_intc 3>,
+ <&cpu35_intc 3>,
+ <&cpu36_intc 3>,
+ <&cpu37_intc 3>,
+ <&cpu38_intc 3>,
+ <&cpu39_intc 3>,
+ <&cpu40_intc 3>,
+ <&cpu41_intc 3>,
+ <&cpu42_intc 3>,
+ <&cpu43_intc 3>,
+ <&cpu44_intc 3>,
+ <&cpu45_intc 3>,
+ <&cpu46_intc 3>,
+ <&cpu47_intc 3>,
+ <&cpu48_intc 3>,
+ <&cpu49_intc 3>,
+ <&cpu50_intc 3>,
+ <&cpu51_intc 3>,
+ <&cpu52_intc 3>,
+ <&cpu53_intc 3>,
+ <&cpu54_intc 3>,
+ <&cpu55_intc 3>,
+ <&cpu56_intc 3>,
+ <&cpu57_intc 3>,
+ <&cpu58_intc 3>,
+ <&cpu59_intc 3>,
+ <&cpu60_intc 3>,
+ <&cpu61_intc 3>,
+ <&cpu62_intc 3>,
+ <&cpu63_intc 3>;
+ };
+
+ clint_mtimer0: timer@70ac004000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac004000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu0_intc 7>,
+ <&cpu1_intc 7>,
+ <&cpu2_intc 7>,
+ <&cpu3_intc 7>;
+ };
+
+ clint_mtimer1: timer@70ac014000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac014000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu4_intc 7>,
+ <&cpu5_intc 7>,
+ <&cpu6_intc 7>,
+ <&cpu7_intc 7>;
+ };
+
+ clint_mtimer2: timer@70ac024000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac024000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu8_intc 7>,
+ <&cpu9_intc 7>,
+ <&cpu10_intc 7>,
+ <&cpu11_intc 7>;
+ };
+
+ clint_mtimer3: timer@70ac034000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac034000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu12_intc 7>,
+ <&cpu13_intc 7>,
+ <&cpu14_intc 7>,
+ <&cpu15_intc 7>;
+ };
+
+ clint_mtimer4: timer@70ac044000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac044000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu16_intc 7>,
+ <&cpu17_intc 7>,
+ <&cpu18_intc 7>,
+ <&cpu19_intc 7>;
+ };
+
+ clint_mtimer5: timer@70ac054000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac054000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu20_intc 7>,
+ <&cpu21_intc 7>,
+ <&cpu22_intc 7>,
+ <&cpu23_intc 7>;
+ };
+
+ clint_mtimer6: timer@70ac064000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac064000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu24_intc 7>,
+ <&cpu25_intc 7>,
+ <&cpu26_intc 7>,
+ <&cpu27_intc 7>;
+ };
+
+ clint_mtimer7: timer@70ac074000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac074000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu28_intc 7>,
+ <&cpu29_intc 7>,
+ <&cpu30_intc 7>,
+ <&cpu31_intc 7>;
+ };
+
+ clint_mtimer8: timer@70ac084000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac084000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu32_intc 7>,
+ <&cpu33_intc 7>,
+ <&cpu34_intc 7>,
+ <&cpu35_intc 7>;
+ };
+
+ clint_mtimer9: timer@70ac094000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac094000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu36_intc 7>,
+ <&cpu37_intc 7>,
+ <&cpu38_intc 7>,
+ <&cpu39_intc 7>;
+ };
+
+ clint_mtimer10: timer@70ac0a4000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu40_intc 7>,
+ <&cpu41_intc 7>,
+ <&cpu42_intc 7>,
+ <&cpu43_intc 7>;
+ };
+
+ clint_mtimer11: timer@70ac0b4000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu44_intc 7>,
+ <&cpu45_intc 7>,
+ <&cpu46_intc 7>,
+ <&cpu47_intc 7>;
+ };
+
+ clint_mtimer12: timer@70ac0c4000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu48_intc 7>,
+ <&cpu49_intc 7>,
+ <&cpu50_intc 7>,
+ <&cpu51_intc 7>;
+ };
+
+ clint_mtimer13: timer@70ac0d4000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu52_intc 7>,
+ <&cpu53_intc 7>,
+ <&cpu54_intc 7>,
+ <&cpu55_intc 7>;
+ };
+
+ clint_mtimer14: timer@70ac0e4000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu56_intc 7>,
+ <&cpu57_intc 7>,
+ <&cpu58_intc 7>,
+ <&cpu59_intc 7>;
+ };
+
+ clint_mtimer15: timer@70ac0f4000 {
+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
+ reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
+ interrupts-extended = <&cpu60_intc 7>,
+ <&cpu61_intc 7>,
+ <&cpu62_intc 7>,
+ <&cpu63_intc 7>;
+ };
+ };
};
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index ec99da39150f..e6891f95d479 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -352,309 +352,6 @@ pcie_rc3: pcie@7062800000 {
status = "disabled";
};
- clint_mswi: interrupt-controller@7094000000 {
- compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
- reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
- interrupts-extended = <&cpu0_intc 3>,
- <&cpu1_intc 3>,
- <&cpu2_intc 3>,
- <&cpu3_intc 3>,
- <&cpu4_intc 3>,
- <&cpu5_intc 3>,
- <&cpu6_intc 3>,
- <&cpu7_intc 3>,
- <&cpu8_intc 3>,
- <&cpu9_intc 3>,
- <&cpu10_intc 3>,
- <&cpu11_intc 3>,
- <&cpu12_intc 3>,
- <&cpu13_intc 3>,
- <&cpu14_intc 3>,
- <&cpu15_intc 3>,
- <&cpu16_intc 3>,
- <&cpu17_intc 3>,
- <&cpu18_intc 3>,
- <&cpu19_intc 3>,
- <&cpu20_intc 3>,
- <&cpu21_intc 3>,
- <&cpu22_intc 3>,
- <&cpu23_intc 3>,
- <&cpu24_intc 3>,
- <&cpu25_intc 3>,
- <&cpu26_intc 3>,
- <&cpu27_intc 3>,
- <&cpu28_intc 3>,
- <&cpu29_intc 3>,
- <&cpu30_intc 3>,
- <&cpu31_intc 3>,
- <&cpu32_intc 3>,
- <&cpu33_intc 3>,
- <&cpu34_intc 3>,
- <&cpu35_intc 3>,
- <&cpu36_intc 3>,
- <&cpu37_intc 3>,
- <&cpu38_intc 3>,
- <&cpu39_intc 3>,
- <&cpu40_intc 3>,
- <&cpu41_intc 3>,
- <&cpu42_intc 3>,
- <&cpu43_intc 3>,
- <&cpu44_intc 3>,
- <&cpu45_intc 3>,
- <&cpu46_intc 3>,
- <&cpu47_intc 3>,
- <&cpu48_intc 3>,
- <&cpu49_intc 3>,
- <&cpu50_intc 3>,
- <&cpu51_intc 3>,
- <&cpu52_intc 3>,
- <&cpu53_intc 3>,
- <&cpu54_intc 3>,
- <&cpu55_intc 3>,
- <&cpu56_intc 3>,
- <&cpu57_intc 3>,
- <&cpu58_intc 3>,
- <&cpu59_intc 3>,
- <&cpu60_intc 3>,
- <&cpu61_intc 3>,
- <&cpu62_intc 3>,
- <&cpu63_intc 3>;
- };
-
- clint_mtimer0: timer@70ac004000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac004000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu0_intc 7>,
- <&cpu1_intc 7>,
- <&cpu2_intc 7>,
- <&cpu3_intc 7>;
- };
-
- clint_mtimer1: timer@70ac014000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac014000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu4_intc 7>,
- <&cpu5_intc 7>,
- <&cpu6_intc 7>,
- <&cpu7_intc 7>;
- };
-
- clint_mtimer2: timer@70ac024000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac024000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu8_intc 7>,
- <&cpu9_intc 7>,
- <&cpu10_intc 7>,
- <&cpu11_intc 7>;
- };
-
- clint_mtimer3: timer@70ac034000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac034000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu12_intc 7>,
- <&cpu13_intc 7>,
- <&cpu14_intc 7>,
- <&cpu15_intc 7>;
- };
-
- clint_mtimer4: timer@70ac044000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac044000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu16_intc 7>,
- <&cpu17_intc 7>,
- <&cpu18_intc 7>,
- <&cpu19_intc 7>;
- };
-
- clint_mtimer5: timer@70ac054000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac054000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu20_intc 7>,
- <&cpu21_intc 7>,
- <&cpu22_intc 7>,
- <&cpu23_intc 7>;
- };
-
- clint_mtimer6: timer@70ac064000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac064000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu24_intc 7>,
- <&cpu25_intc 7>,
- <&cpu26_intc 7>,
- <&cpu27_intc 7>;
- };
-
- clint_mtimer7: timer@70ac074000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac074000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu28_intc 7>,
- <&cpu29_intc 7>,
- <&cpu30_intc 7>,
- <&cpu31_intc 7>;
- };
-
- clint_mtimer8: timer@70ac084000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac084000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu32_intc 7>,
- <&cpu33_intc 7>,
- <&cpu34_intc 7>,
- <&cpu35_intc 7>;
- };
-
- clint_mtimer9: timer@70ac094000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac094000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu36_intc 7>,
- <&cpu37_intc 7>,
- <&cpu38_intc 7>,
- <&cpu39_intc 7>;
- };
-
- clint_mtimer10: timer@70ac0a4000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu40_intc 7>,
- <&cpu41_intc 7>,
- <&cpu42_intc 7>,
- <&cpu43_intc 7>;
- };
-
- clint_mtimer11: timer@70ac0b4000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu44_intc 7>,
- <&cpu45_intc 7>,
- <&cpu46_intc 7>,
- <&cpu47_intc 7>;
- };
-
- clint_mtimer12: timer@70ac0c4000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu48_intc 7>,
- <&cpu49_intc 7>,
- <&cpu50_intc 7>,
- <&cpu51_intc 7>;
- };
-
- clint_mtimer13: timer@70ac0d4000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu52_intc 7>,
- <&cpu53_intc 7>,
- <&cpu54_intc 7>,
- <&cpu55_intc 7>;
- };
-
- clint_mtimer14: timer@70ac0e4000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu56_intc 7>,
- <&cpu57_intc 7>,
- <&cpu58_intc 7>,
- <&cpu59_intc 7>;
- };
-
- clint_mtimer15: timer@70ac0f4000 {
- compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>;
- reg-names = "mtimecmp";
- interrupts-extended = <&cpu60_intc 7>,
- <&cpu61_intc 7>,
- <&cpu62_intc 7>,
- <&cpu63_intc 7>;
- };
-
- intc: interrupt-controller@7090000000 {
- compatible = "sophgo,sg2042-plic", "thead,c900-plic";
- #address-cells = <0>;
- #interrupt-cells = <2>;
- reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
- interrupt-controller;
- interrupts-extended =
- <&cpu0_intc 11>, <&cpu0_intc 9>,
- <&cpu1_intc 11>, <&cpu1_intc 9>,
- <&cpu2_intc 11>, <&cpu2_intc 9>,
- <&cpu3_intc 11>, <&cpu3_intc 9>,
- <&cpu4_intc 11>, <&cpu4_intc 9>,
- <&cpu5_intc 11>, <&cpu5_intc 9>,
- <&cpu6_intc 11>, <&cpu6_intc 9>,
- <&cpu7_intc 11>, <&cpu7_intc 9>,
- <&cpu8_intc 11>, <&cpu8_intc 9>,
- <&cpu9_intc 11>, <&cpu9_intc 9>,
- <&cpu10_intc 11>, <&cpu10_intc 9>,
- <&cpu11_intc 11>, <&cpu11_intc 9>,
- <&cpu12_intc 11>, <&cpu12_intc 9>,
- <&cpu13_intc 11>, <&cpu13_intc 9>,
- <&cpu14_intc 11>, <&cpu14_intc 9>,
- <&cpu15_intc 11>, <&cpu15_intc 9>,
- <&cpu16_intc 11>, <&cpu16_intc 9>,
- <&cpu17_intc 11>, <&cpu17_intc 9>,
- <&cpu18_intc 11>, <&cpu18_intc 9>,
- <&cpu19_intc 11>, <&cpu19_intc 9>,
- <&cpu20_intc 11>, <&cpu20_intc 9>,
- <&cpu21_intc 11>, <&cpu21_intc 9>,
- <&cpu22_intc 11>, <&cpu22_intc 9>,
- <&cpu23_intc 11>, <&cpu23_intc 9>,
- <&cpu24_intc 11>, <&cpu24_intc 9>,
- <&cpu25_intc 11>, <&cpu25_intc 9>,
- <&cpu26_intc 11>, <&cpu26_intc 9>,
- <&cpu27_intc 11>, <&cpu27_intc 9>,
- <&cpu28_intc 11>, <&cpu28_intc 9>,
- <&cpu29_intc 11>, <&cpu29_intc 9>,
- <&cpu30_intc 11>, <&cpu30_intc 9>,
- <&cpu31_intc 11>, <&cpu31_intc 9>,
- <&cpu32_intc 11>, <&cpu32_intc 9>,
- <&cpu33_intc 11>, <&cpu33_intc 9>,
- <&cpu34_intc 11>, <&cpu34_intc 9>,
- <&cpu35_intc 11>, <&cpu35_intc 9>,
- <&cpu36_intc 11>, <&cpu36_intc 9>,
- <&cpu37_intc 11>, <&cpu37_intc 9>,
- <&cpu38_intc 11>, <&cpu38_intc 9>,
- <&cpu39_intc 11>, <&cpu39_intc 9>,
- <&cpu40_intc 11>, <&cpu40_intc 9>,
- <&cpu41_intc 11>, <&cpu41_intc 9>,
- <&cpu42_intc 11>, <&cpu42_intc 9>,
- <&cpu43_intc 11>, <&cpu43_intc 9>,
- <&cpu44_intc 11>, <&cpu44_intc 9>,
- <&cpu45_intc 11>, <&cpu45_intc 9>,
- <&cpu46_intc 11>, <&cpu46_intc 9>,
- <&cpu47_intc 11>, <&cpu47_intc 9>,
- <&cpu48_intc 11>, <&cpu48_intc 9>,
- <&cpu49_intc 11>, <&cpu49_intc 9>,
- <&cpu50_intc 11>, <&cpu50_intc 9>,
- <&cpu51_intc 11>, <&cpu51_intc 9>,
- <&cpu52_intc 11>, <&cpu52_intc 9>,
- <&cpu53_intc 11>, <&cpu53_intc 9>,
- <&cpu54_intc 11>, <&cpu54_intc 9>,
- <&cpu55_intc 11>, <&cpu55_intc 9>,
- <&cpu56_intc 11>, <&cpu56_intc 9>,
- <&cpu57_intc 11>, <&cpu57_intc 9>,
- <&cpu58_intc 11>, <&cpu58_intc 9>,
- <&cpu59_intc 11>, <&cpu59_intc 9>,
- <&cpu60_intc 11>, <&cpu60_intc 9>,
- <&cpu61_intc 11>, <&cpu61_intc 9>,
- <&cpu62_intc 11>, <&cpu62_intc 9>,
- <&cpu63_intc 11>, <&cpu63_intc 9>;
- riscv,ndev = <224>;
- };
-
rstgen: reset-controller@7030013000 {
compatible = "sophgo,sg2042-reset";
reg = <0x00000070 0x30013000 0x00000000 0x0000000c>;
--
2.53.0

18
SPECS/linux/0137-FROMLIST-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch → SPECS/linux/0007-UPSTREAM-net-stmmac-Add-glue-layer-for-Spacemit-K3-S.patch
View File

@@ -1,7 +1,7 @@
From 038576ef6e99d82a7a4fba7ce2c805ef336616df Mon Sep 17 00:00:00 2001
From 7ee6f27118fef0ff2cc4806d39c56dc101cebca5 Mon Sep 17 00:00:00 2001
From: Inochi Amaoto <inochiama@gmail.com>
Date: Thu, 12 Mar 2026 09:22:25 +0800
Subject: [PATCH 137/197] FROMLIST: net: stmmac: Add glue layer for Spacemit K3
Date: Mon, 16 Mar 2026 09:00:39 +0800
Subject: [PATCH 007/189] UPSTREAM: net: stmmac: Add glue layer for Spacemit K3
SoC
The ethernet controller on Spacemit K3 SoC is Synopsys DesignWare
@@ -16,7 +16,9 @@ Add Spacemit dwmac driver support on the Spacemit K3 SoC.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://lore.kernel.org/r/20260312012232.373713-4-inochiama@gmail.com
Link: https://patch.msgid.link/20260316010041.164360-4-inochiama@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
(cherry picked from commit 30f0ba420ed3fb9a16d55523ae3c1b43a6f00e22)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 +
@@ -26,7 +28,7 @@ Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index 907fe2e927f0..583a4692f5da 100644
index 07088d03dbab..d3a6ab7383fc 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -216,6 +216,18 @@ config DWMAC_SOPHGO
@@ -49,7 +51,7 @@ index 907fe2e927f0..583a4692f5da 100644
tristate "StarFive dwmac support"
depends on OF && (ARCH_STARFIVE || COMPILE_TEST)
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index 7bf528731034..9e32045631d8 100644
index c9263987ef8d..945c5354eced 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_DWMAC_RZN1) += dwmac-rzn1.o
@@ -62,7 +64,7 @@ index 7bf528731034..9e32045631d8 100644
obj-$(CONFIG_DWMAC_STM32) += dwmac-stm32.o
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c
new file mode 100644
index 000000000000..c47f26385831
index 000000000000..223754cc5c79
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-spacemit.c
@@ -0,0 +1,227 @@
@@ -247,7 +249,7 @@ index 000000000000..c47f26385831
+ offset);
+ if (IS_ERR(apmu))
+ return dev_err_probe(dev, PTR_ERR(apmu),
+ "Failed to get apmu regmap\n");
+ "Failed to get apmu regmap\n");
+
+ dwmac->apmu = apmu;
+ dwmac->ctrl_offset = offset[0];

216
SPECS/linux/0007-UPSTREAM-riscv-dts-sophgo-fix-the-node-order-of-SG20.patch
View File

@@ -1,216 +0,0 @@
From bf2aa7ef1e30a9de2e5d34020d0f988491019e49 Mon Sep 17 00:00:00 2001
From: Inochi Amaoto <inochiama@gmail.com>
Date: Tue, 13 Jan 2026 10:38:27 +0800
Subject: [PATCH 007/197] UPSTREAM: riscv: dts: sophgo: fix the node order of
SG2042 peripheral
In sg2042.dtsi, some peripheral device node does not follow the
address order. Reorder them in ascending order by address.
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/20260113023828.790136-2-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
(cherry picked from commit ebb87dd74c34a76e1e93041e9329cf9269be35ed)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 176 ++++++++++++-------------
1 file changed, 88 insertions(+), 88 deletions(-)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index e6891f95d479..9fddf3f0b3b9 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -264,94 +264,6 @@ clkgen: clock-controller@7030012000 {
#clock-cells = <1>;
};
- pcie_rc0: pcie@7060000000 {
- compatible = "sophgo,sg2042-pcie-host";
- device_type = "pci";
- reg = <0x70 0x60000000 0x0 0x00800000>,
- <0x40 0x00000000 0x0 0x00001000>;
- reg-names = "reg", "cfg";
- linux,pci-domain = <0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>,
- <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>,
- <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>,
- <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
- <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
- bus-range = <0x0 0xff>;
- vendor-id = <0x1f1c>;
- device-id = <0x2042>;
- cdns,no-bar-match-nbits = <48>;
- msi-parent = <&msi>;
- status = "disabled";
- };
-
- pcie_rc1: pcie@7060800000 {
- compatible = "sophgo,sg2042-pcie-host";
- device_type = "pci";
- reg = <0x70 0x60800000 0x0 0x00800000>,
- <0x44 0x00000000 0x0 0x00001000>;
- reg-names = "reg", "cfg";
- linux,pci-domain = <1>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>,
- <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>,
- <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>,
- <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>,
- <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>;
- bus-range = <0x0 0xff>;
- vendor-id = <0x1f1c>;
- device-id = <0x2042>;
- cdns,no-bar-match-nbits = <48>;
- msi-parent = <&msi>;
- status = "disabled";
- };
-
- pcie_rc2: pcie@7062000000 {
- compatible = "sophgo,sg2042-pcie-host";
- device_type = "pci";
- reg = <0x70 0x62000000 0x0 0x00800000>,
- <0x48 0x00000000 0x0 0x00001000>;
- reg-names = "reg", "cfg";
- linux,pci-domain = <2>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>,
- <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>,
- <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>,
- <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>,
- <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>;
- bus-range = <0x0 0xff>;
- vendor-id = <0x1f1c>;
- device-id = <0x2042>;
- cdns,no-bar-match-nbits = <48>;
- msi-parent = <&msi>;
- status = "disabled";
- };
-
- pcie_rc3: pcie@7062800000 {
- compatible = "sophgo,sg2042-pcie-host";
- device_type = "pci";
- reg = <0x70 0x62800000 0x0 0x00800000>,
- <0x4c 0x00000000 0x0 0x00001000>;
- reg-names = "reg", "cfg";
- linux,pci-domain = <3>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>,
- <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>,
- <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>,
- <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>,
- <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>;
- bus-range = <0x0 0xff>;
- vendor-id = <0x1f1c>;
- device-id = <0x2042>;
- cdns,no-bar-match-nbits = <48>;
- msi-parent = <&msi>;
- status = "disabled";
- };
-
rstgen: reset-controller@7030013000 {
compatible = "sophgo,sg2042-reset";
reg = <0x00000070 0x30013000 0x00000000 0x0000000c>;
@@ -486,5 +398,93 @@ sd: mmc@704002b000 {
"timer";
status = "disabled";
};
+
+ pcie_rc0: pcie@7060000000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x60000000 0x0 0x00800000>,
+ <0x40 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>,
+ <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>,
+ <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>,
+ <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
+ <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
+
+ pcie_rc1: pcie@7060800000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x60800000 0x0 0x00800000>,
+ <0x44 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>,
+ <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>,
+ <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>,
+ <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>,
+ <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
+
+ pcie_rc2: pcie@7062000000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x62000000 0x0 0x00800000>,
+ <0x48 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>,
+ <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>,
+ <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>,
+ <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>,
+ <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
+
+ pcie_rc3: pcie@7062800000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x62800000 0x0 0x00800000>,
+ <0x4c 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <3>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>,
+ <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>,
+ <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>,
+ <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>,
+ <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
};
};
--
2.53.0

53
SPECS/linux/0008-UPSTREAM-drm-imagination-Improve-handling-of-unknown.patch Normal file
View File

@@ -0,0 +1,53 @@
From 7b3b4867cb677527898f6f31e75f7cc32a22bc7d Mon Sep 17 00:00:00 2001
From: Matt Coster <matt.coster@imgtec.com>
Date: Fri, 6 Feb 2026 16:02:12 +0000
Subject: [PATCH 008/189] UPSTREAM: drm/imagination: Improve handling of
unknown FWCCB commands
A couple small changes:
- Validate the magic value at the head of FWCCB commands, and
- Mask off the magic value before logging unknown command types to make
them easier to interpret on sight.
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Link: https://patch.msgid.link/20260206-improve-bad-fwccb-cmd-v1-1-831a852ca127@imgtec.com
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
(cherry picked from commit c7384288d9266e52cd35aadb1749872caf3c0257)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/gpu/drm/imagination/pvr_ccb.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/imagination/pvr_ccb.c b/drivers/gpu/drm/imagination/pvr_ccb.c
index 00c236d24acc..d2829a3b3f8b 100644
--- a/drivers/gpu/drm/imagination/pvr_ccb.c
+++ b/drivers/gpu/drm/imagination/pvr_ccb.c
@@ -136,6 +136,14 @@ pvr_ccb_slot_available_locked(struct pvr_ccb *pvr_ccb, u32 *write_offset)
static void
process_fwccb_command(struct pvr_device *pvr_dev, struct rogue_fwif_fwccb_cmd *cmd)
{
+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
+
+ if ((cmd->cmd_type & ROGUE_CMD_MAGIC_DWORD_MASK) != ROGUE_CMD_MAGIC_DWORD_SHIFTED) {
+ drm_warn_once(drm_dev, "Received FWCCB command with bad magic value; ignoring (type=0x%08x)\n",
+ cmd->cmd_type);
+ return;
+ }
+
switch (cmd->cmd_type) {
case ROGUE_FWIF_FWCCB_CMD_REQUEST_GPU_RESTART:
pvr_power_reset(pvr_dev, false);
@@ -151,8 +159,8 @@ process_fwccb_command(struct pvr_device *pvr_dev, struct rogue_fwif_fwccb_cmd *c
break;
default:
- drm_info(from_pvr_device(pvr_dev), "Received unknown FWCCB command %x\n",
- cmd->cmd_type);
+ drm_info(drm_dev, "Received unknown FWCCB command (type=%d)\n",
+ cmd->cmd_type & ~ROGUE_CMD_MAGIC_DWORD_MASK);
break;
}
}
--
2.53.0

38
SPECS/linux/0008-UPSTREAM-riscv-dts-spacemit-Enable-i2c8-adapter-for-.patch
View File

@@ -1,38 +0,0 @@
From a8bdb7fd857441d84d440c630eeebb3c7b9d06af Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas <javierm@redhat.com>
Date: Sat, 6 Dec 2025 14:44:53 +0100
Subject: [PATCH 008/197] UPSTREAM: riscv: dts: spacemit: Enable i2c8 adapter
for Milk-V Jupiter
The adapter is used to access the SpacemiT P1 PMIC present in this board.
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20251206134532.1741648-2-javierm@redhat.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
(cherry picked from commit f33ccc2316304f3a71e40e53f1568e75042b0a4b)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts
index 28afd39b28da..aa425f02c1f4 100644
--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts
@@ -72,6 +72,12 @@ &pdma {
status = "okay";
};
+&i2c8 {
+ pinctrl-0 = <&i2c8_cfg>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_2_cfg>;
--
2.53.0

40
SPECS/linux/0009-UPSTREAM-drm-imagination-Mark-FWCCB_CMD_UPDATE_STATS.patch Normal file
View File

@@ -0,0 +1,40 @@
From b3a4537106b2ae5fd34d1dc4b093cbceff72b418 Mon Sep 17 00:00:00 2001
From: Matt Coster <matt.coster@imgtec.com>
Date: Fri, 6 Feb 2026 16:02:13 +0000
Subject: [PATCH 009/189] UPSTREAM: drm/imagination: Mark
FWCCB_CMD_UPDATE_STATS as known
Suppress the "unknown type" warning when processing a FWCCB command of
type CMD_UPDATE_STATS which is known but (currently) unused.
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Link: https://patch.msgid.link/20260206-improve-bad-fwccb-cmd-v1-2-831a852ca127@imgtec.com
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
(cherry picked from commit 4af267ce3441e10198daa52a8cc4b5cb4575d06f)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/gpu/drm/imagination/pvr_ccb.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/imagination/pvr_ccb.c b/drivers/gpu/drm/imagination/pvr_ccb.c
index d2829a3b3f8b..f89db5e3baa2 100644
--- a/drivers/gpu/drm/imagination/pvr_ccb.c
+++ b/drivers/gpu/drm/imagination/pvr_ccb.c
@@ -158,6 +158,14 @@ process_fwccb_command(struct pvr_device *pvr_dev, struct rogue_fwif_fwccb_cmd *c
pvr_free_list_process_grow_req(pvr_dev, &cmd->cmd_data.cmd_free_list_gs);
break;
+ case ROGUE_FWIF_FWCCB_CMD_UPDATE_STATS:
+ /*
+ * We currently have no infrastructure for processing these
+ * stats. It may be added in the future, but for now just
+ * suppress the "unknown" warning when receiving this command.
+ */
+ break;
+
default:
drm_info(drm_dev, "Received unknown FWCCB command (type=%d)\n",
cmd->cmd_type & ~ROGUE_CMD_MAGIC_DWORD_MASK);
--
2.53.0

51
SPECS/linux/0009-UPSTREAM-riscv-dts-spacemit-Define-fixed-regulators-.patch
View File

@@ -1,51 +0,0 @@
From 57c223973625219896f33076129c53137bdc5a62 Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas <javierm@redhat.com>
Date: Sat, 6 Dec 2025 14:44:54 +0100
Subject: [PATCH 009/197] UPSTREAM: riscv: dts: spacemit: Define fixed
regulators for Milk-V Jupiter
Define the DC power input and the 4v power as fixed regulator supplies.
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20251206134532.1741648-3-javierm@redhat.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
(cherry picked from commit ae9d03f8aec76c1bff21083b67c211238d7c57b1)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../boot/dts/spacemit/k1-milkv-jupiter.dts | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts
index aa425f02c1f4..5babed4d7094 100644
--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts
@@ -20,6 +20,25 @@ aliases {
chosen {
stdout-path = "serial0";
};
+
+ reg_dc_in: dc-in-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_in_12v";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vcc_4v: vcc-4v {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_4v";
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <4000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ vin-supply = <&reg_dc_in>;
+ };
};
&eth0 {
--
2.53.0

144
SPECS/linux/0010-UPSTREAM-drm-imagination-Improve-firmware-power-off-.patch Normal file
View File

@@ -0,0 +1,144 @@
From bbb49c5f2c5d031657e21691ead99a040b669ec1 Mon Sep 17 00:00:00 2001
From: Brajesh Gupta <brajesh.gupta@imgtec.com>
Date: Fri, 13 Mar 2026 06:38:24 +0000
Subject: [PATCH 010/189] UPSTREAM: drm/imagination: Improve firmware power off
for layout_mars config
In layout_mars HW config, Firmware MCU moved from Sidekick to new Mars
domain so Firmware takes care of powering down Sidekick/Jones and SLC.
Skip checks for those from kernel and check idle bits for Firmware MCU
and system arbiter excluding SOCIF.
Signed-off-by: Brajesh Gupta <brajesh.gupta@imgtec.com>
Reviewed-by: Matt Coster <matt.coster@imgtec.com>
Link: https://patch.msgid.link/20260313-b4-staging-layout_mars_base-v2-1-9e3c251d278e@imgtec.com
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
(cherry picked from commit 51e39ceeca7e85a3b9ca533502a404eb5f3b0f02)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../gpu/drm/imagination/pvr_fw_startstop.c | 85 +++++++++++++------
1 file changed, 57 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/imagination/pvr_fw_startstop.c b/drivers/gpu/drm/imagination/pvr_fw_startstop.c
index dcbb9903e791..6ae0489f7e2e 100644
--- a/drivers/gpu/drm/imagination/pvr_fw_startstop.c
+++ b/drivers/gpu/drm/imagination/pvr_fw_startstop.c
@@ -209,18 +209,32 @@ pvr_fw_stop(struct pvr_device *pvr_dev)
ROGUE_CR_SIDEKICK_IDLE_SOCIF_EN |
ROGUE_CR_SIDEKICK_IDLE_HOSTIF_EN);
bool skip_garten_idle = false;
+ u64 layout_mars_value = 0;
+ bool layout_mars = false;
+ bool meta_fw = pvr_dev->fw_dev.processor_type == PVR_FW_PROCESSOR_TYPE_META;
u32 reg_value;
int err;
+ if (PVR_FEATURE_VALUE(pvr_dev, layout_mars, &layout_mars_value) == 0)
+ layout_mars = layout_mars_value > 0;
+
/*
- * Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper.
- * For cores with the LAYOUT_MARS feature, SIDEKICK would have been
+ * For cores with the LAYOUT_MARS feature, SIDEKICK and SLC would have been
* powered down by the FW.
*/
- err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_mask,
- sidekick_idle_mask, POLL_TIMEOUT_USEC);
- if (err)
- return err;
+ if (!layout_mars) {
+ /* Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper. */
+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_mask,
+ sidekick_idle_mask, POLL_TIMEOUT_USEC);
+ if (err)
+ return err;
+
+ /* Wait for SLC to signal IDLE. */
+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SLC_IDLE, ROGUE_CR_SLC_IDLE_MASKFULL,
+ ROGUE_CR_SLC_IDLE_MASKFULL, POLL_TIMEOUT_USEC);
+ if (err)
+ return err;
+ }
/* Unset MTS DM association with threads. */
pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC,
@@ -270,27 +284,25 @@ pvr_fw_stop(struct pvr_device *pvr_dev)
return err;
/*
- * Wait for SLC to signal IDLE.
- * For cores with the LAYOUT_MARS feature, SLC would have been powered
- * down by the FW.
+ * For cores with the LAYOUT_MARS feature, SIDEKICK and SLC would have been
+ * powered down by the FW.
*/
- err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SLC_IDLE,
- ROGUE_CR_SLC_IDLE_MASKFULL,
- ROGUE_CR_SLC_IDLE_MASKFULL, POLL_TIMEOUT_USEC);
- if (err)
- return err;
+ if (!layout_mars) {
+ /* Wait for SLC to signal IDLE. */
+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SLC_IDLE,
+ ROGUE_CR_SLC_IDLE_MASKFULL,
+ ROGUE_CR_SLC_IDLE_MASKFULL, POLL_TIMEOUT_USEC);
+ if (err)
+ return err;
- /*
- * Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper.
- * For cores with the LAYOUT_MARS feature, SIDEKICK would have been powered
- * down by the FW.
- */
- err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_mask,
- sidekick_idle_mask, POLL_TIMEOUT_USEC);
- if (err)
- return err;
+ /* Wait for Sidekick/Jones to signal IDLE except for the Garten Wrapper. */
+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE, sidekick_idle_mask,
+ sidekick_idle_mask, POLL_TIMEOUT_USEC);
+ if (err)
+ return err;
+ }
- if (pvr_dev->fw_dev.processor_type == PVR_FW_PROCESSOR_TYPE_META) {
+ if (meta_fw) {
err = pvr_meta_cr_read32(pvr_dev, META_CR_TxVECINT_BHALT, &reg_value);
if (err)
return err;
@@ -304,11 +316,28 @@ pvr_fw_stop(struct pvr_device *pvr_dev)
skip_garten_idle = true;
}
- if (!skip_garten_idle) {
- err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE,
- ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN,
- ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN,
+ if (meta_fw || !layout_mars) {
+ if (!skip_garten_idle) {
+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_SIDEKICK_IDLE,
+ ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN,
+ ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN,
+ POLL_TIMEOUT_USEC);
+ if (err)
+ return err;
+ }
+ } else {
+ /*
+ * As FW core has been moved from SIDEKICK to the new MARS domain, checking
+ * idle bits for CPU & System Arbiter excluding SOCIF which will never be
+ * idle if Host polling on this register
+ */
+ err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_MARS_IDLE,
+ ROGUE_CR_MARS_IDLE_CPU_EN |
+ ROGUE_CR_MARS_IDLE_MH_SYSARB0_EN,
+ ROGUE_CR_MARS_IDLE_CPU_EN |
+ ROGUE_CR_MARS_IDLE_MH_SYSARB0_EN,
POLL_TIMEOUT_USEC);
+
if (err)
return err;
}
--
2.53.0

145
SPECS/linux/0010-UPSTREAM-riscv-dts-spacemit-Define-the-P1-PMIC-regul.patch
View File

@@ -1,145 +0,0 @@
From 95ac92a72da3beee4583a20ba8126bd4c46b7d74 Mon Sep 17 00:00:00 2001
From: Javier Martinez Canillas <javierm@redhat.com>
Date: Sat, 6 Dec 2025 14:44:55 +0100
Subject: [PATCH 010/197] UPSTREAM: riscv: dts: spacemit: Define the P1 PMIC
regulators for Milk-V Jupiter
Define the SpacemiT P1 PMIC voltage regulators and their constraints.
The power management hardware design on the Milk-V Jupiter is identical to
the Banana Pi BPI-F3, so the DT Nodes were taken from k1-bananapi-f3.dts.
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20251206134532.1741648-4-javierm@redhat.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
(cherry picked from commit 7d307daa12b15a97269f577d5dcf50518758b568)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../boot/dts/spacemit/k1-milkv-jupiter.dts | 110 ++++++++++++++++++
1 file changed, 110 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts
index 5babed4d7094..800a112d5d70 100644
--- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts
@@ -95,6 +95,116 @@ &i2c8 {
pinctrl-0 = <&i2c8_cfg>;
pinctrl-names = "default";
status = "okay";
+
+ pmic@41 {
+ compatible = "spacemit,p1";
+ reg = <0x41>;
+ interrupts = <64>;
+ vin-supply = <&reg_vcc_4v>;
+
+ regulators {
+ buck1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck3_1v8: buck3 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck4 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck5 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck6 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ aldo1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ };
+
+ aldo2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ aldo3 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ aldo4 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ dldo1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ };
+
+ dldo2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ dldo3 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ dldo4 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-always-on;
+ };
+
+ dldo5 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ dldo6 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-always-on;
+ };
+
+ dldo7 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+ };
+ };
};
&uart0 {
--
2.53.0

47
SPECS/linux/0011-UPSTREAM-drm-imagination-Skip-2nd-thread-DM-associat.patch Normal file
View File

@@ -0,0 +1,47 @@
From 2c7e3f05c596f50a712015318f19577d1cbff735 Mon Sep 17 00:00:00 2001
From: Brajesh Gupta <brajesh.gupta@imgtec.com>
Date: Fri, 13 Mar 2026 06:38:25 +0000
Subject: [PATCH 011/189] UPSTREAM: drm/imagination: Skip 2nd thread DM
association for non META Firmware
Only a META firmware can have two threads.
Signed-off-by: Brajesh Gupta <brajesh.gupta@imgtec.com>
Reviewed-by: Matt Coster <matt.coster@imgtec.com>
Link: https://patch.msgid.link/20260313-b4-staging-layout_mars_base-v2-2-9e3c251d278e@imgtec.com
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
(cherry picked from commit 62a6f98cda4ec75107e96571346349a649fc63d1)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/gpu/drm/imagination/pvr_fw_startstop.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/imagination/pvr_fw_startstop.c b/drivers/gpu/drm/imagination/pvr_fw_startstop.c
index 6ae0489f7e2e..e24ed6fc4362 100644
--- a/drivers/gpu/drm/imagination/pvr_fw_startstop.c
+++ b/drivers/gpu/drm/imagination/pvr_fw_startstop.c
@@ -243,12 +243,15 @@ pvr_fw_stop(struct pvr_device *pvr_dev)
pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC,
ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_MASKFULL &
ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK);
- pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC,
- ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL &
- ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK);
- pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC,
- ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL &
- ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK);
+
+ if (meta_fw) {
+ pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC,
+ ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL &
+ ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK);
+ pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC,
+ ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL &
+ ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK);
+ }
/* Extra Idle checks. */
err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_BIF_STATUS_MMU, 0,
--
2.53.0

47
SPECS/linux/0011-UPSTREAM-pwm-th1520-Replace-kernel-c_str-with-C-Stri.patch
View File

@@ -1,47 +0,0 @@
From d50a49f9a081070f2eff66f4a4f992e8fd983a3d Mon Sep 17 00:00:00 2001
From: Tamir Duberstein <tamird@gmail.com>
Date: Mon, 22 Dec 2025 13:24:46 +0100
Subject: [PATCH 011/197] UPSTREAM: pwm: th1520: Replace `kernel::c_str!` with
C-Strings
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
C-String literals were added in Rust 1.77. Replace instances of
`kernel::c_str!` with C-String literals where possible.
Signed-off-by: Tamir Duberstein <tamird@gmail.com>
Reviewed-by: Michal Wilczynski <m.wilczynski@samsung.com>
Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Link: https://patch.msgid.link/20251222-cstr-pwm-v1-1-e8916d976f8d@gmail.com
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
(cherry picked from commit 269febe7747904d717d916ed1ee586aebce95d54)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/pwm/pwm_th1520.rs | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/pwm/pwm_th1520.rs b/drivers/pwm/pwm_th1520.rs
index e3b7e77356fc..8ae8f852ec02 100644
--- a/drivers/pwm/pwm_th1520.rs
+++ b/drivers/pwm/pwm_th1520.rs
@@ -22,7 +22,6 @@
use core::ops::Deref;
use kernel::{
- c_str,
clk::Clk,
device::{Bound, Core, Device},
devres,
@@ -327,7 +326,7 @@ fn drop(self: Pin<&mut Self>) {
OF_TABLE,
MODULE_OF_TABLE,
<Th1520PwmPlatformDriver as platform::Driver>::IdInfo,
- [(of::DeviceId::new(c_str!("thead,th1520-pwm")), ())]
+ [(of::DeviceId::new(c"thead,th1520-pwm"), ())]
);
impl platform::Driver for Th1520PwmPlatformDriver {
--
2.53.0

53
SPECS/linux/0012-UPSTREAM-drm-imagination-Add-missing-rogue-context-r.patch Normal file
View File

@@ -0,0 +1,53 @@
From 20f1468fdda61c059c28a62158efa377b7196e64 Mon Sep 17 00:00:00 2001
From: Alexandru Dadu <alexandru.dadu@imgtec.com>
Date: Mon, 23 Mar 2026 20:31:28 +0200
Subject: [PATCH 012/189] UPSTREAM: drm/imagination: Add missing rogue context
reset reasons
Update the context reset reason enum with the missing reset reasons in
the 6-11 value gap:
- CDM Mission/safety checksum mismatch;
- TRP checksum mismatch;
- GPU ECC error (corrected, OK);
- GPU ECC error (uncorrected, HWR);
- FW ECC error (corrected, OK);
- FW ECC error (uncorrected, ERR);
Co-developed-by: Sarah Walker <sarah.walker@imgtec.com>
Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com>
Reviewed-by: Matt Coster <matt.coster@imgtec.com>
Link: https://patch.msgid.link/20260323-b4-firmware-context-reset-notification-handling-v3-1-1a66049a9a65@imgtec.com
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
(cherry picked from commit da173557a2b090d7d8c155283ba489a287983ced)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h
index 6c09c15bf9bd..f622553cdc11 100644
--- a/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h
+++ b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h
@@ -236,6 +236,18 @@ enum rogue_context_reset_reason {
ROGUE_CONTEXT_RESET_REASON_INNOCENT_OVERRUNING = 4,
/* Forced reset to ensure scheduling requirements */
ROGUE_CONTEXT_RESET_REASON_HARD_CONTEXT_SWITCH = 5,
+ /* CDM Mission/safety checksum mismatch */
+ ROGUE_CONTEXT_RESET_REASON_WGP_CHECKSUM = 6,
+ /* TRP checksum mismatch */
+ ROGUE_CONTEXT_RESET_REASON_TRP_CHECKSUM = 7,
+ /* GPU ECC error (corrected, OK) */
+ ROGUE_CONTEXT_RESET_REASON_GPU_ECC_OK = 8,
+ /* GPU ECC error (uncorrected, HWR) */
+ ROGUE_CONTEXT_RESET_REASON_GPU_ECC_HWR = 9,
+ /* FW ECC error (corrected, OK) */
+ ROGUE_CONTEXT_RESET_REASON_FW_ECC_OK = 10,
+ /* FW ECC error (uncorrected, ERR) */
+ ROGUE_CONTEXT_RESET_REASON_FW_ECC_ERR = 11,
/* FW Safety watchdog triggered */
ROGUE_CONTEXT_RESET_REASON_FW_WATCHDOG = 12,
/* FW page fault (no HWR) */
--
2.53.0

152
SPECS/linux/0012-UPSTREAM-dt-bindings-phy-spacemit-Add-SpacemiT-PCIe-.patch
View File

@@ -1,152 +0,0 @@
From 1b2a537ac1a76c0499b051c1b1770e8e5ef6d9a2 Mon Sep 17 00:00:00 2001
From: Alex Elder <elder@riscstar.com>
Date: Thu, 18 Dec 2025 09:12:27 -0600
Subject: [PATCH 012/197] UPSTREAM: dt-bindings: phy: spacemit: Add SpacemiT
PCIe/combo PHY
Add the Device Tree binding for the PCIe/USB 3.0 combo PHY found in
the SpacemiT K1 SoC. This is one of three PCIe PHYs, and is unusual
in that only the combo PHY can perform a calibration step needed to
determine settings used by the other two PCIe PHYs.
Calibration must be done with the combo PHY in PCIe mode, and to allow
this to occur independent of the eventual use for the PHY (PCIe or USB)
some PCIe-related properties must be supplied: clocks; resets; and a
syscon phandle.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Alex Elder <elder@riscstar.com>
Link: https://lore.kernel.org/all/ba532f8d-a452-40e5-af46-b58b89f70a92@linaro.org/ [1]
Tested-by: Yixun Lan <dlan@gentoo.org>
Link: https://patch.msgid.link/20251218151235.454997-2-elder@riscstar.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
(cherry picked from commit f6194de7df023ecfd5156caf8e2762487be07ef7)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../bindings/phy/spacemit,k1-combo-phy.yaml | 114 ++++++++++++++++++
1 file changed, 114 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml
new file mode 100644
index 000000000000..b59476cd78b5
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/spacemit,k1-combo-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT K1 PCIe/USB3 Combo PHY
+
+maintainers:
+ - Alex Elder <elder@riscstar.com>
+
+description: >
+ Of the three PHYs on the SpacemiT K1 SoC capable of being used for
+ PCIe, one is a combo PHY that can also be configured for use by a
+ USB 3 controller. Using PCIe or USB 3 is a board design decision.
+
+ The combo PHY is also the only PCIe PHY that is able to determine
+ PCIe calibration values to use, and this must be determined before
+ the other two PCIe PHYs can be used. This calibration must be
+ performed with the combo PHY in PCIe mode, and is this is done
+ when the combo PHY is probed.
+
+ The combo PHY uses an external oscillator as a reference clock.
+ During normal operation, the PCIe or USB port driver is responsible
+ for ensuring all other clocks needed by a PHY are enabled, and all
+ resets affecting the PHY are deasserted. However, for the combo
+ PHY to perform calibration independent of whether it's later used
+ for PCIe or USB, all PCIe mode clocks and resets must be defined.
+
+properties:
+ compatible:
+ const: spacemit,k1-combo-phy
+
+ reg:
+ items:
+ - description: PHY control registers
+
+ clocks:
+ items:
+ - description: External oscillator used by the PHY PLL
+ - description: DWC PCIe Data Bus Interface (DBI) clock
+ - description: DWC PCIe application AXI-bus Master interface clock
+ - description: DWC PCIe application AXI-bus slave interface clock
+
+ clock-names:
+ items:
+ - const: refclk
+ - const: dbi
+ - const: mstr
+ - const: slv
+
+ resets:
+ items:
+ - description: PHY reset; remains deasserted after initialization
+ - description: DWC PCIe Data Bus Interface (DBI) reset
+ - description: DWC PCIe application AXI-bus Master interface reset
+ - description: DWC PCIe application AXI-bus slave interface reset
+
+ reset-names:
+ items:
+ - const: phy
+ - const: dbi
+ - const: mstr
+ - const: slv
+
+ spacemit,apmu:
+ description:
+ A phandle that refers to the APMU system controller, whose
+ regmap is used in setting the mode
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ "#phy-cells":
+ const: 1
+ description:
+ The argument value (PHY_TYPE_PCIE or PHY_TYPE_USB3) determines
+ whether the PHY operates in PCIe or USB3 mode.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - spacemit,apmu
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/spacemit,k1-syscon.h>
+ phy@c0b10000 {
+ compatible = "spacemit,k1-combo-phy";
+ reg = <0xc0b10000 0x1000>;
+ clocks = <&vctcxo_24m>,
+ <&syscon_apmu CLK_PCIE0_DBI>,
+ <&syscon_apmu CLK_PCIE0_MASTER>,
+ <&syscon_apmu CLK_PCIE0_SLAVE>;
+ clock-names = "refclk",
+ "dbi",
+ "mstr",
+ "slv";
+ resets = <&syscon_apmu RESET_PCIE0_GLOBAL>,
+ <&syscon_apmu RESET_PCIE0_DBI>,
+ <&syscon_apmu RESET_PCIE0_MASTER>,
+ <&syscon_apmu RESET_PCIE0_SLAVE>;
+ reset-names = "phy",
+ "dbi",
+ "mstr",
+ "slv";
+ spacemit,apmu = <&syscon_apmu>;
+ #phy-cells = <1>;
+ };
--
2.53.0

61
SPECS/linux/0013-UPSTREAM-drm-imagination-Switch-reset_reason-fields-.patch Normal file
View File

@@ -0,0 +1,61 @@
From 693dcd6c8f6c34dabf4588377969b088b7d4a9ee Mon Sep 17 00:00:00 2001
From: Alexandru Dadu <alexandru.dadu@imgtec.com>
Date: Mon, 23 Mar 2026 20:31:29 +0200
Subject: [PATCH 013/189] UPSTREAM: drm/imagination: Switch reset_reason fields
from enum to u32
Update the reset_reason fwif structure fields from enum to u32 to remove
any ambiguity from the interface (enum is not a fixed size thus is unfit
for the purpose of the data type).
Fixes: a26f067feac1f ("drm/imagination: Add FWIF headers")
Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com>
Reviewed-by: Matt Coster <matt.coster@imgtec.com>
Link: https://patch.msgid.link/20260323-b4-firmware-context-reset-notification-handling-v3-2-1a66049a9a65@imgtec.com
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
(cherry picked from commit d2f83a6cd598bf413f1acf34153bd1d71023fbab)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/gpu/drm/imagination/pvr_rogue_fwif.h | 8 ++++++--
drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h | 6 +++++-
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/imagination/pvr_rogue_fwif.h b/drivers/gpu/drm/imagination/pvr_rogue_fwif.h
index 172886be4c82..5d590c4c2566 100644
--- a/drivers/gpu/drm/imagination/pvr_rogue_fwif.h
+++ b/drivers/gpu/drm/imagination/pvr_rogue_fwif.h
@@ -1347,8 +1347,12 @@ struct rogue_fwif_fwccb_cmd_freelists_reconstruction_data {
struct rogue_fwif_fwccb_cmd_context_reset_data {
/* Context affected by the reset */
u32 server_common_context_id;
- /* Reason for reset */
- enum rogue_context_reset_reason reset_reason;
+ /*
+ * Reason for reset
+ * The valid values for reset_reason are the ones from
+ * enum rogue_context_reset_reason
+ */
+ u32 reset_reason;
/* Data Master affected by the reset */
u32 dm;
/* Job ref running at the time of reset */
diff --git a/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h
index f622553cdc11..869d904e3649 100644
--- a/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h
+++ b/drivers/gpu/drm/imagination/pvr_rogue_fwif_shared.h
@@ -261,7 +261,11 @@ enum rogue_context_reset_reason {
};
struct rogue_context_reset_reason_data {
- enum rogue_context_reset_reason reset_reason;
+ /*
+ * The valid values for reset_reason are the ones from
+ * enum rogue_context_reset_reason
+ */
+ u32 reset_reason;
u32 reset_ext_job_ref;
};
--
2.53.0

104
SPECS/linux/0013-UPSTREAM-dt-bindings-phy-spacemit-Introduce-PCIe-PHY.patch
View File

@@ -1,104 +0,0 @@
From 44ead6fb85c2d7cba87bb45b8388a76384e3ae96 Mon Sep 17 00:00:00 2001
From: Alex Elder <elder@riscstar.com>
Date: Thu, 18 Dec 2025 09:12:28 -0600
Subject: [PATCH 013/197] UPSTREAM: dt-bindings: phy: spacemit: Introduce PCIe
PHY
Add the Device Tree binding for two PCIe PHYs present on the SpacemiT
K1 SoC. These PHYs are dependent on a separate combo PHY, which
determines at probe time the calibration values used by the PCIe-only
PHYs.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Alex Elder <elder@riscstar.com>
Link: https://lore.kernel.org/all/ba532f8d-a452-40e5-af46-b58b89f70a92@linaro.org/ [1]
Tested-by: Yixun Lan <dlan@gentoo.org>
Link: https://patch.msgid.link/20251218151235.454997-3-elder@riscstar.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
(cherry picked from commit 326a278a3682d390269699f68e597b5ef5a57d26)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../bindings/phy/spacemit,k1-pcie-phy.yaml | 71 +++++++++++++++++++
1 file changed, 71 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml
new file mode 100644
index 000000000000..019b28349be7
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/spacemit,k1-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT K1 PCIe PHY
+
+maintainers:
+ - Alex Elder <elder@riscstar.com>
+
+description: >
+ Two PHYs on the SpacemiT K1 SoC used for only for PCIe. These
+ PHYs must be configured using calibration values that are
+ determined by a third "combo PHY". The combo PHY determines
+ these calibration values during probe so they can be used for
+ the two PCIe-only PHYs.
+
+ The PHY uses an external oscillator as a reference clock. During
+ normal operation, the PCIe host driver is responsible for ensuring
+ all other clocks needed by a PHY are enabled, and all resets
+ affecting the PHY are deasserted.
+
+properties:
+ compatible:
+ const: spacemit,k1-pcie-phy
+
+ reg:
+ items:
+ - description: PHY control registers
+
+ clocks:
+ items:
+ - description: External oscillator used by the PHY PLL
+
+ clock-names:
+ const: refclk
+
+ resets:
+ items:
+ - description: PHY reset; remains deasserted after initialization
+
+ reset-names:
+ const: phy
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/spacemit,k1-syscon.h>
+ phy@c0c10000 {
+ compatible = "spacemit,k1-pcie-phy";
+ reg = <0xc0c10000 0x1000>;
+ clocks = <&vctcxo_24m>;
+ clock-names = "refclk";
+ resets = <&syscon_apmu RESET_PCIE1_GLOBAL>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ };
--
2.53.0

208
SPECS/linux/0014-UPSTREAM-drm-imagination-Implement-handling-of-conte.patch Normal file
View File

@@ -0,0 +1,208 @@
From 8b9de02fa0473bfa648ad3016b635f501e42474a Mon Sep 17 00:00:00 2001
From: Alexandru Dadu <alexandru.dadu@imgtec.com>
Date: Mon, 23 Mar 2026 20:31:30 +0200
Subject: [PATCH 014/189] UPSTREAM: drm/imagination: Implement handling of
context reset notification
The firmware will send the context reset notification message as
part of handling hardware recovery (HWR) events deecoding the message
and printing via drm_info(). This eliminates the "Unknown FWCCB command"
message that was previously printed.
Co-developed-by: Sarah Walker <sarah.walker@imgtec.com>
Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com>
Reviewed-by: Matt Coster <matt.coster@imgtec.com>
Link: https://patch.msgid.link/20260323-b4-firmware-context-reset-notification-handling-v3-3-1a66049a9a65@imgtec.com
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
(cherry picked from commit d994acc526c70d40ec9029cfe03d08ee411083c5)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/gpu/drm/imagination/Makefile | 1 +
drivers/gpu/drm/imagination/pvr_ccb.c | 5 ++
drivers/gpu/drm/imagination/pvr_dump.c | 113 +++++++++++++++++++++++++
drivers/gpu/drm/imagination/pvr_dump.h | 17 ++++
4 files changed, 136 insertions(+)
create mode 100644 drivers/gpu/drm/imagination/pvr_dump.c
create mode 100644 drivers/gpu/drm/imagination/pvr_dump.h
diff --git a/drivers/gpu/drm/imagination/Makefile b/drivers/gpu/drm/imagination/Makefile
index f5072f06b4c4..1222a14262e4 100644
--- a/drivers/gpu/drm/imagination/Makefile
+++ b/drivers/gpu/drm/imagination/Makefile
@@ -8,6 +8,7 @@ powervr-y := \
pvr_device.o \
pvr_device_info.o \
pvr_drv.o \
+ pvr_dump.o \
pvr_free_list.o \
pvr_fw.o \
pvr_fw_meta.o \
diff --git a/drivers/gpu/drm/imagination/pvr_ccb.c b/drivers/gpu/drm/imagination/pvr_ccb.c
index f89db5e3baa2..4accf18e2341 100644
--- a/drivers/gpu/drm/imagination/pvr_ccb.c
+++ b/drivers/gpu/drm/imagination/pvr_ccb.c
@@ -4,6 +4,7 @@
#include "pvr_ccb.h"
#include "pvr_device.h"
#include "pvr_drv.h"
+#include "pvr_dump.h"
#include "pvr_free_list.h"
#include "pvr_fw.h"
#include "pvr_gem.h"
@@ -165,6 +166,10 @@ process_fwccb_command(struct pvr_device *pvr_dev, struct rogue_fwif_fwccb_cmd *c
* suppress the "unknown" warning when receiving this command.
*/
break;
+ case ROGUE_FWIF_FWCCB_CMD_CONTEXT_RESET_NOTIFICATION:
+ pvr_dump_context_reset_notification(pvr_dev,
+ &cmd->cmd_data.cmd_context_reset_notification);
+ break;
default:
drm_info(drm_dev, "Received unknown FWCCB command (type=%d)\n",
diff --git a/drivers/gpu/drm/imagination/pvr_dump.c b/drivers/gpu/drm/imagination/pvr_dump.c
new file mode 100644
index 000000000000..52e95fce2817
--- /dev/null
+++ b/drivers/gpu/drm/imagination/pvr_dump.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/* Copyright (c) 2026 Imagination Technologies Ltd. */
+
+#include "pvr_device.h"
+#include "pvr_dump.h"
+#include "pvr_rogue_fwif.h"
+
+#include <drm/drm_print.h>
+#include <linux/types.h>
+
+static const char *
+get_reset_reason_desc(enum rogue_context_reset_reason reason)
+{
+ switch (reason) {
+ case ROGUE_CONTEXT_RESET_REASON_NONE:
+ return "None";
+ case ROGUE_CONTEXT_RESET_REASON_GUILTY_LOCKUP:
+ return "Guilty lockup";
+ case ROGUE_CONTEXT_RESET_REASON_INNOCENT_LOCKUP:
+ return "Innocent lockup";
+ case ROGUE_CONTEXT_RESET_REASON_GUILTY_OVERRUNING:
+ return "Guilty overrunning";
+ case ROGUE_CONTEXT_RESET_REASON_INNOCENT_OVERRUNING:
+ return "Innocent overrunning";
+ case ROGUE_CONTEXT_RESET_REASON_HARD_CONTEXT_SWITCH:
+ return "Hard context switch";
+ case ROGUE_CONTEXT_RESET_REASON_WGP_CHECKSUM:
+ return "CDM Mission/safety checksum mismatch";
+ case ROGUE_CONTEXT_RESET_REASON_TRP_CHECKSUM:
+ return "TRP checksum mismatch";
+ case ROGUE_CONTEXT_RESET_REASON_GPU_ECC_OK:
+ return "GPU ECC error (corrected, OK)";
+ case ROGUE_CONTEXT_RESET_REASON_GPU_ECC_HWR:
+ return "GPU ECC error (uncorrected, HWR)";
+ case ROGUE_CONTEXT_RESET_REASON_FW_ECC_OK:
+ return "Firmware ECC error (corrected, OK)";
+ case ROGUE_CONTEXT_RESET_REASON_FW_ECC_ERR:
+ return "Firmware ECC error (uncorrected, ERR)";
+ case ROGUE_CONTEXT_RESET_REASON_FW_WATCHDOG:
+ return "Firmware watchdog";
+ case ROGUE_CONTEXT_RESET_REASON_FW_PAGEFAULT:
+ return "Firmware pagefault";
+ case ROGUE_CONTEXT_RESET_REASON_FW_EXEC_ERR:
+ return "Firmware execution error";
+ case ROGUE_CONTEXT_RESET_REASON_HOST_WDG_FW_ERR:
+ return "Host watchdog";
+ case ROGUE_CONTEXT_GEOM_OOM_DISABLED:
+ return "Geometry OOM disabled";
+
+ default:
+ return "Unknown";
+ }
+}
+
+static const char *
+get_dm_name(u32 dm)
+{
+ switch (dm) {
+ case PVR_FWIF_DM_GP:
+ return "General purpose";
+ /* PVR_FWIF_DM_TDM has the same index, but is discriminated by a device feature */
+ case PVR_FWIF_DM_2D:
+ return "2D or TDM";
+ case PVR_FWIF_DM_GEOM:
+ return "Geometry";
+ case PVR_FWIF_DM_FRAG:
+ return "Fragment";
+ case PVR_FWIF_DM_CDM:
+ return "Compute";
+ case PVR_FWIF_DM_RAY:
+ return "Raytracing";
+ case PVR_FWIF_DM_GEOM2:
+ return "Geometry 2";
+ case PVR_FWIF_DM_GEOM3:
+ return "Geometry 3";
+ case PVR_FWIF_DM_GEOM4:
+ return "Geometry 4";
+
+ default:
+ return "Unknown";
+ }
+}
+
+/**
+ * pvr_dump_context_reset_notification() - Handle context reset notification from FW
+ * @pvr_dev: Device pointer.
+ * @data: Data provided by FW.
+ *
+ * This will decode the data structure provided by FW and print the results via drm_info().
+ */
+void
+pvr_dump_context_reset_notification(struct pvr_device *pvr_dev,
+ struct rogue_fwif_fwccb_cmd_context_reset_data *data)
+{
+ struct drm_device *drm_dev = from_pvr_device(pvr_dev);
+
+ if (data->flags & ROGUE_FWIF_FWCCB_CMD_CONTEXT_RESET_FLAG_ALL_CTXS) {
+ drm_info(drm_dev, "Received context reset notification for all contexts\n");
+ } else {
+ drm_info(drm_dev, "Received context reset notification on context %u\n",
+ data->server_common_context_id);
+ }
+
+ drm_info(drm_dev, " Reset reason=%u (%s)\n", data->reset_reason,
+ get_reset_reason_desc((enum rogue_context_reset_reason)data->reset_reason));
+ drm_info(drm_dev, " Data Master=%u (%s)\n", data->dm, get_dm_name(data->dm));
+ drm_info(drm_dev, " Job ref=%u\n", data->reset_job_ref);
+
+ if (data->flags & ROGUE_FWIF_FWCCB_CMD_CONTEXT_RESET_FLAG_PF) {
+ drm_info(drm_dev, " Page fault occurred, fault address=%llx\n",
+ data->fault_address);
+ }
+}
diff --git a/drivers/gpu/drm/imagination/pvr_dump.h b/drivers/gpu/drm/imagination/pvr_dump.h
new file mode 100644
index 000000000000..3c0728c05596
--- /dev/null
+++ b/drivers/gpu/drm/imagination/pvr_dump.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/* Copyright (c) 2026 Imagination Technologies Ltd. */
+
+#ifndef PVR_DUMP_H
+#define PVR_DUMP_H
+
+/* Forward declaration from pvr_device.h. */
+struct pvr_device;
+
+/* Forward declaration from pvr_rogue_fwif.h. */
+struct rogue_fwif_fwccb_cmd_context_reset_data;
+
+void
+pvr_dump_context_reset_notification(struct pvr_device *pvr_dev,
+ struct rogue_fwif_fwccb_cmd_context_reset_data *data);
+
+#endif /* PVR_DUMP_H */
--
2.53.0

758
SPECS/linux/0014-UPSTREAM-phy-spacemit-Introduce-PCIe-combo-PHY.patch
View File

@@ -1,758 +0,0 @@
From ee34667e0e4b206e72b7bdd80fb7737e5ae56096 Mon Sep 17 00:00:00 2001
From: Alex Elder <elder@riscstar.com>
Date: Thu, 18 Dec 2025 09:12:29 -0600
Subject: [PATCH 014/197] UPSTREAM: phy: spacemit: Introduce PCIe/combo PHY
Introduce a driver that supports three PHYs found on the SpacemiT
K1 SoC. The first PHY is a combo PHY that can be configured for
use for either USB 3 or PCIe. The other two PHYs support PCIe
only.
All three PHYs must be programmed with an 8 bit receiver termination
value, which must be determined dynamically. Only the combo PHY is
able to determine this value. The combo PHY performs a special
calibration step at probe time to discover this, and that value is
used to program each PHY that operates in PCIe mode. The combo
PHY must therefore be probed before either of the PCIe-only PHYs
will be used.
Each PHY has an internal PLL driven from an external oscillator.
This PLL started when the PHY is first initialized, and stays
on thereafter.
During normal operation, the USB or PCIe driver using the PHY must
ensure (other) clocks and resets are set up properly.
However PCIe mode clocks are enabled and resets are de-asserted
temporarily by this driver to perform the calibration step on the
combo PHY.
Tested-by: Junzhong Pan <panjunzhong@linux.spacemit.com>
Signed-off-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/all/ba532f8d-a452-40e5-af46-b58b89f70a92@linaro.org/ [1]
Tested-by: Yixun Lan <dlan@gentoo.org>
Link: https://patch.msgid.link/20251218151235.454997-4-elder@riscstar.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
(cherry picked from commit 57e920b92724dd568526990c04e79ed54241c5fc)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/phy/Kconfig | 11 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-spacemit-k1-pcie.c | 670 +++++++++++++++++++++++++++++
3 files changed, 682 insertions(+)
create mode 100644 drivers/phy/phy-spacemit-k1-pcie.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 678dd0452f0a..1984c2e56122 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -101,6 +101,17 @@ config PHY_NXP_PTN3222
schemes. It supports all three USB 2.0 data rates: Low Speed, Full
Speed and High Speed.
+config PHY_SPACEMIT_K1_PCIE
+ tristate "PCIe and combo PHY driver for the SpacemiT K1 SoC"
+ depends on ARCH_SPACEMIT || COMPILE_TEST
+ depends on HAS_IOMEM
+ depends on OF
+ select GENERIC_PHY
+ default ARCH_SPACEMIT
+ help
+ Enable support for the PCIe and USB 3 combo PHY and two
+ PCIe-only PHYs used in the SpacemiT K1 SoC.
+
source "drivers/phy/allwinner/Kconfig"
source "drivers/phy/amlogic/Kconfig"
source "drivers/phy/broadcom/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index bfb27fb5a494..a206133a3515 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_PHY_SNPS_EUSB2) += phy-snps-eusb2.o
obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o
obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o
obj-$(CONFIG_PHY_NXP_PTN3222) += phy-nxp-ptn3222.o
+obj-$(CONFIG_PHY_SPACEMIT_K1_PCIE) += phy-spacemit-k1-pcie.o
obj-y += allwinner/ \
amlogic/ \
broadcom/ \
diff --git a/drivers/phy/phy-spacemit-k1-pcie.c b/drivers/phy/phy-spacemit-k1-pcie.c
new file mode 100644
index 000000000000..75477bea7f70
--- /dev/null
+++ b/drivers/phy/phy-spacemit-k1-pcie.c
@@ -0,0 +1,670 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SpacemiT K1 PCIe and PCIe/USB 3 combo PHY driver
+ *
+ * Copyright (C) 2025 by RISCstar Solutions Corporation. All rights reserved.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#include <dt-bindings/phy/phy.h>
+
+/*
+ * Three PCIe ports are supported in the SpacemiT K1 SoC, and this driver
+ * supports their PHYs.
+ *
+ * The PHY for PCIe port A is different from the PHYs for ports B and C:
+ * - It has one lane, while ports B and C have two
+ * - It is a combo PHY can be used for PCIe or USB 3
+ * - It can automatically calibrate PCIe TX and RX termination settings
+ *
+ * The PHY functionality for PCIe ports B and C is identical:
+ * - They have two PCIe lanes (but can be restricted to 1 via device tree)
+ * - They are used for PCIe only
+ * - They are configured using TX and RX values computed for port A
+ *
+ * A given board is designed to use the combo PHY for either PCIe or USB 3.
+ * Whether the combo PHY is configured for PCIe or USB 3 is specified in
+ * device tree using a phandle plus an argument. The argument indicates
+ * the type (either PHY_TYPE_PCIE or PHY_TYPE_USB3).
+ *
+ * Each PHY has a reset that it gets and deasserts during initialization.
+ * Each depends also on other clocks and resets provided by the controller
+ * hardware (PCIe or USB) it is associated with. The controller drivers
+ * are required to enable any clocks and de-assert any resets that affect
+ * PHY operation. In addition each PHY implements an internal PLL, driven
+ * by an external (24 MHz) oscillator.
+ *
+ * PCIe PHYs must be programmed with RX and TX calibration values. The
+ * combo PHY is the only one that can determine these values. They are
+ * determined by temporarily enabling the combo PHY in PCIe mode at probe
+ * time (if necessary). This calibration only needs to be done once, and
+ * when it has completed the TX and RX values are saved.
+ *
+ * To allow the combo PHY to be enabled for calibration, the resets and
+ * clocks it uses in PCIe mode must be supplied.
+ */
+
+struct k1_pcie_phy {
+ struct device *dev; /* PHY provider device */
+ struct phy *phy;
+ void __iomem *regs;
+ u32 pcie_lanes; /* Max (1 or 2) unless limited by DT */
+ struct clk *pll;
+ struct clk_hw pll_hw; /* Private PLL clock */
+
+ /* The remaining fields are only used for the combo PHY */
+ u32 type; /* PHY_TYPE_PCIE or PHY_TYPE_USB3 */
+ struct regmap *pmu; /* MMIO regmap (no errors) */
+};
+
+#define CALIBRATION_TIMEOUT 500000 /* For combo PHY (usec) */
+#define PLL_TIMEOUT 500000 /* For PHY PLL lock (usec) */
+#define POLL_DELAY 500 /* Time between polls (usec) */
+
+/* Selecting the combo PHY operating mode requires APMU regmap access */
+#define SYSCON_APMU "spacemit,apmu"
+
+/* PMU space, for selecting between PCIe and USB 3 mode (combo PHY only) */
+
+#define PMUA_USB_PHY_CTRL0 0x0110
+#define COMBO_PHY_SEL BIT(3) /* 0: PCIe; 1: USB 3 */
+
+#define PCIE_CLK_RES_CTRL 0x03cc
+#define PCIE_APP_HOLD_PHY_RST BIT(30)
+
+/* PHY register space */
+
+/* Offset between lane 0 and lane 1 registers when there are two */
+#define PHY_LANE_OFFSET 0x0400
+
+/* PHY PLL configuration */
+#define PCIE_PU_ADDR_CLK_CFG 0x0008
+#define PLL_READY BIT(0) /* read-only */
+#define CFG_INTERNAL_TIMER_ADJ GENMASK(10, 7)
+#define TIMER_ADJ_USB 0x2
+#define TIMER_ADJ_PCIE 0x6
+#define CFG_SW_PHY_INIT_DONE BIT(11) /* We set after PLL config */
+
+#define PCIE_RC_DONE_STATUS 0x0018
+#define CFG_FORCE_RCV_RETRY BIT(10) /* Used for PCIe */
+
+/* PCIe PHY lane calibration; assumes 24MHz input clock */
+#define PCIE_RC_CAL_REG2 0x0020
+#define RC_CAL_TOGGLE BIT(22)
+#define CLKSEL GENMASK(31, 29)
+#define CLKSEL_24M 0x3
+
+/* Additional PHY PLL configuration (USB 3 and PCIe) */
+#define PCIE_PU_PLL_1 0x0048
+#define REF_100_WSSC BIT(12) /* 1: input is 100MHz, SSC */
+#define FREF_SEL GENMASK(15, 13)
+#define FREF_24M 0x1
+#define SSC_DEP_SEL GENMASK(19, 16)
+#define SSC_DEP_NONE 0x0
+#define SSC_DEP_5000PPM 0xa
+
+/* PCIe PHY configuration */
+#define PCIE_PU_PLL_2 0x004c
+#define GEN_REF100 BIT(4) /* 1: generate 100MHz clk */
+
+#define PCIE_RX_REG1 0x0050
+#define EN_RTERM BIT(3)
+#define AFE_RTERM_REG GENMASK(11, 8)
+
+#define PCIE_RX_REG2 0x0054
+#define RX_RTERM_SEL BIT(5) /* 0: use AFE_RTERM_REG value */
+
+#define PCIE_LTSSM_DIS_ENTRY 0x005c
+#define CFG_REFCLK_MODE GENMASK(9, 8)
+#define RFCLK_MODE_DRIVER 0x1
+#define OVRD_REFCLK_MODE BIT(10) /* 1: use CFG_RFCLK_MODE */
+
+#define PCIE_TX_REG1 0x0064
+#define TX_RTERM_REG GENMASK(15, 12)
+#define TX_RTERM_SEL BIT(25) /* 1: use TX_RTERM_REG */
+
+/* Zeroed for the combo PHY operating in USB mode */
+#define USB3_TEST_CTRL 0x0068
+
+/* PHY calibration values, determined by the combo PHY at probe time */
+#define PCIE_RCAL_RESULT 0x0084 /* Port A PHY only */
+#define RTERM_VALUE_RX GENMASK(3, 0)
+#define RTERM_VALUE_TX GENMASK(7, 4)
+#define R_TUNE_DONE BIT(10)
+
+static u32 k1_phy_rterm = ~0; /* Invalid initial value */
+
+/* Save the RX and TX receiver termination values */
+static void k1_phy_rterm_set(u32 val)
+{
+ k1_phy_rterm = val & (RTERM_VALUE_RX | RTERM_VALUE_TX);
+}
+
+static bool k1_phy_rterm_valid(void)
+{
+ /* Valid if no bits outside those we care about are set */
+ return !(k1_phy_rterm & ~(RTERM_VALUE_RX | RTERM_VALUE_TX));
+}
+
+static u32 k1_phy_rterm_rx(void)
+{
+ return FIELD_GET(RTERM_VALUE_RX, k1_phy_rterm);
+}
+
+static u32 k1_phy_rterm_tx(void)
+{
+ return FIELD_GET(RTERM_VALUE_TX, k1_phy_rterm);
+}
+
+/* Only the combo PHY has a PMU pointer defined */
+static bool k1_phy_port_a(struct k1_pcie_phy *k1_phy)
+{
+ return !!k1_phy->pmu;
+}
+
+/* The PLL clocks are driven by the external oscillator */
+static const struct clk_parent_data k1_pcie_phy_data[] = {
+ { .fw_name = "refclk", },
+};
+
+static struct k1_pcie_phy *clk_hw_to_k1_phy(struct clk_hw *clk_hw)
+{
+ return container_of(clk_hw, struct k1_pcie_phy, pll_hw);
+}
+
+/* USB mode only works on the combo PHY, which has only one lane */
+static void k1_pcie_phy_pll_prepare_usb(struct k1_pcie_phy *k1_phy)
+{
+ void __iomem *regs = k1_phy->regs;
+ u32 val;
+
+ val = readl(regs + PCIE_PU_ADDR_CLK_CFG);
+ val &= ~CFG_INTERNAL_TIMER_ADJ;
+ val |= FIELD_PREP(CFG_INTERNAL_TIMER_ADJ, TIMER_ADJ_USB);
+ writel(val, regs + PCIE_PU_ADDR_CLK_CFG);
+
+ val = readl(regs + PCIE_PU_PLL_1);
+ val &= ~SSC_DEP_SEL;
+ val |= FIELD_PREP(SSC_DEP_SEL, SSC_DEP_5000PPM);
+ writel(val, regs + PCIE_PU_PLL_1);
+}
+
+/* Perform PCIe-specific register updates before starting the PLL clock */
+static void k1_pcie_phy_pll_prepare_pcie(struct k1_pcie_phy *k1_phy)
+{
+ void __iomem *regs = k1_phy->regs;
+ u32 val;
+ u32 i;
+
+ for (i = 0; i < k1_phy->pcie_lanes; i++) {
+ val = readl(regs + PCIE_PU_ADDR_CLK_CFG);
+ val &= ~CFG_INTERNAL_TIMER_ADJ;
+ val |= FIELD_PREP(CFG_INTERNAL_TIMER_ADJ, TIMER_ADJ_PCIE);
+ writel(val, regs + PCIE_PU_ADDR_CLK_CFG);
+
+ regs += PHY_LANE_OFFSET; /* Next lane */
+ }
+
+ regs = k1_phy->regs;
+ val = readl(regs + PCIE_RC_DONE_STATUS);
+ val |= CFG_FORCE_RCV_RETRY;
+ writel(val, regs + PCIE_RC_DONE_STATUS);
+
+ val = readl(regs + PCIE_PU_PLL_1);
+ val &= ~SSC_DEP_SEL;
+ val |= FIELD_PREP(SSC_DEP_SEL, SSC_DEP_NONE);
+ writel(val, regs + PCIE_PU_PLL_1);
+
+ val = readl(regs + PCIE_PU_PLL_2);
+ val |= GEN_REF100; /* Enable 100 MHz PLL output clock */
+ writel(val, regs + PCIE_PU_PLL_2);
+}
+
+static int k1_pcie_phy_pll_prepare(struct clk_hw *clk_hw)
+{
+ struct k1_pcie_phy *k1_phy = clk_hw_to_k1_phy(clk_hw);
+ void __iomem *regs = k1_phy->regs;
+ u32 val;
+ u32 i;
+
+ if (k1_phy_port_a(k1_phy) && k1_phy->type == PHY_TYPE_USB3)
+ k1_pcie_phy_pll_prepare_usb(k1_phy);
+ else
+ k1_pcie_phy_pll_prepare_pcie(k1_phy);
+
+ /*
+ * Disable 100 MHz input reference with spread-spectrum
+ * clocking and select the 24 MHz clock input frequency
+ */
+ val = readl(regs + PCIE_PU_PLL_1);
+ val &= ~REF_100_WSSC;
+ val &= ~FREF_SEL;
+ val |= FIELD_PREP(FREF_SEL, FREF_24M);
+ writel(val, regs + PCIE_PU_PLL_1);
+
+ /* Mark PLL configuration done on all lanes */
+ for (i = 0; i < k1_phy->pcie_lanes; i++) {
+ val = readl(regs + PCIE_PU_ADDR_CLK_CFG);
+ val |= CFG_SW_PHY_INIT_DONE;
+ writel(val, regs + PCIE_PU_ADDR_CLK_CFG);
+
+ regs += PHY_LANE_OFFSET; /* Next lane */
+ }
+
+ /*
+ * Wait for indication the PHY PLL is locked. Lanes for ports
+ * B and C share a PLL, so it's enough to sample just lane 0.
+ */
+ return readl_poll_timeout(k1_phy->regs + PCIE_PU_ADDR_CLK_CFG,
+ val, val & PLL_READY,
+ POLL_DELAY, PLL_TIMEOUT);
+}
+
+/* Prepare implies enable, and once enabled, it's always on */
+static const struct clk_ops k1_pcie_phy_pll_ops = {
+ .prepare = k1_pcie_phy_pll_prepare,
+};
+
+/* We represent the PHY PLL as a private clock */
+static int k1_pcie_phy_pll_setup(struct k1_pcie_phy *k1_phy)
+{
+ struct clk_hw *hw = &k1_phy->pll_hw;
+ struct device *dev = k1_phy->dev;
+ struct clk_init_data init = { };
+ char *name;
+ int ret;
+
+ name = kasprintf(GFP_KERNEL, "pcie%u_phy_pll", k1_phy->phy->id);
+ if (!name)
+ return -ENOMEM;
+
+ init.name = name;
+ init.ops = &k1_pcie_phy_pll_ops;
+ init.parent_data = k1_pcie_phy_data;
+ init.num_parents = ARRAY_SIZE(k1_pcie_phy_data);
+
+ hw->init = &init;
+
+ ret = devm_clk_hw_register(dev, hw);
+
+ kfree(name); /* __clk_register() duplicates the name we provide */
+
+ if (ret)
+ return ret;
+
+ k1_phy->pll = devm_clk_hw_get_clk(dev, hw, "pll");
+ if (IS_ERR(k1_phy->pll))
+ return PTR_ERR(k1_phy->pll);
+
+ return 0;
+}
+
+/* Select PCIe or USB 3 mode for the combo PHY. */
+static void k1_combo_phy_sel(struct k1_pcie_phy *k1_phy, bool usb)
+{
+ struct regmap *pmu = k1_phy->pmu;
+
+ /* Only change it if it's not already in the desired state */
+ if (!regmap_test_bits(pmu, PMUA_USB_PHY_CTRL0, COMBO_PHY_SEL) == usb)
+ regmap_assign_bits(pmu, PMUA_USB_PHY_CTRL0, COMBO_PHY_SEL, usb);
+}
+
+static void k1_pcie_phy_init_pcie(struct k1_pcie_phy *k1_phy)
+{
+ u32 rx_rterm = k1_phy_rterm_rx();
+ u32 tx_rterm = k1_phy_rterm_tx();
+ void __iomem *regs;
+ u32 val;
+ int i;
+
+ /* For the combo PHY, set PHY to PCIe mode */
+ if (k1_phy_port_a(k1_phy))
+ k1_combo_phy_sel(k1_phy, false);
+
+ regs = k1_phy->regs;
+ for (i = 0; i < k1_phy->pcie_lanes; i++) {
+ val = readl(regs + PCIE_RX_REG1);
+
+ /* Set RX analog front-end receiver termination value */
+ val &= ~AFE_RTERM_REG;
+ val |= FIELD_PREP(AFE_RTERM_REG, rx_rterm);
+
+ /* And enable refclock receiver termination */
+ val |= EN_RTERM;
+ writel(val, regs + PCIE_RX_REG1);
+
+ val = readl(regs + PCIE_RX_REG2);
+ /* Use PCIE_RX_REG1 AFE_RTERM_REG value */
+ val &= ~RX_RTERM_SEL;
+ writel(val, regs + PCIE_RX_REG2);
+
+ val = readl(regs + PCIE_TX_REG1);
+
+ /* Set TX driver termination value */
+ val &= ~TX_RTERM_REG;
+ val |= FIELD_PREP(TX_RTERM_REG, tx_rterm);
+
+ /* Use PCIE_TX_REG1 TX_RTERM_REG value */
+ val |= TX_RTERM_SEL;
+ writel(val, regs + PCIE_TX_REG1);
+
+ /* Set the input clock to 24 MHz, and clear RC_CAL_TOGGLE */
+ val = readl(regs + PCIE_RC_CAL_REG2);
+ val &= CLKSEL;
+ val |= FIELD_PREP(CLKSEL, CLKSEL_24M);
+ val &= ~RC_CAL_TOGGLE;
+ writel(val, regs + PCIE_RC_CAL_REG2);
+
+ /* Now trigger recalibration by setting RC_CAL_TOGGLE again */
+ val |= RC_CAL_TOGGLE;
+ writel(val, regs + PCIE_RC_CAL_REG2);
+
+ val = readl(regs + PCIE_LTSSM_DIS_ENTRY);
+ /* Override the reference clock; set to refclk driver mode */
+ val |= OVRD_REFCLK_MODE;
+ val &= ~CFG_REFCLK_MODE;
+ val |= FIELD_PREP(CFG_REFCLK_MODE, RFCLK_MODE_DRIVER);
+ writel(val, regs + PCIE_LTSSM_DIS_ENTRY);
+
+ regs += PHY_LANE_OFFSET; /* Next lane */
+ }
+}
+
+/* Only called for combo PHY */
+static void k1_pcie_phy_init_usb(struct k1_pcie_phy *k1_phy)
+{
+ k1_combo_phy_sel(k1_phy, true);
+
+ /* We're not doing any testing */
+ writel(0, k1_phy->regs + USB3_TEST_CTRL);
+}
+
+static int k1_pcie_phy_init(struct phy *phy)
+{
+ struct k1_pcie_phy *k1_phy = phy_get_drvdata(phy);
+
+ /* Note: port type is only valid for port A (both checks needed) */
+ if (k1_phy_port_a(k1_phy) && k1_phy->type == PHY_TYPE_USB3)
+ k1_pcie_phy_init_usb(k1_phy);
+ else
+ k1_pcie_phy_init_pcie(k1_phy);
+
+
+ return clk_prepare_enable(k1_phy->pll);
+}
+
+static int k1_pcie_phy_exit(struct phy *phy)
+{
+ struct k1_pcie_phy *k1_phy = phy_get_drvdata(phy);
+
+ clk_disable_unprepare(k1_phy->pll);
+
+ return 0;
+}
+
+static const struct phy_ops k1_pcie_phy_ops = {
+ .init = k1_pcie_phy_init,
+ .exit = k1_pcie_phy_exit,
+ .owner = THIS_MODULE,
+};
+
+/*
+ * Get values needed for calibrating PHYs operating in PCIe mode. Only
+ * the combo PHY is able to do this, and its calibration values are used
+ * for configuring all PCIe PHYs.
+ *
+ * We always need to de-assert the "global" reset on the combo PHY,
+ * because the USB driver depends on it. If used for PCIe, that driver
+ * will (also) de-assert this, but by leaving it de-asserted for the
+ * combo PHY, the USB driver doesn't have to do this. Note: although
+ * SpacemiT refers to this as the global reset, we name the "phy" reset.
+ *
+ * In addition, we guarantee the APP_HOLD_PHY_RESET bit is clear for the
+ * combo PHY, so the USB driver doesn't have to manage that either. The
+ * PCIe driver is free to change this bit for normal operation.
+ *
+ * Calibration only needs to be done once. It's possible calibration has
+ * already completed (e.g., it might have happened in the boot loader, or
+ * -EPROBE_DEFER might result in this function being called again). So we
+ * check that early too, to avoid doing it more than once.
+ *
+ * Otherwise we temporarily power up the PHY using the PCIe app clocks
+ * and resets, wait for the hardware to indicate calibration is done,
+ * grab the value, then shut the PHY down again.
+ */
+static int k1_pcie_combo_phy_calibrate(struct k1_pcie_phy *k1_phy)
+{
+ struct reset_control_bulk_data resets[] = {
+ { .id = "dbi", },
+ { .id = "mstr", },
+ { .id = "slv", },
+ };
+ struct clk_bulk_data clocks[] = {
+ { .id = "dbi", },
+ { .id = "mstr", },
+ { .id = "slv", },
+ };
+ struct device *dev = k1_phy->dev;
+ int ret = 0;
+ int val;
+
+ /* Nothing to do if we already set the receiver termination value */
+ if (k1_phy_rterm_valid())
+ return 0;
+
+ /*
+ * We also guarantee the APP_HOLD_PHY_RESET bit is clear. We can
+ * leave this bit clear even if an error happens below.
+ */
+ regmap_assign_bits(k1_phy->pmu, PCIE_CLK_RES_CTRL,
+ PCIE_APP_HOLD_PHY_RST, false);
+
+ /* If the calibration already completed (e.g. by U-Boot), we're done */
+ val = readl(k1_phy->regs + PCIE_RCAL_RESULT);
+ if (val & R_TUNE_DONE)
+ goto out_tune_done;
+
+ /* Put the PHY into PCIe mode */
+ k1_combo_phy_sel(k1_phy, false);
+
+ /* Get and enable the PCIe app clocks */
+ ret = clk_bulk_get(dev, ARRAY_SIZE(clocks), clocks);
+ if (ret < 0)
+ goto out_tune_done;
+ ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks);
+ if (ret)
+ goto out_put_clocks;
+
+ /* Get the PCIe application resets (not the PHY reset) */
+ ret = reset_control_bulk_get_shared(dev, ARRAY_SIZE(resets), resets);
+ if (ret)
+ goto out_disable_clocks;
+
+ /* De-assert the PCIe application resets */
+ ret = reset_control_bulk_deassert(ARRAY_SIZE(resets), resets);
+ if (ret)
+ goto out_put_resets;
+
+ /*
+ * This is the core activity here. Wait for the hardware to
+ * signal that it has completed calibration/tuning. Once it
+ * has, the register value will contain the values we'll
+ * use to configure PCIe PHYs.
+ */
+ ret = readl_poll_timeout(k1_phy->regs + PCIE_RCAL_RESULT,
+ val, val & R_TUNE_DONE,
+ POLL_DELAY, CALIBRATION_TIMEOUT);
+
+ /* Clean up. We're done with the resets and clocks */
+ reset_control_bulk_assert(ARRAY_SIZE(resets), resets);
+out_put_resets:
+ reset_control_bulk_put(ARRAY_SIZE(resets), resets);
+out_disable_clocks:
+ clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks);
+out_put_clocks:
+ clk_bulk_put(ARRAY_SIZE(clocks), clocks);
+out_tune_done:
+ /* If we got the value without timing out, set k1_phy_rterm */
+ if (!ret)
+ k1_phy_rterm_set(val);
+
+ return ret;
+}
+
+static struct phy *
+k1_pcie_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args)
+{
+ struct k1_pcie_phy *k1_phy = dev_get_drvdata(dev);
+ u32 type;
+
+ /* The argument specifying the PHY mode is required */
+ if (args->args_count != 1)
+ return ERR_PTR(-EINVAL);
+
+ /* We only support PCIe and USB 3 mode */
+ type = args->args[0];
+ if (type != PHY_TYPE_PCIE && type != PHY_TYPE_USB3)
+ return ERR_PTR(-EINVAL);
+
+ /* This PHY can only be used once */
+ if (k1_phy->type != PHY_NONE)
+ return ERR_PTR(-EBUSY);
+
+ k1_phy->type = type;
+
+ return k1_phy->phy;
+}
+
+/* Use the maximum number of PCIe lanes unless limited by device tree */
+static u32 k1_pcie_num_lanes(struct k1_pcie_phy *k1_phy, bool port_a)
+{
+ struct device *dev = k1_phy->dev;
+ u32 count = 0;
+ u32 max;
+ int ret;
+
+ ret = of_property_read_u32(dev_of_node(dev), "num-lanes", &count);
+ if (count == 1)
+ return 1;
+
+ if (count == 2 && !port_a)
+ return 2;
+
+ max = port_a ? 1 : 2;
+ if (ret != -EINVAL)
+ dev_warn(dev, "bad lane count %u for port; using %u\n",
+ count, max);
+
+ return max;
+}
+
+static int k1_pcie_combo_phy_probe(struct k1_pcie_phy *k1_phy)
+{
+ struct device *dev = k1_phy->dev;
+ struct regmap *regmap;
+ int ret;
+
+ /* Setting the PHY mode requires access to the PMU regmap */
+ regmap = syscon_regmap_lookup_by_phandle(dev_of_node(dev), SYSCON_APMU);
+ if (IS_ERR(regmap))
+ return dev_err_probe(dev, PTR_ERR(regmap), "failed to get PMU\n");
+ k1_phy->pmu = regmap;
+
+ ret = k1_pcie_combo_phy_calibrate(k1_phy);
+ if (ret)
+ return dev_err_probe(dev, ret, "calibration failed\n");
+
+ /* Needed by k1_pcie_combo_phy_xlate(), which also sets k1_phy->type */
+ dev_set_drvdata(dev, k1_phy);
+
+ return 0;
+}
+
+static int k1_pcie_phy_probe(struct platform_device *pdev)
+{
+ struct phy *(*xlate)(struct device *dev,
+ const struct of_phandle_args *args);
+ struct device *dev = &pdev->dev;
+ struct reset_control *phy_reset;
+ struct phy_provider *provider;
+ struct k1_pcie_phy *k1_phy;
+ bool probing_port_a;
+ int ret;
+
+ xlate = of_device_get_match_data(dev);
+ probing_port_a = xlate == k1_pcie_combo_phy_xlate;
+
+ /* Only the combo PHY can calibrate, so it must probe first */
+ if (!k1_phy_rterm_valid() && !probing_port_a)
+ return -EPROBE_DEFER;
+
+ k1_phy = devm_kzalloc(dev, sizeof(*k1_phy), GFP_KERNEL);
+ if (!k1_phy)
+ return -ENOMEM;
+ k1_phy->dev = dev;
+
+ k1_phy->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(k1_phy->regs))
+ return dev_err_probe(dev, PTR_ERR(k1_phy->regs),
+ "error mapping registers\n");
+
+ /* De-assert the PHY (global) reset and leave it that way */
+ phy_reset = devm_reset_control_get_exclusive_deasserted(dev, "phy");
+ if (IS_ERR(phy_reset))
+ return PTR_ERR(phy_reset);
+
+ if (probing_port_a) {
+ ret = k1_pcie_combo_phy_probe(k1_phy);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "error probing combo phy\n");
+ }
+
+ k1_phy->pcie_lanes = k1_pcie_num_lanes(k1_phy, probing_port_a);
+
+ k1_phy->phy = devm_phy_create(dev, NULL, &k1_pcie_phy_ops);
+ if (IS_ERR(k1_phy->phy))
+ return dev_err_probe(dev, PTR_ERR(k1_phy->phy),
+ "error creating phy\n");
+ phy_set_drvdata(k1_phy->phy, k1_phy);
+
+ ret = k1_pcie_phy_pll_setup(k1_phy);
+ if (ret)
+ return dev_err_probe(dev, ret, "error initializing clock\n");
+
+ provider = devm_of_phy_provider_register(dev, xlate);
+ if (IS_ERR(provider))
+ return dev_err_probe(dev, PTR_ERR(provider),
+ "error registering provider\n");
+ return 0;
+}
+
+static const struct of_device_id k1_pcie_phy_of_match[] = {
+ { .compatible = "spacemit,k1-combo-phy", k1_pcie_combo_phy_xlate, },
+ { .compatible = "spacemit,k1-pcie-phy", of_phy_simple_xlate, },
+ { },
+};
+MODULE_DEVICE_TABLE(of, k1_pcie_phy_of_match);
+
+static struct platform_driver k1_pcie_phy_driver = {
+ .probe = k1_pcie_phy_probe,
+ .driver = {
+ .of_match_table = k1_pcie_phy_of_match,
+ .name = "spacemit-k1-pcie-phy",
+ }
+};
+module_platform_driver(k1_pcie_phy_driver);
+
+MODULE_DESCRIPTION("SpacemiT K1 PCIe and USB 3 PHY driver");
+MODULE_LICENSE("GPL");
--
2.53.0

14
SPECS/linux/0082-FROMLIST-dt-bindings-vendor-prefixes-add-verisilicon.patch → SPECS/linux/0015-UPSTREAM-dt-bindings-vendor-prefixes-add-verisilicon.patch
View File

@@ -1,7 +1,7 @@
From 734f09f341d9e9420a38cb28960a7d7842973e6e Mon Sep 17 00:00:00 2001
From 0a462a41ce3cbe90ba17130e8b9767a0767d13f1 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <uwu@icenowy.me>
Date: Fri, 23 Jan 2026 17:28:22 +0800
Subject: [PATCH 082/197] FROMLIST: dt-bindings: vendor-prefixes: add
Date: Thu, 29 Jan 2026 10:39:15 +0800
Subject: [PATCH 015/189] UPSTREAM: dt-bindings: vendor-prefixes: add
verisilicon
VeriSilicon is a Silicon IP vendor, which is the current owner of
@@ -12,17 +12,19 @@ Add a vendor prefix for this company.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20260123092830.4046009-2-zhengxingda@iscas.ac.cn
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://patch.msgid.link/20260129023922.1527729-2-zhengxingda@iscas.ac.cn
(cherry picked from commit c131d78840d7487e41c3afdc52bb74fd3f8861ef)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index c7591b2aec2a..18f931f36919 100644
index ee7fd3cfe203..1ef679f88203 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1745,6 +1745,8 @@ patternProperties:
@@ -1761,6 +1761,8 @@ patternProperties:
description: Variscite Ltd.
"^vdl,.*":
description: Van der Laan b.v.

41
SPECS/linux/0015-UPSTREAM-riscv-dts-spacemit-Add-a-PCIe-regulator.patch
View File

@@ -1,41 +0,0 @@
From 816016905988fc7e7af77bed041f36d5741f803d Mon Sep 17 00:00:00 2001
From: Alex Elder <elder@riscstar.com>
Date: Thu, 18 Dec 2025 09:12:30 -0600
Subject: [PATCH 015/197] UPSTREAM: riscv: dts: spacemit: Add a PCIe regulator
Define a 3.3v fixed voltage regulator to be used by PCIe on the
Banana Pi BPI-F3. On this platform, this regulator is always on.
Signed-off-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Tested-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20251218151235.454997-5-elder@riscstar.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
(cherry picked from commit 73a6c811fa0d07078c9e1eaecea76ce26fb5f10e)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index 02f218a16318..71f48454ba47 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -33,6 +33,14 @@ led1 {
};
};
+ pcie_vcc_3v3: pcie-vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "PCIE_VCC3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
reg_dc_in: dc-in-12v {
compatible = "regulator-fixed";
regulator-name = "dc_in_12v";
--
2.53.0

10
SPECS/linux/0083-FROMLIST-dt-bindings-display-add-verisilicon-dc.patch → SPECS/linux/0016-UPSTREAM-dt-bindings-display-add-verisilicon-dc.patch
View File

@@ -1,7 +1,7 @@
From fb3e1b8f058d84044407f7a42f456ce4520b031b Mon Sep 17 00:00:00 2001
From b22844d74bf437626e0380d47d106734efde49a7 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <uwu@icenowy.me>
Date: Fri, 23 Jan 2026 17:28:23 +0800
Subject: [PATCH 083/197] FROMLIST: dt-bindings: display: add verisilicon,dc
Date: Thu, 29 Jan 2026 10:39:16 +0800
Subject: [PATCH 016/189] UPSTREAM: dt-bindings: display: add verisilicon,dc
Verisilicon has a series of display controllers prefixed with DC and
with self-identification facility like their GC series GPUs.
@@ -15,7 +15,9 @@ signal (which seems to be some plain parallel bus to HDMI controllers).
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20260123092830.4046009-3-zhengxingda@iscas.ac.cn
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://patch.msgid.link/20260129023922.1527729-3-zhengxingda@iscas.ac.cn
(cherry picked from commit 5f6965fa1e2ec8ac69e1d448d343a528dc60cdfb)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../bindings/display/verisilicon,dc.yaml | 122 ++++++++++++++++++

331
SPECS/linux/0016-UPSTREAM-riscv-dts-spacemit-PCIe-and-PHY-related-upd.patch
View File

@@ -1,331 +0,0 @@
From e17e5a91d6d6a4d5fc8d87dc1fc52c52e322abde Mon Sep 17 00:00:00 2001
From: Alex Elder <elder@riscstar.com>
Date: Thu, 18 Dec 2025 09:12:31 -0600
Subject: [PATCH 016/197] UPSTREAM: riscv: dts: spacemit: PCIe and PHY-related
updates
Define PCIe and PHY-related Device Tree nodes for the SpacemiT K1 SoC.
Enable the combo PHY and the two PCIe-only PHYs on the Banana Pi BPI-F3
board. The combo PHY is used for USB on this board, and that will be
enabled when USB 3 support is accepted.
The combo PHY must perform a calibration step to determine configuration
values used by the PCIe-only PHYs. As a result, it must be enabled if
either of the other two PHYs is enabled.
Signed-off-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Tested-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20251218151235.454997-6-elder@riscstar.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
(cherry picked from commit 0be016a4b5d1b927de04e2e7a0a2bce51aacbfff)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../boot/dts/spacemit/k1-bananapi-f3.dts | 36 ++++
arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 33 ++++
arch/riscv/boot/dts/spacemit/k1.dtsi | 176 ++++++++++++++++++
3 files changed, 245 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index 71f48454ba47..3f10efd925dc 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -61,6 +61,12 @@ reg_vcc_4v: vcc-4v {
};
};
+&combo_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_3_cfg>;
+ status = "okay";
+};
+
&emmc {
bus-width = <8>;
mmc-hs400-1_8v;
@@ -272,6 +278,36 @@ dldo7 {
};
};
+&pcie1_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_3_cfg>;
+ status = "okay";
+};
+
+&pcie1_port {
+ phys = <&pcie1_phy>;
+};
+
+&pcie1 {
+ vpcie3v3-supply = <&pcie_vcc_3v3>;
+ status = "okay";
+};
+
+&pcie2_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_4_cfg>;
+ status = "okay";
+};
+
+&pcie2_port {
+ phys = <&pcie2_phy>;
+};
+
+&pcie2 {
+ vpcie3v3-supply = <&pcie_vcc_3v3>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_2_cfg>;
diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
index e922e05ff856..b13dcb10f4d6 100644
--- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
@@ -530,6 +530,39 @@ uart9-2-pins {
};
};
+ pcie0_3_cfg: pcie0-3-cfg {
+ pcie0-3-pins {
+ pinmux = <K1_PADCONF(54, 3)>, /* PERST# */
+ <K1_PADCONF(55, 3)>, /* WAKE# */
+ <K1_PADCONF(53, 3)>; /* CLKREQ# */
+
+ bias-pull-up = <0>;
+ drive-strength = <21>;
+ };
+ };
+
+ pcie1_3_cfg: pcie1-3-cfg {
+ pcie1-3-pins {
+ pinmux = <K1_PADCONF(59, 4)>, /* PERST# */
+ <K1_PADCONF(60, 4)>, /* WAKE# */
+ <K1_PADCONF(61, 4)>; /* CLKREQ# */
+
+ bias-pull-up = <0>;
+ drive-strength = <21>;
+ };
+ };
+
+ pcie2_4_cfg: pcie2-4-cfg {
+ pcie2-4-pins {
+ pinmux = <K1_PADCONF(62, 4)>, /* PERST# */
+ <K1_PADCONF(112, 3)>, /* WAKE# */
+ <K1_PADCONF(117, 4)>; /* CLKREQ# */
+
+ bias-pull-up = <0>;
+ drive-strength = <21>;
+ };
+ };
+
pwm14_1_cfg: pwm14-1-cfg {
pwm14-1-pins {
pinmux = <K1_PADCONF(44, 4)>;
diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index 7818ca4979b6..86d1db14e2ee 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/clock/spacemit,k1-syscon.h>
+#include <dt-bindings/phy/phy.h>
/dts-v1/;
/ {
@@ -423,6 +424,52 @@ i2c5: i2c@d4013800 {
status = "disabled";
};
+ combo_phy: phy@c0b10000 {
+ compatible = "spacemit,k1-combo-phy";
+ reg = <0x0 0xc0b10000 0x0 0x1000>;
+ clocks = <&vctcxo_24m>,
+ <&syscon_apmu CLK_PCIE0_DBI>,
+ <&syscon_apmu CLK_PCIE0_MASTER>,
+ <&syscon_apmu CLK_PCIE0_SLAVE>;
+ clock-names = "refclk",
+ "dbi",
+ "mstr",
+ "slv";
+ resets = <&syscon_apmu RESET_PCIE0_GLOBAL>,
+ <&syscon_apmu RESET_PCIE0_DBI>,
+ <&syscon_apmu RESET_PCIE0_MASTER>,
+ <&syscon_apmu RESET_PCIE0_SLAVE>;
+ reset-names = "phy",
+ "dbi",
+ "mstr",
+ "slv";
+ #phy-cells = <1>;
+ spacemit,apmu = <&syscon_apmu>;
+ status = "disabled";
+ };
+
+ pcie1_phy: phy@c0c10000 {
+ compatible = "spacemit,k1-pcie-phy";
+ reg = <0x0 0xc0c10000 0x0 0x1000>;
+ clocks = <&vctcxo_24m>;
+ clock-names = "refclk";
+ resets = <&syscon_apmu RESET_PCIE1_GLOBAL>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ pcie2_phy: phy@c0d10000 {
+ compatible = "spacemit,k1-pcie-phy";
+ reg = <0x0 0xc0d10000 0x0 0x1000>;
+ clocks = <&vctcxo_24m>;
+ clock-names = "refclk";
+ resets = <&syscon_apmu RESET_PCIE2_GLOBAL>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
syscon_apbc: system-controller@d4015000 {
compatible = "spacemit,k1-syscon-apbc";
reg = <0x0 0xd4015000 0x0 0x1000>;
@@ -969,6 +1016,135 @@ pcie-bus {
#size-cells = <2>;
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
<0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>;
+ pcie0: pcie@ca000000 {
+ device_type = "pci";
+ compatible = "spacemit,k1-pcie";
+ reg = <0x0 0xca000000 0x0 0x00001000>,
+ <0x0 0xca300000 0x0 0x0001ff24>,
+ <0x0 0x8f000000 0x0 0x00002000>,
+ <0x0 0xc0b20000 0x0 0x00001000>;
+ reg-names = "dbi",
+ "atu",
+ "config",
+ "link";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>,
+ <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x0f000000>;
+ interrupts = <141>;
+ interrupt-names = "msi";
+ clocks = <&syscon_apmu CLK_PCIE0_DBI>,
+ <&syscon_apmu CLK_PCIE0_MASTER>,
+ <&syscon_apmu CLK_PCIE0_SLAVE>;
+ clock-names = "dbi",
+ "mstr",
+ "slv";
+ resets = <&syscon_apmu RESET_PCIE0_DBI>,
+ <&syscon_apmu RESET_PCIE0_MASTER>,
+ <&syscon_apmu RESET_PCIE0_SLAVE>;
+ reset-names = "dbi",
+ "mstr",
+ "slv";
+ spacemit,apmu = <&syscon_apmu 0x03cc>;
+ status = "disabled";
+
+ pcie0_port: pcie@0 {
+ device_type = "pci";
+ compatible = "pciclass,0604";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+
+ pcie1: pcie@ca400000 {
+ device_type = "pci";
+ compatible = "spacemit,k1-pcie";
+ reg = <0x0 0xca400000 0x0 0x00001000>,
+ <0x0 0xca700000 0x0 0x0001ff24>,
+ <0x0 0x9f000000 0x0 0x00002000>,
+ <0x0 0xc0c20000 0x0 0x00001000>;
+ reg-names = "dbi",
+ "atu",
+ "config",
+ "link";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>,
+ <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x0f000000>;
+ interrupts = <142>;
+ interrupt-names = "msi";
+ clocks = <&syscon_apmu CLK_PCIE1_DBI>,
+ <&syscon_apmu CLK_PCIE1_MASTER>,
+ <&syscon_apmu CLK_PCIE1_SLAVE>;
+ clock-names = "dbi",
+ "mstr",
+ "slv";
+ resets = <&syscon_apmu RESET_PCIE1_DBI>,
+ <&syscon_apmu RESET_PCIE1_MASTER>,
+ <&syscon_apmu RESET_PCIE1_SLAVE>;
+ reset-names = "dbi",
+ "mstr",
+ "slv";
+ spacemit,apmu = <&syscon_apmu 0x3d4>;
+ status = "disabled";
+
+ pcie1_port: pcie@0 {
+ device_type = "pci";
+ compatible = "pciclass,0604";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+
+ pcie2: pcie@ca800000 {
+ device_type = "pci";
+ compatible = "spacemit,k1-pcie";
+ reg = <0x0 0xca800000 0x0 0x00001000>,
+ <0x0 0xcab00000 0x0 0x0001ff24>,
+ <0x0 0xb7000000 0x0 0x00002000>,
+ <0x0 0xc0d20000 0x0 0x00001000>;
+ reg-names = "dbi",
+ "atu",
+ "config",
+ "link";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x00000000 0x0 0xb7002000 0x0 0x00100000>,
+ <0x42000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000>,
+ <0x02000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x07000000>;
+ interrupts = <143>;
+ interrupt-names = "msi";
+ clocks = <&syscon_apmu CLK_PCIE2_DBI>,
+ <&syscon_apmu CLK_PCIE2_MASTER>,
+ <&syscon_apmu CLK_PCIE2_SLAVE>;
+ clock-names = "dbi",
+ "mstr",
+ "slv";
+ resets = <&syscon_apmu RESET_PCIE2_DBI>,
+ <&syscon_apmu RESET_PCIE2_MASTER>,
+ <&syscon_apmu RESET_PCIE2_SLAVE>;
+ reset-names = "dbi",
+ "mstr",
+ "slv";
+ spacemit,apmu = <&syscon_apmu 0x3dc>;
+ status = "disabled";
+
+ pcie2_port: pcie@0 {
+ device_type = "pci";
+ compatible = "pciclass,0604";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
};
storage-bus {
--
2.53.0

64
SPECS/linux/0084-FROMLIST-drm-verisilicon-add-a-driver-for-Verisilico.patch → SPECS/linux/0017-UPSTREAM-drm-verisilicon-add-a-driver-for-Verisilico.patch
View File

@@ -1,7 +1,7 @@
From fadaa298ad9bed9e0e13597fc7162c80e455a953 Mon Sep 17 00:00:00 2001
From 65e87bf77f4e8a8291eb2691fb1b1db0ccefb1e7 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <uwu@icenowy.me>
Date: Fri, 23 Jan 2026 17:28:24 +0800
Subject: [PATCH 084/197] FROMLIST: drm: verisilicon: add a driver for
Date: Thu, 29 Jan 2026 10:39:17 +0800
Subject: [PATCH 017/189] UPSTREAM: drm: verisilicon: add a driver for
Verisilicon display controllers
This is a from-scratch driver targeting Verisilicon DC-series display
@@ -21,12 +21,16 @@ Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Tested-by: Han Gao <gaohan@iscas.ac.cn>
Tested-by: Michal Wilczynski <m.wilczynski@samsung.com>
Link: https://lore.kernel.org/r/20260123092830.4046009-4-zhengxingda@iscas.ac.cn
Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de>
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://patch.msgid.link/20260129023922.1527729-4-zhengxingda@iscas.ac.cn
(cherry picked from commit dbf21777caa8b8c88c12f7f036b01208fec0d55a)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/gpu/drm/Kconfig | 2 +
MAINTAINERS | 7 +
drivers/gpu/drm/Kconfig | 1 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/verisilicon/Kconfig | 15 +
drivers/gpu/drm/verisilicon/Kconfig | 16 +
drivers/gpu/drm/verisilicon/Makefile | 5 +
drivers/gpu/drm/verisilicon/vs_bridge.c | 371 ++++++++++++++++++
drivers/gpu/drm/verisilicon/vs_bridge.h | 39 ++
@@ -45,7 +49,7 @@ Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
drivers/gpu/drm/verisilicon/vs_plane.h | 72 ++++
.../gpu/drm/verisilicon/vs_primary_plane.c | 173 ++++++++
.../drm/verisilicon/vs_primary_plane_regs.h | 53 +++
21 files changed, 1852 insertions(+)
22 files changed, 1859 insertions(+)
create mode 100644 drivers/gpu/drm/verisilicon/Kconfig
create mode 100644 drivers/gpu/drm/verisilicon/Makefile
create mode 100644 drivers/gpu/drm/verisilicon/vs_bridge.c
@@ -66,21 +70,38 @@ Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
create mode 100644 drivers/gpu/drm/verisilicon/vs_primary_plane.c
create mode 100644 drivers/gpu/drm/verisilicon/vs_primary_plane_regs.h
diff --git a/MAINTAINERS b/MAINTAINERS
index d1cc0e12fe1f..7edc13840626 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8798,6 +8798,13 @@ F: Documentation/devicetree/bindings/display/brcm,bcm2835-*.yaml
F: drivers/gpu/drm/vc4/
F: include/uapi/drm/vc4_drm.h
+DRM DRIVERS FOR VERISILICON DISPLAY CONTROLLER IP
+M: Icenowy Zheng <zhengxingda@iscas.ac.cn>
+L: dri-devel@lists.freedesktop.org
+S: Maintained
+F: Documentation/devicetree/bindings/display/verisilicon,dc.yaml
+F: drivers/gpu/drm/verisilicon/
+
DRM DRIVERS FOR VIVANTE GPU IP
M: Lucas Stach <l.stach@pengutronix.de>
R: Russell King <linux+etnaviv@armlinux.org.uk>
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index ed85d0ceee3b..a0917595d11c 100644
index d3d52310c9cc..5888eb147ed1 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -398,6 +398,8 @@ source "drivers/gpu/drm/imagination/Kconfig"
source "drivers/gpu/drm/tyr/Kconfig"
@@ -335,6 +335,7 @@ source "drivers/gpu/drm/udl/Kconfig"
source "drivers/gpu/drm/v3d/Kconfig"
source "drivers/gpu/drm/vboxvideo/Kconfig"
source "drivers/gpu/drm/vc4/Kconfig"
+source "drivers/gpu/drm/verisilicon/Kconfig"
+
config DRM_HYPERV
tristate "DRM Support for Hyper-V synthetic video device"
depends on DRM && PCI && HYPERV_VMBUS
source "drivers/gpu/drm/vgem/Kconfig"
source "drivers/gpu/drm/virtio/Kconfig"
source "drivers/gpu/drm/vkms/Kconfig"
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index d26191717428..a5727a1bf833 100644
index ec2c5ff82382..387943393898 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -237,6 +237,7 @@ obj-y += solomon/
@@ -93,19 +114,20 @@ index d26191717428..a5727a1bf833 100644
hdrtest-files := \
diff --git a/drivers/gpu/drm/verisilicon/Kconfig b/drivers/gpu/drm/verisilicon/Kconfig
new file mode 100644
index 000000000000..0235577c7282
index 000000000000..7cce86ec8603
--- /dev/null
+++ b/drivers/gpu/drm/verisilicon/Kconfig
@@ -0,0 +1,15 @@
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config DRM_VERISILICON_DC
+ tristate "DRM Support for Verisilicon DC-series display controllers"
+ depends on DRM && COMMON_CLK
+ depends on RISCV || COMPILER_TEST
+ depends on RISCV || COMPILE_TEST
+ select DRM_BRIDGE_CONNECTOR
+ select DRM_CLIENT_SELECTION
+ select DRM_DISPLAY_HELPER
+ select DRM_GEM_DMA_HELPER
+ select DRM_KMS_HELPER
+ select DRM_BRIDGE_CONNECTOR
+ select REGMAP_MMIO
+ select VIDEOMODE_HELPERS
+ help

38
SPECS/linux/0017-UPSTREAM-dt-bindings-i2c-spacemit-add-optional-reset.patch
View File

@@ -1,38 +0,0 @@
From 755be63d1169933bded11bc11962ebeaca162ae9 Mon Sep 17 00:00:00 2001
From: Encrow Thorne <jyc0019@gmail.com>
Date: Tue, 30 Dec 2025 23:06:51 +0800
Subject: [PATCH 017/197] UPSTREAM: dt-bindings: i2c: spacemit: add optional
resets
The I2C controller requires a reset to ensure it starts from a clean state.
Add the 'resets' property to support this hardware requirement.
Signed-off-by: Encrow Thorne <jyc0019@gmail.com>
Reviewed-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20251230150653.42097-1-jyc0019@gmail.com
(cherry picked from commit ad0876a84631fee7b0ad4cd8118b9696aa566671)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml
index b7220fff2235..5896fb120501 100644
--- a/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml
@@ -41,6 +41,9 @@ properties:
default: 400000
maximum: 3300000
+ resets:
+ maxItems: 1
+
required:
- compatible
- reg
--
2.53.0

10
SPECS/linux/0085-FROMLIST-dt-bindings-display-bridge-add-binding-for-.patch → SPECS/linux/0018-UPSTREAM-dt-bindings-display-bridge-add-binding-for-.patch
View File

@@ -1,7 +1,7 @@
From 39ffe402477f3b1989c1b8f5032ca02cfbc951c3 Mon Sep 17 00:00:00 2001
From 80047b6b46af7db6fe6604d1c72eed35a7bb36cf Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <uwu@icenowy.me>
Date: Fri, 23 Jan 2026 17:28:25 +0800
Subject: [PATCH 085/197] FROMLIST: dt-bindings: display/bridge: add binding
Date: Thu, 29 Jan 2026 10:39:18 +0800
Subject: [PATCH 018/189] UPSTREAM: dt-bindings: display/bridge: add binding
for TH1520 HDMI controller
T-Head TH1520 SoC contains a Synopsys DesignWare HDMI controller paired
@@ -13,7 +13,9 @@ Add a device tree binding to it.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20260123092830.4046009-5-zhengxingda@iscas.ac.cn
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://patch.msgid.link/20260129023922.1527729-5-zhengxingda@iscas.ac.cn
(cherry picked from commit 3d60ff99a78ccd3b72765542dd083b134d6ae4bb)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../display/bridge/thead,th1520-dw-hdmi.yaml | 120 ++++++++++++++++++

56
SPECS/linux/0018-UPSTREAM-i2c-k1-add-reset-support.patch
View File

@@ -1,56 +0,0 @@
From f6e993d7f03145a634f970a79023e366bc68f3e3 Mon Sep 17 00:00:00 2001
From: Encrow Thorne <jyc0019@gmail.com>
Date: Tue, 30 Dec 2025 23:06:52 +0800
Subject: [PATCH 018/197] UPSTREAM: i2c: k1: add reset support
The K1 I2C controller provides a reset line that needs to be deasserted
before the controller can be accessed.
Add reset support to the driver to ensure the controller starts in the
required state.
Signed-off-by: Encrow Thorne <jyc0019@gmail.com>
Reviewed-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20251230150653.42097-2-jyc0019@gmail.com
(cherry picked from commit b96259551b337225bb0e7afb3452b98435dd8b81)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/i2c/busses/i2c-k1.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c
index 8ef6d5d1927b..d0948a16de3e 100644
--- a/drivers/i2c/busses/i2c-k1.c
+++ b/drivers/i2c/busses/i2c-k1.c
@@ -10,6 +10,7 @@
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
+ #include <linux/reset.h>
/* spacemit i2c registers */
#define SPACEMIT_ICR 0x0 /* Control register */
@@ -534,6 +535,7 @@ static int spacemit_i2c_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *of_node = pdev->dev.of_node;
struct spacemit_i2c_dev *i2c;
+ struct reset_control *rst;
int ret;
i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
@@ -578,6 +580,11 @@ static int spacemit_i2c_probe(struct platform_device *pdev)
if (IS_ERR(clk))
return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock");
+ rst = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL);
+ if (IS_ERR(rst))
+ return dev_err_probe(dev, PTR_ERR(rst),
+ "failed to acquire deasserted reset\n");
+
spacemit_i2c_reset(i2c);
i2c_set_adapdata(&i2c->adapt, i2c);
--
2.53.0

23
SPECS/linux/0086-FROMLIST-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch → SPECS/linux/0019-UPSTREAM-drm-bridge-add-a-driver-for-T-Head-TH1520-H.patch
View File

@@ -1,7 +1,7 @@
From e7a19561b84f0bd1e3138f1d72577b55cbce9f9d Mon Sep 17 00:00:00 2001
From c2beb18b0c4f2524c33026b6780a7deb9884f261 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <uwu@icenowy.me>
Date: Fri, 23 Jan 2026 17:28:26 +0800
Subject: [PATCH 086/197] FROMLIST: drm/bridge: add a driver for T-Head TH1520
Date: Thu, 29 Jan 2026 10:39:19 +0800
Subject: [PATCH 019/189] UPSTREAM: drm/bridge: add a driver for T-Head TH1520
HDMI controller
T-Head TH1520 SoC contains a Synopsys DesignWare HDMI controller (paired
@@ -15,7 +15,10 @@ Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Tested-by: Han Gao <gaohan@iscas.ac.cn>
Tested-by: Michal Wilczynski <m.wilczynski@samsung.com>
Link: https://lore.kernel.org/r/20260123092830.4046009-6-zhengxingda@iscas.ac.cn
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://patch.msgid.link/20260129023922.1527729-6-zhengxingda@iscas.ac.cn
(cherry picked from commit 96f30ee0fb9db1663eb8fd55c12e4c67da8c4a90)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
MAINTAINERS | 1 +
@@ -26,10 +29,10 @@ Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
create mode 100644 drivers/gpu/drm/bridge/th1520-dw-hdmi.c
diff --git a/MAINTAINERS b/MAINTAINERS
index e08767323763..7f6615e0295e 100644
index 7edc13840626..08394b6c2f87 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22592,6 +22592,7 @@ F: Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml
@@ -22840,6 +22840,7 @@ F: Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml
F: arch/riscv/boot/dts/thead/
F: drivers/clk/thead/clk-th1520-ap.c
F: drivers/firmware/thead,th1520-aon.c
@@ -38,10 +41,10 @@ index e08767323763..7f6615e0295e 100644
F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c
F: drivers/pinctrl/pinctrl-th1520.c
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index a250afd8d662..8e19f5fb9ad7 100644
index 39385deafc68..1cabfa1d2b2e 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -335,6 +335,16 @@ config DRM_THINE_THC63LVD1024
@@ -342,6 +342,16 @@ config DRM_THINE_THC63LVD1024
help
Thine THC63LVD1024 LVDS/parallel converter driver.
@@ -59,10 +62,10 @@ index a250afd8d662..8e19f5fb9ad7 100644
tristate "TC358762 DSI/DPI bridge"
depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index c7dc03182e59..085b5db45d6f 100644
index 909c21cc3acd..fb0cf0bf8875 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_DRM_SII902X) += sii902x.o
@@ -29,6 +29,7 @@ obj-$(CONFIG_DRM_SII902X) += sii902x.o
obj-$(CONFIG_DRM_SII9234) += sii9234.o
obj-$(CONFIG_DRM_SIMPLE_BRIDGE) += simple-bridge.o
obj-$(CONFIG_DRM_SOLOMON_SSD2825) += ssd2825.o

87
SPECS/linux/0019-UPSTREAM-riscv-dts-spacemit-add-reset-property.patch
View File

@@ -1,87 +0,0 @@
From 699fd40bbe435c072198c84bbb0b6c2834eb6d65 Mon Sep 17 00:00:00 2001
From: Encrow Thorne <jyc0019@gmail.com>
Date: Tue, 30 Dec 2025 23:06:53 +0800
Subject: [PATCH 019/197] UPSTREAM: riscv: dts: spacemit: add reset property
Add resets property to K1 I2C node.
Signed-off-by: Encrow Thorne <jyc0019@gmail.com>
Link: https://lore.kernel.org/r/20251230150653.42097-3-jyc0019@gmail.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
(cherry picked from commit 7d6fe7e381d2912300df06e1a7e7a6f6a9269af0)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/spacemit/k1.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index 86d1db14e2ee..4c045da95d72 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -368,6 +368,7 @@ i2c0: i2c@d4010800 {
<&syscon_apbc CLK_TWSI0_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
+ resets = <&syscon_apbc RESET_TWSI0>;
interrupts = <36>;
status = "disabled";
};
@@ -381,6 +382,7 @@ i2c1: i2c@d4011000 {
<&syscon_apbc CLK_TWSI1_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
+ resets = <&syscon_apbc RESET_TWSI1>;
interrupts = <37>;
status = "disabled";
};
@@ -394,6 +396,7 @@ i2c2: i2c@d4012000 {
<&syscon_apbc CLK_TWSI2_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
+ resets = <&syscon_apbc RESET_TWSI2>;
interrupts = <38>;
status = "disabled";
};
@@ -407,6 +410,7 @@ i2c4: i2c@d4012800 {
<&syscon_apbc CLK_TWSI4_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
+ resets = <&syscon_apbc RESET_TWSI4>;
interrupts = <40>;
status = "disabled";
};
@@ -420,6 +424,7 @@ i2c5: i2c@d4013800 {
<&syscon_apbc CLK_TWSI5_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
+ resets = <&syscon_apbc RESET_TWSI5>;
interrupts = <41>;
status = "disabled";
};
@@ -490,6 +495,7 @@ i2c6: i2c@d4018800 {
<&syscon_apbc CLK_TWSI6_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
+ resets = <&syscon_apbc RESET_TWSI6>;
interrupts = <70>;
status = "disabled";
};
@@ -593,6 +599,7 @@ i2c7: i2c@d401d000 {
<&syscon_apbc CLK_TWSI7_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
+ resets = <&syscon_apbc RESET_TWSI7>;
interrupts = <18>;
status = "disabled";
};
@@ -606,6 +613,7 @@ i2c8: i2c@d401d800 {
<&syscon_apbc CLK_TWSI8_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
+ resets = <&syscon_apbc RESET_TWSI8>;
interrupts = <19>;
status = "disabled";
};
--
2.53.0

18
SPECS/linux/0114-FROMLIST-dt-bindings-mfd-spacemit-p1-Add-individual-.patch → SPECS/linux/0020-UPSTREAM-dt-bindings-mfd-spacemit-p1-Add-individual-.patch
View File

@@ -1,7 +1,7 @@
From 10fd48e60fe2836419c7f15e78cecebbaf7fe82f Mon Sep 17 00:00:00 2001
From 22183de70b126211700ea83c21577a6f340dafc5 Mon Sep 17 00:00:00 2001
From: Guodong Xu <guodong@riscstar.com>
Date: Sat, 24 Jan 2026 08:20:17 +0800
Subject: [PATCH 114/197] FROMLIST: dt-bindings: mfd: spacemit,p1: Add
Date: Fri, 6 Feb 2026 10:32:02 +0800
Subject: [PATCH 020/189] UPSTREAM: dt-bindings: mfd: spacemit,p1: Add
individual regulator supply properties
Add supply properties that match the P1 PMIC's actual hardware topology
@@ -9,12 +9,16 @@ where each buck converter has its own VIN pin and LDO groups share
common input pins. Supply names are defined according to the pinout
names in the P1 datasheet.
This allows different boards to describe their actual power tree
connections in devicetree rather than hardcoding supply relationships
in the driver.
The existing "vin-supply" is dropped from the binding document as the
updated spacemit P1 driver no longer parses it. Only the per-rail names
("vin1-supply", "vin2-supply", ...) are supported.
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Link: https://lore.kernel.org/r/20260124-spacemit-p1-v2-2-2c86b06694ba@riscstar.com
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Alex Elder <elder@riscstar.com>
Link: https://patch.msgid.link/20260206-spacemit-p1-v4-1-8f695d93811e@riscstar.com
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit 82ffa9610ba39d3628a9bec968ddc68fe2fe6612)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../devicetree/bindings/mfd/spacemit,p1.yaml | 49 ++++++++++++++++++-

69
SPECS/linux/0020-UPSTREAM-dt-bindings-phy-spacemit-add-K1-USB2-PHY.patch
View File

@@ -1,69 +0,0 @@
From 2bc92cfc661e4978bc1b472573ea816c06a161e5 Mon Sep 17 00:00:00 2001
From: Ze Huang <huang.ze@linux.dev>
Date: Fri, 17 Oct 2025 22:49:52 +0800
Subject: [PATCH 020/197] UPSTREAM: dt-bindings: phy: spacemit: add K1 USB2 PHY
Add support for USB2 PHY found on SpacemiT K1 SoC.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Ze Huang <huang.ze@linux.dev>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Tested-by: Junzhong Pan <panjunzhong@linux.spacemit.com>
Link: https://patch.msgid.link/20251017-k1-usb2phy-v6-1-7cf9ea2477a1@linux.dev
Signed-off-by: Vinod Koul <vkoul@kernel.org>
(cherry picked from commit 61b84d5b20af2a4c9944972202c1386026598928)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../bindings/phy/spacemit,usb2-phy.yaml | 40 +++++++++++++++++++
1 file changed, 40 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml
new file mode 100644
index 000000000000..43eaca90d88c
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/spacemit,usb2-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT K1 SoC USB 2.0 PHY
+
+maintainers:
+ - Ze Huang <huang.ze@linux.dev>
+
+properties:
+ compatible:
+ const: spacemit,k1-usb2-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ usb-phy@c09c0000 {
+ compatible = "spacemit,k1-usb2-phy";
+ reg = <0xc09c0000 0x200>;
+ clocks = <&syscon_apmu 15>;
+ #phy-cells = <0>;
+ };
--
2.53.0

297
SPECS/linux/0021-UPSTREAM-phy-spacemit-support-K1-USB2.0-PHY-controll.patch
View File

@@ -1,297 +0,0 @@
From 8cbbd62ecc06e393d6e9bc9b2727a862a841c92a Mon Sep 17 00:00:00 2001
From: Ze Huang <huang.ze@linux.dev>
Date: Fri, 17 Oct 2025 22:49:53 +0800
Subject: [PATCH 021/197] UPSTREAM: phy: spacemit: support K1 USB2.0 PHY
controller
The SpacemiT K1 SoC includes three USB ports:
- One USB2.0 OTG port
- One USB2.0 host-only port
- One USB3.0 port with an integrated USB2.0 DRD interface
Each of these ports is connected to a USB2.0 PHY responsible for USB2
transmission.
This commit adds support for the SpacemiT K1 USB2.0 PHY, which is
compliant with the USB 2.0 specification and supports both 8-bit 60MHz
and 16-bit 30MHz parallel interfaces.
Signed-off-by: Ze Huang <huang.ze@linux.dev>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Tested-by: Junzhong Pan <panjunzhong@linux.spacemit.com>
Link: https://patch.msgid.link/20251017-k1-usb2phy-v6-2-7cf9ea2477a1@linux.dev
Signed-off-by: Vinod Koul <vkoul@kernel.org>
(cherry picked from commit fe4bc1a08638309b6be1af37210930b856908eb7)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/phy/Kconfig | 1 +
drivers/phy/Makefile | 1 +
drivers/phy/spacemit/Kconfig | 13 ++
drivers/phy/spacemit/Makefile | 2 +
drivers/phy/spacemit/phy-k1-usb2.c | 200 +++++++++++++++++++++++++++++
5 files changed, 217 insertions(+)
create mode 100644 drivers/phy/spacemit/Kconfig
create mode 100644 drivers/phy/spacemit/Makefile
create mode 100644 drivers/phy/spacemit/phy-k1-usb2.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 1984c2e56122..95ee47f0fbc7 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -134,6 +134,7 @@ source "drivers/phy/rockchip/Kconfig"
source "drivers/phy/samsung/Kconfig"
source "drivers/phy/socionext/Kconfig"
source "drivers/phy/sophgo/Kconfig"
+source "drivers/phy/spacemit/Kconfig"
source "drivers/phy/st/Kconfig"
source "drivers/phy/starfive/Kconfig"
source "drivers/phy/sunplus/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index a206133a3515..950dd4f14372 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -37,6 +37,7 @@ obj-y += allwinner/ \
samsung/ \
socionext/ \
sophgo/ \
+ spacemit/ \
st/ \
starfive/ \
sunplus/ \
diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig
new file mode 100644
index 000000000000..0136aee2e8a2
--- /dev/null
+++ b/drivers/phy/spacemit/Kconfig
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Phy drivers for SpacemiT platforms
+#
+config PHY_SPACEMIT_K1_USB2
+ tristate "SpacemiT K1 USB 2.0 PHY support"
+ depends on (ARCH_SPACEMIT || COMPILE_TEST) && OF
+ depends on COMMON_CLK
+ depends on USB_COMMON
+ select GENERIC_PHY
+ help
+ Enable this to support K1 USB 2.0 PHY driver. This driver takes care of
+ enabling and clock setup and will be used by K1 udc/ehci/otg/xhci driver.
diff --git a/drivers/phy/spacemit/Makefile b/drivers/phy/spacemit/Makefile
new file mode 100644
index 000000000000..fec0b425a948
--- /dev/null
+++ b/drivers/phy/spacemit/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) += phy-k1-usb2.o
diff --git a/drivers/phy/spacemit/phy-k1-usb2.c b/drivers/phy/spacemit/phy-k1-usb2.c
new file mode 100644
index 000000000000..342061380012
--- /dev/null
+++ b/drivers/phy/spacemit/phy-k1-usb2.c
@@ -0,0 +1,200 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * SpacemiT K1 USB 2.0 PHY driver
+ *
+ * Copyright (C) 2025 SpacemiT (Hangzhou) Technology Co. Ltd
+ * Copyright (C) 2025 Ze Huang <huang.ze@linux.dev>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/iopoll.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/usb/of.h>
+
+#define PHY_RST_MODE_CTRL 0x04
+#define PHY_PLL_RDY BIT(0)
+#define PHY_CLK_CDR_EN BIT(1)
+#define PHY_CLK_PLL_EN BIT(2)
+#define PHY_CLK_MAC_EN BIT(3)
+#define PHY_MAC_RSTN BIT(5)
+#define PHY_CDR_RSTN BIT(6)
+#define PHY_PLL_RSTN BIT(7)
+/*
+ * hs line state sel (Bit 13):
+ * - 1 (Default): Internal HS line state is set to 01 when usb_hs_tx_en is valid.
+ * - 0: Internal HS line state is always driven by usb_hs_lstate.
+ *
+ * fs line state sel (Bit 14):
+ * - 1 (Default): FS line state is determined by the output data
+ * (usb_fs_datain/b).
+ * - 0: FS line state is always determined by the input data (dmo/dpo).
+ */
+#define PHY_HS_LINE_TX_MODE BIT(13)
+#define PHY_FS_LINE_TX_MODE BIT(14)
+
+#define PHY_INIT_MODE_BITS (PHY_FS_LINE_TX_MODE | PHY_HS_LINE_TX_MODE)
+#define PHY_CLK_ENABLE_BITS (PHY_CLK_PLL_EN | PHY_CLK_CDR_EN | \
+ PHY_CLK_MAC_EN)
+#define PHY_DEASSERT_RST_BITS (PHY_PLL_RSTN | PHY_CDR_RSTN | \
+ PHY_MAC_RSTN)
+
+#define PHY_TX_HOST_CTRL 0x10
+#define PHY_HST_DISC_AUTO_CLR BIT(2) /* autoclear hs host disc when re-connect */
+
+#define PHY_HSTXP_HW_CTRL 0x34
+#define PHY_HSTXP_RSTN BIT(2) /* generate reset for clock hstxp */
+#define PHY_CLK_HSTXP_EN BIT(3) /* clock hstxp enable */
+#define PHY_HSTXP_MODE BIT(4) /* 0: force en_txp to be 1; 1: no force */
+
+#define PHY_PLL_DIV_CFG 0x98
+#define PHY_FDIV_FRACT_8_15 GENMASK(7, 0)
+#define PHY_FDIV_FRACT_16_19 GENMASK(11, 8)
+#define PHY_FDIV_FRACT_20_21 BIT(12) /* fdiv_reg<21>, <20>, bit21 == bit20 */
+/*
+ * freq_sel<1:0>
+ * if ref clk freq=24.0MHz-->freq_sel<2:0> == 3b'001, then internal divider value == 80
+ */
+#define PHY_FDIV_FRACT_0_1 GENMASK(14, 13)
+/*
+ * pll divider value selection
+ * 1: divider value will choose internal default value ,dependent on freq_sel<1:0>
+ * 0: divider value will be over ride by fdiv_reg<21:0>
+ */
+#define PHY_DIV_LOCAL_EN BIT(15)
+
+#define PHY_SEL_FREQ_24MHZ 0x01
+#define FDIV_REG_MASK (PHY_FDIV_FRACT_20_21 | PHY_FDIV_FRACT_16_19 | \
+ PHY_FDIV_FRACT_8_15)
+#define FDIV_REG_VAL 0x1ec4 /* 0x100 selects 24MHz, rest are default */
+
+#define K1_USB2PHY_RESET_TIME_MS 50
+
+struct spacemit_usb2phy {
+ struct phy *phy;
+ struct clk *clk;
+ struct regmap *regmap_base;
+};
+
+static const struct regmap_config phy_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = 0x200,
+};
+
+static int spacemit_usb2phy_init(struct phy *phy)
+{
+ struct spacemit_usb2phy *sphy = phy_get_drvdata(phy);
+ struct regmap *map = sphy->regmap_base;
+ u32 val;
+ int ret;
+
+ ret = clk_enable(sphy->clk);
+ if (ret) {
+ dev_err(&phy->dev, "failed to enable clock\n");
+ clk_disable(sphy->clk);
+ return ret;
+ }
+
+ /*
+ * make sure the usb controller is not under reset process before
+ * any configuration
+ */
+ usleep_range(150, 200);
+
+ /* 24M ref clk */
+ val = FIELD_PREP(FDIV_REG_MASK, FDIV_REG_VAL) |
+ FIELD_PREP(PHY_FDIV_FRACT_0_1, PHY_SEL_FREQ_24MHZ) |
+ PHY_DIV_LOCAL_EN;
+ regmap_write(map, PHY_PLL_DIV_CFG, val);
+
+ ret = regmap_read_poll_timeout(map, PHY_RST_MODE_CTRL, val,
+ (val & PHY_PLL_RDY),
+ 500, K1_USB2PHY_RESET_TIME_MS * 1000);
+ if (ret) {
+ dev_err(&phy->dev, "wait PLLREADY timeout\n");
+ clk_disable(sphy->clk);
+ return ret;
+ }
+
+ /* release usb2 phy internal reset and enable clock gating */
+ val = (PHY_INIT_MODE_BITS | PHY_CLK_ENABLE_BITS | PHY_DEASSERT_RST_BITS);
+ regmap_write(map, PHY_RST_MODE_CTRL, val);
+
+ val = (PHY_HSTXP_RSTN | PHY_CLK_HSTXP_EN | PHY_HSTXP_MODE);
+ regmap_write(map, PHY_HSTXP_HW_CTRL, val);
+
+ /* auto clear host disc */
+ regmap_update_bits(map, PHY_TX_HOST_CTRL, PHY_HST_DISC_AUTO_CLR,
+ PHY_HST_DISC_AUTO_CLR);
+
+ return 0;
+}
+
+static int spacemit_usb2phy_exit(struct phy *phy)
+{
+ struct spacemit_usb2phy *sphy = phy_get_drvdata(phy);
+
+ clk_disable(sphy->clk);
+
+ return 0;
+}
+
+static const struct phy_ops spacemit_usb2phy_ops = {
+ .init = spacemit_usb2phy_init,
+ .exit = spacemit_usb2phy_exit,
+ .owner = THIS_MODULE,
+};
+
+static int spacemit_usb2phy_probe(struct platform_device *pdev)
+{
+ struct phy_provider *phy_provider;
+ struct device *dev = &pdev->dev;
+ struct spacemit_usb2phy *sphy;
+ void __iomem *base;
+
+ sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL);
+ if (!sphy)
+ return -ENOMEM;
+
+ sphy->clk = devm_clk_get_prepared(&pdev->dev, NULL);
+ if (IS_ERR(sphy->clk))
+ return dev_err_probe(dev, PTR_ERR(sphy->clk), "Failed to get clock\n");
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ sphy->regmap_base = devm_regmap_init_mmio(dev, base, &phy_regmap_config);
+ if (IS_ERR(sphy->regmap_base))
+ return dev_err_probe(dev, PTR_ERR(sphy->regmap_base), "Failed to init regmap\n");
+
+ sphy->phy = devm_phy_create(dev, NULL, &spacemit_usb2phy_ops);
+ if (IS_ERR(sphy->phy))
+ return dev_err_probe(dev, PTR_ERR(sphy->phy), "Failed to create phy\n");
+
+ phy_set_drvdata(sphy->phy, sphy);
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id spacemit_usb2phy_dt_match[] = {
+ { .compatible = "spacemit,k1-usb2-phy", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, spacemit_usb2phy_dt_match);
+
+static struct platform_driver spacemit_usb2_phy_driver = {
+ .probe = spacemit_usb2phy_probe,
+ .driver = {
+ .name = "spacemit-usb2-phy",
+ .of_match_table = spacemit_usb2phy_dt_match,
+ },
+};
+module_platform_driver(spacemit_usb2_phy_driver);
+
+MODULE_DESCRIPTION("Spacemit USB 2.0 PHY driver");
+MODULE_LICENSE("GPL");
--
2.53.0

20
SPECS/linux/0115-FROMLIST-regulator-spacemit-p1-Update-supply-names.patch → SPECS/linux/0021-UPSTREAM-regulator-spacemit-p1-Update-supply-names.patch
View File

@@ -1,18 +1,24 @@
From 6c887b90f92667d4f250f1be28fd525b33e91723 Mon Sep 17 00:00:00 2001
From 1163fb23ee05b37c3cbe62e97a3eff89f515fa73 Mon Sep 17 00:00:00 2001
From: Guodong Xu <guodong@riscstar.com>
Date: Sat, 24 Jan 2026 08:20:18 +0800
Subject: [PATCH 115/197] FROMLIST: regulator: spacemit-p1: Update supply names
Date: Fri, 6 Feb 2026 10:32:03 +0800
Subject: [PATCH 021/189] UPSTREAM: regulator: spacemit-p1: Update supply names
Update supply names to match the P1 PMIC's actual hardware pinout where
each buck has an individual VIN pin (vin1-vin6) and LDO groups have
dedicated input pins (aldoin, dldoin1, dldoin2).
The supply is a board design decision and should not be hardcoded to any
existing power source. This allows boards to specify their actual power
tree topology in devicetree.
This is an ABI change from the original "vin" and "buck5" supplies.
The P1/PMIC regulator has no consumers in the DTS tree yet. For the two
K1 boards in-tree (BPI-F3 and Jupiter), power settings come from
boot firmware, so a probe failure has minimal impact.
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Link: https://lore.kernel.org/r/20260124-spacemit-p1-v2-3-2c86b06694ba@riscstar.com
Link: https://developer.spacemit.com/documentation?token=T1Btw2BdiiSlSXkAdibcoMetnag
[1]
Reviewed-by: Alex Elder <elder@riscstar.com>
Link: https://patch.msgid.link/20260206-spacemit-p1-v4-2-8f695d93811e@riscstar.com
Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit fbb4c52ccdcb4a612d2b7f800aa57090eeee16d7)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/regulator/spacemit-p1.c | 25 ++++++++++++++-----------

19
SPECS/linux/0101-FROMLIST-mmc-sdhci-of-k1-add-reset-support.patch → SPECS/linux/0022-UPSTREAM-mmc-sdhci-of-k1-add-reset-support.patch
View File

@@ -1,21 +1,24 @@
From 273b296fe857b26f16c9ffbd5f52983bdd0b900d Mon Sep 17 00:00:00 2001
From 6be001be65836999146e3a718d76c5631c17af50 Mon Sep 17 00:00:00 2001
From: Yixun Lan <dlan@gentoo.org>
Date: Sun, 21 Dec 2025 16:20:27 +0800
Subject: [PATCH 101/197] FROMLIST: mmc: sdhci-of-k1: add reset support
Date: Tue, 23 Dec 2025 10:24:50 +0800
Subject: [PATCH 022/189] UPSTREAM: mmc: sdhci-of-k1: add reset support
The SDHCI controller of SpacemiT K1 SoC requires two resets, add
support to explicitly request the reset line and deassert during
initialization phase.
initialization phase. Still using devm_xx_get_optional() API to
make the request optional.
Signed-off-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20251221-07-k1-sdhci-reset-v1-2-6780af7fa6e7@gentoo.org
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit 658b716c048684ad13d78280d69b883f181251da)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/mmc/host/sdhci-of-k1.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c
index 0cc97e23a2f9..f8330cff5b2a 100644
index 0cc97e23a2f9..a160e1d5d9bd 100644
--- a/drivers/mmc/host/sdhci-of-k1.c
+++ b/drivers/mmc/host/sdhci-of-k1.c
@@ -15,6 +15,7 @@
@@ -34,11 +37,11 @@ index 0cc97e23a2f9..f8330cff5b2a 100644
+{
+ struct reset_control *rst;
+
+ rst = devm_reset_control_get_shared_deasserted(dev, "axi");
+ rst = devm_reset_control_get_optional_shared_deasserted(dev, "axi");
+ if (IS_ERR(rst))
+ return PTR_ERR(rst);
+
+ rst = devm_reset_control_get_exclusive_deasserted(dev, "sdh");
+ rst = devm_reset_control_get_optional_exclusive_deasserted(dev, "sdh");
+ if (IS_ERR(rst))
+ return PTR_ERR(rst);
+

45
SPECS/linux/0022-UPSTREAM-riscv-dts-spacemit-Add-USB2-PHY-node-for-K1.patch
View File

@@ -1,45 +0,0 @@
From b93126e2b5f3b4ab93dcdd166b783691b8aebf11 Mon Sep 17 00:00:00 2001
From: Ze Huang <huang.ze@linux.dev>
Date: Sun, 11 Jan 2026 14:41:02 +0800
Subject: [PATCH 022/197] UPSTREAM: riscv: dts: spacemit: Add USB2 PHY node for
K1
K1's DWC3 USB 3.0 controller requires two separate PHYs to function:
the USB 3.0 combophy (for SuperSpeed) and a USB 2.0 PHY (for High-Speed,
Full-Speed, etc.).
Add node for this second USB 2.0 PHY (usbphy2).
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Ze Huang <huang.ze@linux.dev>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20260111-k1-usb3dts-v2-v3-1-f5ebd546e904@linux.dev
Signed-off-by: Yixun Lan <dlan@gentoo.org>
(cherry picked from commit 9d591fef025d5008f23ab339a10006b151150578)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/spacemit/k1.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index 4c045da95d72..dfabda5ed4fa 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -429,6 +429,14 @@ i2c5: i2c@d4013800 {
status = "disabled";
};
+ usbphy2: phy@c0a30000 {
+ compatible = "spacemit,k1-usb2-phy";
+ reg = <0x0 0xc0a30000 0x0 0x200>;
+ clocks = <&syscon_apmu CLK_USB30>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
combo_phy: phy@c0b10000 {
compatible = "spacemit,k1-combo-phy";
reg = <0x0 0xc0b10000 0x0 0x1000>;
--
2.53.0

9
SPECS/linux/0117-FROMLIST-dt-bindings-mmc-spacemit-sdhci-add-support-.patch → SPECS/linux/0023-UPSTREAM-dt-bindings-mmc-spacemit-sdhci-add-support-.patch
View File

@@ -1,7 +1,7 @@
From 72c161c1472e8786d001c872241367dc9f93847f Mon Sep 17 00:00:00 2001
From 1dae82c5c652718953283584668bb1ec7ca35472 Mon Sep 17 00:00:00 2001
From: Yixun Lan <dlan@kernel.org>
Date: Thu, 22 Jan 2026 17:37:30 +0800
Subject: [PATCH 117/197] FROMLIST: dt-bindings: mmc: spacemit,sdhci: add
Subject: [PATCH 023/189] UPSTREAM: dt-bindings: mmc: spacemit,sdhci: add
support for K3 SoC
The SDHCI controller found on SpacemiT K3 SoC share the same IP with
@@ -10,14 +10,15 @@ compatible string to enable support for it.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260122-07-k3-mmc-v2-1-3c3ffef25e94@kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit b4206966e2d48883f04d5a2b2ae6c46b528245d3)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml
index 322c69b056f4..1081ea687702 100644
index 13d9382058fb..383841369fb2 100644
--- a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml
@@ -14,7 +14,9 @@ allOf:

59
SPECS/linux/0023-UPSTREAM-riscv-dts-spacemit-Add-DWC3-USB-3.0-control.patch
View File

@@ -1,59 +0,0 @@
From 9e429f8a8fb83d876c31a9137f46f8bbfaaa4e3f Mon Sep 17 00:00:00 2001
From: Ze Huang <huang.ze@linux.dev>
Date: Sun, 11 Jan 2026 14:41:03 +0800
Subject: [PATCH 023/197] UPSTREAM: riscv: dts: spacemit: Add DWC3 USB 3.0
controller node for K1
Add node for the Synopsys DWC3 USB 3.0 host controller on the K1 SoC.
The controller resides on the 'storage-bus' and uses its DMA
translations.
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Ze Huang <huang.ze@linux.dev>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20260111-k1-usb3dts-v2-v3-2-f5ebd546e904@linux.dev
Signed-off-by: Yixun Lan <dlan@gentoo.org>
(cherry picked from commit 6e8dcd141833a23d7117fe16896f6d5dfdb2e112)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/spacemit/k1.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index dfabda5ed4fa..137fc26ddc29 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -1170,6 +1170,30 @@ storage-bus {
#size-cells = <2>;
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
+ usb_dwc3: usb@c0a00000 {
+ compatible = "spacemit,k1-dwc3";
+ reg = <0x0 0xc0a00000 0x0 0x10000>;
+ clocks = <&syscon_apmu CLK_USB30>;
+ clock-names = "usbdrd30";
+ interrupts = <125>;
+ phys = <&usbphy2>, <&combo_phy PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi";
+ resets = <&syscon_apmu RESET_USB30_AHB>,
+ <&syscon_apmu RESET_USB30_VCC>,
+ <&syscon_apmu RESET_USB30_PHY>;
+ reset-names = "ahb", "vcc", "phy";
+ reset-delay = <2>;
+ snps,hsphy_interface = "utmi";
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,dis_rxdet_inp3_quirk;
+ status = "disabled";
+ };
+
emmc: mmc@d4281000 {
compatible = "spacemit,k1-sdhci";
reg = <0x0 0xd4281000 0x0 0x200>;
--
2.53.0

9
SPECS/linux/0118-FROMLIST-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch → SPECS/linux/0024-UPSTREAM-mmc-sdhci-of-k1-spacemit-Add-support-for-K3.patch
View File

@@ -1,7 +1,7 @@
From 8c899c26b451beb9891649f977c1b3ced32b4119 Mon Sep 17 00:00:00 2001
From 858d7d52fe9855677ea3ca901a9f07e14d776001 Mon Sep 17 00:00:00 2001
From: Yixun Lan <dlan@kernel.org>
Date: Thu, 22 Jan 2026 17:37:31 +0800
Subject: [PATCH 118/197] FROMLIST: mmc: sdhci-of-k1: spacemit: Add support for
Subject: [PATCH 024/189] UPSTREAM: mmc: sdhci-of-k1: spacemit: Add support for
K3 SoC
The SDHCI controller found on SpacemiT K3 SoC share the same IP with K1
@@ -9,14 +9,15 @@ generation and introduce a compatible data to denote the change that broken
64BIT DMA issue has been fixed.
Signed-off-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260122-07-k3-mmc-v2-2-3c3ffef25e94@kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit 1e9f43a1dbefd3de45b97545e5773d2b52dc7f02)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/mmc/host/sdhci-of-k1.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c
index f8330cff5b2a..ac623beabdeb 100644
index a160e1d5d9bd..455656f9842d 100644
--- a/drivers/mmc/host/sdhci-of-k1.c
+++ b/drivers/mmc/host/sdhci-of-k1.c
@@ -259,8 +259,20 @@ static const struct sdhci_pltfm_data spacemit_sdhci_k1_pdata = {

88
SPECS/linux/0024-UPSTREAM-riscv-dts-spacemit-Enable-USB3.0-on-BananaP.patch
View File

@@ -1,88 +0,0 @@
From 0d9cc73f214e3a8302b0aab23092df22dda6d69d Mon Sep 17 00:00:00 2001
From: Ze Huang <huang.ze@linux.dev>
Date: Sun, 11 Jan 2026 14:41:04 +0800
Subject: [PATCH 024/197] UPSTREAM: riscv: dts: spacemit: Enable USB3.0 on
BananaPi-F3
Enable the DWC3 USB 3.0 controller and its associated usbphy2 on the
Banana Pi F3 board.
The board utilizes a VLI VL817 hub, which requires two separate power
supplies: one VBUS and one for hub itself. Add two GPIO-controlled
fixed-regulators to manage this.
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Ze Huang <huang.ze@linux.dev>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20260111-k1-usb3dts-v2-v3-3-f5ebd546e904@linux.dev
Signed-off-by: Yixun Lan <dlan@gentoo.org>
(cherry picked from commit c7e62c4eea026d42d192a0b86ce7313086ef2093)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../boot/dts/spacemit/k1-bananapi-f3.dts | 46 +++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index 3f10efd925dc..5971605754b3 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -59,6 +59,25 @@ reg_vcc_4v: vcc-4v {
regulator-always-on;
vin-supply = <&reg_dc_in>;
};
+
+ usb3-vbus-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "USB30_VBUS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ usb3_hub_5v: usb3-hub-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "USB30_HUB";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
};
&combo_phy {
@@ -313,3 +332,30 @@ &uart0 {
pinctrl-0 = <&uart0_2_cfg>;
status = "okay";
};
+
+&usbphy2 {
+ status = "okay";
+};
+
+&usb_dwc3 {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ hub_2_0: hub@1 {
+ compatible = "usb2109,2817";
+ reg = <0x1>;
+ vdd-supply = <&usb3_hub_5v>;
+ peer-hub = <&hub_3_0>;
+ reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>;
+ };
+
+ hub_3_0: hub@2 {
+ compatible = "usb2109,817";
+ reg = <0x2>;
+ vdd-supply = <&usb3_hub_5v>;
+ peer-hub = <&hub_2_0>;
+ reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>;
+ };
+};
--
2.53.0

90
SPECS/linux/0025-UPSTREAM-PCI-cadence-Add-flags-for-disabling-ASPM-ca.patch Normal file
View File

@@ -0,0 +1,90 @@
From c17c6f71e4345878ab59b1339fb12ba92567d659 Mon Sep 17 00:00:00 2001
From: Yao Zi <me@ziyao.cc>
Date: Sun, 5 Apr 2026 15:41:53 +0000
Subject: [PATCH 025/189] UPSTREAM: PCI: cadence: Add flags for disabling ASPM
capability for broken Root Ports
Add flags for disabling the ASPM L0s/L1 capability for broken Root Ports
by clearing the corresponding bits in Link Capabilities Register through
the local management bus. This allows ASPM to be disabled on platforms
which don't support it.
Signed-off-by: Yao Zi <me@ziyao.cc>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Tested-by: Han Gao <gaohan@iscas.ac.cn>
Tested-by: Chen Wang <unicorn_wang@outlook.com> # Pioneerbox
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://patch.msgid.link/20260405154154.46829-2-me@ziyao.cc
(cherry picked from commit 5ccc76a87f1ec2422811e61be44165bfc9e7cf54)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../controller/cadence/pcie-cadence-host.c | 7 +++++++
drivers/pci/controller/cadence/pcie-cadence.h | 19 +++++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index db3154c1eccb..0bc9e6e90e0e 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -147,6 +147,13 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc)
cdns_pcie_rp_writeb(pcie, PCI_CLASS_PROG, 0);
cdns_pcie_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
+ value = cdns_pcie_rp_readl(pcie, CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP);
+ if (rc->quirk_broken_aspm_l0s)
+ value &= ~PCI_EXP_LNKCAP_ASPM_L0S;
+ if (rc->quirk_broken_aspm_l1)
+ value &= ~PCI_EXP_LNKCAP_ASPM_L1;
+ cdns_pcie_rp_writel(pcie, CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP, value);
+
return 0;
}
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index 443033c607d7..efbda0b3ec2c 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -115,6 +115,8 @@ struct cdns_pcie {
* @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk
* @ecam_supported: Whether the ECAM is supported
* @no_inbound_map: Whether inbound mapping is supported
+ * @quirk_broken_aspm_l0s: Disable ASPM L0s support as quirk
+ * @quirk_broken_aspm_l1: Disable ASPM L1 support as quirk
*/
struct cdns_pcie_rc {
struct cdns_pcie pcie;
@@ -127,6 +129,8 @@ struct cdns_pcie_rc {
unsigned int quirk_detect_quiet_flag:1;
unsigned int ecam_supported:1;
unsigned int no_inbound_map:1;
+ unsigned int quirk_broken_aspm_l0s:1;
+ unsigned int quirk_broken_aspm_l1:1;
};
/**
@@ -344,6 +348,21 @@ static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg)
return cdns_pcie_read_sz(addr, 0x2);
}
+static inline void cdns_pcie_rp_writel(struct cdns_pcie *pcie,
+ u32 reg, u32 value)
+{
+ void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
+
+ cdns_pcie_write_sz(addr, 0x4, value);
+}
+
+static inline u32 cdns_pcie_rp_readl(struct cdns_pcie *pcie, u32 reg)
+{
+ void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
+
+ return cdns_pcie_read_sz(addr, 0x4);
+}
+
static inline void cdns_pcie_hpa_rp_writeb(struct cdns_pcie *pcie,
u32 reg, u8 value)
{
--
2.53.0

44
SPECS/linux/0025-UPSTREAM-dt-bindings-pinctrl-spacemit-convert-drive-.patch
View File

@@ -1,44 +0,0 @@
From 6649b32e1161dad29cd240d0f45bc95cec3e7c37 Mon Sep 17 00:00:00 2001
From: Yixun Lan <dlan@gentoo.org>
Date: Fri, 2 Jan 2026 15:00:22 +0800
Subject: [PATCH 025/197] UPSTREAM: dt-bindings: pinctrl: spacemit: convert
drive strength to schema format
In order to better extend the pinctrl support for future new SoC, convert
drive strength setting from free form text to more standard schema format.
Signed-off-by: Yixun Lan <dlan@gentoo.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
(cherry picked from commit c3efac0592f88ab48c8eef028268e6514908be51)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../bindings/pinctrl/spacemit,k1-pinctrl.yaml | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml
index d80e88aa07b4..609d7db97822 100644
--- a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml
@@ -72,10 +72,14 @@ patternProperties:
enum: [ 0, 1 ]
drive-strength:
- description: |
- typical current when output high level.
- 1.8V output: 11, 21, 32, 42 (mA)
- 3.3V output: 7, 10, 13, 16, 19, 23, 26, 29 (mA)
+ description:
+ typical current (in mA) when the output at high level.
+ oneOf:
+ - enum: [ 11, 21, 32, 42 ]
+ description: For K1 SoC, 1.8V voltage output
+
+ - enum: [ 7, 10, 13, 16, 19, 23, 26, 29 ]
+ description: For K1 SoC, 3.3V voltage output
input-schmitt:
description: |
--
2.53.0

47
SPECS/linux/0026-UPSTREAM-PCI-sg2042-Avoid-L0s-and-L1-on-Sophgo-2042-.patch Normal file
View File

@@ -0,0 +1,47 @@
From 9f4b6ef64ed81b15766e5b3aec967826b6f9f560 Mon Sep 17 00:00:00 2001
From: Yao Zi <me@ziyao.cc>
Date: Sun, 5 Apr 2026 15:41:54 +0000
Subject: [PATCH 026/189] UPSTREAM: PCI: sg2042: Avoid L0s and L1 on Sophgo
2042 PCIe Root Ports
Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states
for devicetree platforms") force enables ASPM on all device tree platforms,
the SG2042 Root Ports are breaking as they advertise L0s and L1
capabilities without supporting them.
Set ASPM quirks to disable the L0s and L1 capabilities for the Root Ports
so that these broken link states won't be enabled.
Fixes: 4e27aca4881a ("riscv: sophgo: dts: add PCIe controllers for SG2042")
Co-developed-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Yao Zi <me@ziyao.cc>
[mani: commit log]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Tested-by: Han Gao <gaohan@iscas.ac.cn>
Tested-by: Chen Wang <unicorn_wang@outlook.com> # Pioneerbox
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://patch.msgid.link/20260405154154.46829-3-me@ziyao.cc
(cherry picked from commit 988ef706cdd8a72e61dd90c0d0554eec4df7594a)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/pci/controller/cadence/pcie-sg2042.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c
index 0c50c74d03ee..4a2af4d0713e 100644
--- a/drivers/pci/controller/cadence/pcie-sg2042.c
+++ b/drivers/pci/controller/cadence/pcie-sg2042.c
@@ -48,6 +48,8 @@ static int sg2042_pcie_probe(struct platform_device *pdev)
bridge->child_ops = &sg2042_pcie_child_ops;
rc = pci_host_bridge_priv(bridge);
+ rc->quirk_broken_aspm_l0s = 1;
+ rc->quirk_broken_aspm_l1 = 1;
pcie = &rc->pcie;
pcie->dev = dev;
--
2.53.0

51
SPECS/linux/0026-UPSTREAM-dt-bindings-pinctrl-spacemit-add-K3-SoC-sup.patch
View File

@@ -1,51 +0,0 @@
From 8d6f91d5e278213a2b364644b5e688c628b6a153 Mon Sep 17 00:00:00 2001
From: Yixun Lan <dlan@gentoo.org>
Date: Fri, 2 Jan 2026 15:00:23 +0800
Subject: [PATCH 026/197] UPSTREAM: dt-bindings: pinctrl: spacemit: add K3 SoC
support
Add new compatible string for SpacemiT K3 SoC, the pinctrl IP shares
almost same logic with previous K1 generation, but has different register
offset and pin configuration, for example the drive strength and
schmitter trigger settings has been changed.
Signed-off-by: Yixun Lan <dlan@gentoo.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
(cherry picked from commit 5adaa1a8c08839617e5a6385fe05a8baa63e355f)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../bindings/pinctrl/spacemit,k1-pinctrl.yaml | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml
index 609d7db97822..9a76cffcbaee 100644
--- a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml
@@ -11,7 +11,9 @@ maintainers:
properties:
compatible:
- const: spacemit,k1-pinctrl
+ enum:
+ - spacemit,k1-pinctrl
+ - spacemit,k3-pinctrl
reg:
items:
@@ -81,6 +83,12 @@ patternProperties:
- enum: [ 7, 10, 13, 16, 19, 23, 26, 29 ]
description: For K1 SoC, 3.3V voltage output
+ - enum: [ 2, 4, 6, 7, 9, 11, 13, 14, 21, 23, 25, 26, 28, 30, 31, 33 ]
+ description: For K3 SoC, 1.8V voltage output
+
+ - enum: [ 3, 5, 7, 9, 11, 13, 15, 17, 25, 27, 29, 31, 33, 35, 37, 38 ]
+ description: For K3 SoC, 1.8V voltage output
+
input-schmitt:
description: |
typical threshold for schmitt trigger.
--
2.53.0

7
SPECS/linux/0155-FROMLIST-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch → SPECS/linux/0027-UPSTREAM-dt-bindings-hwmon-moortec-mr75203-adapt-mul.patch
View File

@@ -1,7 +1,7 @@
From 5e60ace586f2aaf5b45b6ee70a6178daed7bdabd Mon Sep 17 00:00:00 2001
From 14f66de8b55d16c248186c60646e0e99175dace6 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Date: Tue, 10 Mar 2026 00:24:56 +0800
Subject: [PATCH 155/197] FROMLIST: dt-bindings: hwmon: moortec,mr75203: adapt
Subject: [PATCH 027/189] UPSTREAM: dt-bindings: hwmon: moortec,mr75203: adapt
multipleOf for T-Head TH1520
The G and J coefficients provided by T-Head TH1520 manual (which calls
@@ -15,7 +15,10 @@ of milli-Celsius) to satisfy the need of TH1520.
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20260309162457.4128205-2-zhengxingda@iscas.ac.cn
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
(cherry picked from commit 967ee29c103a44c6e584a5e37401968a69e54a0c)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
Documentation/devicetree/bindings/hwmon/moortec,mr75203.yaml | 4 ++--

449
SPECS/linux/0027-UPSTREAM-pinctrl-spacemit-k3-add-initial-pin-support.patch
View File

@@ -1,449 +0,0 @@
From d14f109a1a164e63287c9bfd42c7e94b4f8b1544 Mon Sep 17 00:00:00 2001
From: Yixun Lan <dlan@gentoo.org>
Date: Fri, 2 Jan 2026 15:00:24 +0800
Subject: [PATCH 027/197] UPSTREAM: pinctrl: spacemit: k3: add initial pin
support
For the pinctrl IP of SpacemiT's K3 SoC, it has different register offset
comparing with previous SoC generation, so introduce a function to do the
pin to offset mapping. Also add all the pinctrl data.
Signed-off-by: Yixun Lan <dlan@gentoo.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>
(cherry picked from commit 7412311c4655497b6ab6dd7b802f9390f0f57dc7)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/pinctrl/spacemit/Kconfig | 4 +-
drivers/pinctrl/spacemit/pinctrl-k1.c | 354 +++++++++++++++++++++++++-
2 files changed, 352 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/spacemit/Kconfig b/drivers/pinctrl/spacemit/Kconfig
index d6f6017fd097..c021d51033d1 100644
--- a/drivers/pinctrl/spacemit/Kconfig
+++ b/drivers/pinctrl/spacemit/Kconfig
@@ -4,7 +4,7 @@
#
config PINCTRL_SPACEMIT_K1
- bool "SpacemiT K1 SoC Pinctrl driver"
+ bool "SpacemiT K1/K3 SoC Pinctrl driver"
depends on ARCH_SPACEMIT || COMPILE_TEST
depends on OF
default ARCH_SPACEMIT
@@ -12,7 +12,7 @@ config PINCTRL_SPACEMIT_K1
select GENERIC_PINMUX_FUNCTIONS
select GENERIC_PINCONF
help
- Say Y to select the pinctrl driver for K1 SoC.
+ Say Y to select the pinctrl driver for K1/K3 SoC.
This pin controller allows selecting the mux function for
each pin. This driver can also be built as a module called
pinctrl-k1.
diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c
index 33af9b5791c1..441817f539e3 100644
--- a/drivers/pinctrl/spacemit/pinctrl-k1.c
+++ b/drivers/pinctrl/spacemit/pinctrl-k1.c
@@ -66,6 +66,7 @@ struct spacemit_pinctrl_data {
const struct pinctrl_pin_desc *pins;
const struct spacemit_pin *data;
u16 npins;
+ unsigned int (*pin_to_offset)(unsigned int pin);
};
struct spacemit_pin_mux_config {
@@ -79,7 +80,7 @@ struct spacemit_pin_drv_strength {
};
/* map pin id to pinctrl register offset, refer MFPR definition */
-static unsigned int spacemit_pin_to_offset(unsigned int pin)
+static unsigned int spacemit_k1_pin_to_offset(unsigned int pin)
{
unsigned int offset = 0;
@@ -124,10 +125,17 @@ static unsigned int spacemit_pin_to_offset(unsigned int pin)
return offset << 2;
}
+static unsigned int spacemit_k3_pin_to_offset(unsigned int pin)
+{
+ unsigned int offset = pin > 130 ? (pin + 2) : pin;
+
+ return offset << 2;
+}
+
static inline void __iomem *spacemit_pin_to_reg(struct spacemit_pinctrl *pctrl,
unsigned int pin)
{
- return pctrl->regs + spacemit_pin_to_offset(pin);
+ return pctrl->regs + pctrl->data->pin_to_offset(pin);
}
static u16 spacemit_dt_get_pin(u32 value)
@@ -177,7 +185,7 @@ static void spacemit_pctrl_dbg_show(struct pinctrl_dev *pctldev,
void __iomem *reg;
u32 value;
- seq_printf(seq, "offset: 0x%04x ", spacemit_pin_to_offset(pin));
+ seq_printf(seq, "offset: 0x%04x ", pctrl->data->pin_to_offset(pin));
seq_printf(seq, "type: %s ", io_type_desc[type]);
reg = spacemit_pin_to_reg(pctrl, pin);
@@ -1042,10 +1050,348 @@ static const struct spacemit_pinctrl_data k1_pinctrl_data = {
.pins = k1_pin_desc,
.data = k1_pin_data,
.npins = ARRAY_SIZE(k1_pin_desc),
+ .pin_to_offset = spacemit_k1_pin_to_offset,
+};
+
+static const struct pinctrl_pin_desc k3_pin_desc[] = {
+ PINCTRL_PIN(0, "GPIO_00"),
+ PINCTRL_PIN(1, "GPIO_01"),
+ PINCTRL_PIN(2, "GPIO_02"),
+ PINCTRL_PIN(3, "GPIO_03"),
+ PINCTRL_PIN(4, "GPIO_04"),
+ PINCTRL_PIN(5, "GPIO_05"),
+ PINCTRL_PIN(6, "GPIO_06"),
+ PINCTRL_PIN(7, "GPIO_07"),
+ PINCTRL_PIN(8, "GPIO_08"),
+ PINCTRL_PIN(9, "GPIO_09"),
+ PINCTRL_PIN(10, "GPIO_10"),
+ PINCTRL_PIN(11, "GPIO_11"),
+ PINCTRL_PIN(12, "GPIO_12"),
+ PINCTRL_PIN(13, "GPIO_13"),
+ PINCTRL_PIN(14, "GPIO_14"),
+ PINCTRL_PIN(15, "GPIO_15"),
+ PINCTRL_PIN(16, "GPIO_16"),
+ PINCTRL_PIN(17, "GPIO_17"),
+ PINCTRL_PIN(18, "GPIO_18"),
+ PINCTRL_PIN(19, "GPIO_19"),
+ PINCTRL_PIN(20, "GPIO_20"),
+ PINCTRL_PIN(21, "GPIO_21"),
+ PINCTRL_PIN(22, "GPIO_22"),
+ PINCTRL_PIN(23, "GPIO_23"),
+ PINCTRL_PIN(24, "GPIO_24"),
+ PINCTRL_PIN(25, "GPIO_25"),
+ PINCTRL_PIN(26, "GPIO_26"),
+ PINCTRL_PIN(27, "GPIO_27"),
+ PINCTRL_PIN(28, "GPIO_28"),
+ PINCTRL_PIN(29, "GPIO_29"),
+ PINCTRL_PIN(30, "GPIO_30"),
+ PINCTRL_PIN(31, "GPIO_31"),
+ PINCTRL_PIN(32, "GPIO_32"),
+ PINCTRL_PIN(33, "GPIO_33"),
+ PINCTRL_PIN(34, "GPIO_34"),
+ PINCTRL_PIN(35, "GPIO_35"),
+ PINCTRL_PIN(36, "GPIO_36"),
+ PINCTRL_PIN(37, "GPIO_37"),
+ PINCTRL_PIN(38, "GPIO_38"),
+ PINCTRL_PIN(39, "GPIO_39"),
+ PINCTRL_PIN(40, "GPIO_40"),
+ PINCTRL_PIN(41, "GPIO_41"),
+ PINCTRL_PIN(42, "GPIO_42"),
+ PINCTRL_PIN(43, "GPIO_43"),
+ PINCTRL_PIN(44, "GPIO_44"),
+ PINCTRL_PIN(45, "GPIO_45"),
+ PINCTRL_PIN(46, "GPIO_46"),
+ PINCTRL_PIN(47, "GPIO_47"),
+ PINCTRL_PIN(48, "GPIO_48"),
+ PINCTRL_PIN(49, "GPIO_49"),
+ PINCTRL_PIN(50, "GPIO_50"),
+ PINCTRL_PIN(51, "GPIO_51"),
+ PINCTRL_PIN(52, "GPIO_52"),
+ PINCTRL_PIN(53, "GPIO_53"),
+ PINCTRL_PIN(54, "GPIO_54"),
+ PINCTRL_PIN(55, "GPIO_55"),
+ PINCTRL_PIN(56, "GPIO_56"),
+ PINCTRL_PIN(57, "GPIO_57"),
+ PINCTRL_PIN(58, "GPIO_58"),
+ PINCTRL_PIN(59, "GPIO_59"),
+ PINCTRL_PIN(60, "GPIO_60"),
+ PINCTRL_PIN(61, "GPIO_61"),
+ PINCTRL_PIN(62, "GPIO_62"),
+ PINCTRL_PIN(63, "GPIO_63"),
+ PINCTRL_PIN(64, "GPIO_64"),
+ PINCTRL_PIN(65, "GPIO_65"),
+ PINCTRL_PIN(66, "GPIO_66"),
+ PINCTRL_PIN(67, "GPIO_67"),
+ PINCTRL_PIN(68, "GPIO_68"),
+ PINCTRL_PIN(69, "GPIO_69"),
+ PINCTRL_PIN(70, "GPIO_70"),
+ PINCTRL_PIN(71, "GPIO_71"),
+ PINCTRL_PIN(72, "GPIO_72"),
+ PINCTRL_PIN(73, "GPIO_73"),
+ PINCTRL_PIN(74, "GPIO_74"),
+ PINCTRL_PIN(75, "GPIO_75"),
+ PINCTRL_PIN(76, "GPIO_76"),
+ PINCTRL_PIN(77, "GPIO_77"),
+ PINCTRL_PIN(78, "GPIO_78"),
+ PINCTRL_PIN(79, "GPIO_79"),
+ PINCTRL_PIN(80, "GPIO_80"),
+ PINCTRL_PIN(81, "GPIO_81"),
+ PINCTRL_PIN(82, "GPIO_82"),
+ PINCTRL_PIN(83, "GPIO_83"),
+ PINCTRL_PIN(84, "GPIO_84"),
+ PINCTRL_PIN(85, "GPIO_85"),
+ PINCTRL_PIN(86, "GPIO_86"),
+ PINCTRL_PIN(87, "GPIO_87"),
+ PINCTRL_PIN(88, "GPIO_88"),
+ PINCTRL_PIN(89, "GPIO_89"),
+ PINCTRL_PIN(90, "GPIO_90"),
+ PINCTRL_PIN(91, "GPIO_91"),
+ PINCTRL_PIN(92, "GPIO_92"),
+ PINCTRL_PIN(93, "GPIO_93"),
+ PINCTRL_PIN(94, "GPIO_94"),
+ PINCTRL_PIN(95, "GPIO_95"),
+ PINCTRL_PIN(96, "GPIO_96"),
+ PINCTRL_PIN(97, "GPIO_97"),
+ PINCTRL_PIN(98, "GPIO_98"),
+ PINCTRL_PIN(99, "GPIO_99"),
+ PINCTRL_PIN(100, "GPIO_100"),
+ PINCTRL_PIN(101, "GPIO_101"),
+ PINCTRL_PIN(102, "GPIO_102"),
+ PINCTRL_PIN(103, "GPIO_103"),
+ PINCTRL_PIN(104, "GPIO_104"),
+ PINCTRL_PIN(105, "GPIO_105"),
+ PINCTRL_PIN(106, "GPIO_106"),
+ PINCTRL_PIN(107, "GPIO_107"),
+ PINCTRL_PIN(108, "GPIO_108"),
+ PINCTRL_PIN(109, "GPIO_109"),
+ PINCTRL_PIN(110, "GPIO_110"),
+ PINCTRL_PIN(111, "GPIO_111"),
+ PINCTRL_PIN(112, "GPIO_112"),
+ PINCTRL_PIN(113, "GPIO_113"),
+ PINCTRL_PIN(114, "GPIO_114"),
+ PINCTRL_PIN(115, "GPIO_115"),
+ PINCTRL_PIN(116, "GPIO_116"),
+ PINCTRL_PIN(117, "GPIO_117"),
+ PINCTRL_PIN(118, "GPIO_118"),
+ PINCTRL_PIN(119, "GPIO_119"),
+ PINCTRL_PIN(120, "GPIO_120"),
+ PINCTRL_PIN(121, "GPIO_121"),
+ PINCTRL_PIN(122, "GPIO_122"),
+ PINCTRL_PIN(123, "GPIO_123"),
+ PINCTRL_PIN(124, "GPIO_124"),
+ PINCTRL_PIN(125, "GPIO_125"),
+ PINCTRL_PIN(126, "GPIO_126"),
+ PINCTRL_PIN(127, "GPIO_127"),
+ PINCTRL_PIN(128, "PWR_SCL"),
+ PINCTRL_PIN(129, "PWR_SDA"),
+ PINCTRL_PIN(130, "VCXO_EN"),
+ PINCTRL_PIN(131, "PMIC_INT_N"),
+ PINCTRL_PIN(132, "MMC1_DAT3"),
+ PINCTRL_PIN(133, "MMC1_DAT2"),
+ PINCTRL_PIN(134, "MMC1_DAT1"),
+ PINCTRL_PIN(135, "MMC1_DAT0"),
+ PINCTRL_PIN(136, "MMC1_CMD"),
+ PINCTRL_PIN(137, "MMC1_CLK"),
+ PINCTRL_PIN(138, "QSPI_DAT0"),
+ PINCTRL_PIN(139, "QSPI_DAT1"),
+ PINCTRL_PIN(140, "QSPI_DAT2"),
+ PINCTRL_PIN(141, "QSPI_DAT3"),
+ PINCTRL_PIN(142, "QSPI_CS0"),
+ PINCTRL_PIN(143, "QSPI_CS1"),
+ PINCTRL_PIN(144, "QSPI_CLK"),
+ PINCTRL_PIN(145, "PRI_TDI"),
+ PINCTRL_PIN(146, "PRI_TMS"),
+ PINCTRL_PIN(147, "PRI_TCK"),
+ PINCTRL_PIN(148, "PRI_TDO"),
+ PINCTRL_PIN(149, "PWR_SSP_SCLK"),
+ PINCTRL_PIN(150, "PWR_SSP_FRM"),
+ PINCTRL_PIN(151, "PWR_SSP_TXD"),
+ PINCTRL_PIN(152, "PWR_SSP_RXD"),
+};
+
+static const struct spacemit_pin k3_pin_data[ARRAY_SIZE(k3_pin_desc)] = {
+ /* GPIO1 bank */
+ K1_FUNC_PIN(0, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(1, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(2, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(3, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(4, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(5, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(6, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(7, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(8, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(9, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(10, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(11, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(12, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(13, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(14, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(15, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(16, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(17, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(18, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(19, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(20, 0, IO_TYPE_EXTERNAL),
+
+ /* GPIO2 bank */
+ K1_FUNC_PIN(21, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(22, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(23, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(24, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(25, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(26, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(27, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(28, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(29, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(30, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(31, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(32, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(33, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(34, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(35, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(36, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(37, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(38, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(39, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(40, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(41, 0, IO_TYPE_EXTERNAL),
+
+ /* GPIO3 bank */
+ K1_FUNC_PIN(42, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(43, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(44, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(45, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(46, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(47, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(48, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(49, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(50, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(51, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(52, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(53, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(54, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(55, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(56, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(57, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(58, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(59, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(60, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(61, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(62, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(63, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(64, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(65, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(66, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(67, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(68, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(69, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(70, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(71, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(72, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(73, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(74, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(75, 0, IO_TYPE_1V8),
+
+ /* GPIO4 bank */
+ K1_FUNC_PIN(76, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(77, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(78, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(79, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(80, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(81, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(82, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(83, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(84, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(85, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(86, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(87, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(88, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(89, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(90, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(91, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(92, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(93, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(94, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(95, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(96, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(97, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(98, 0, IO_TYPE_EXTERNAL),
+
+ /* GPIO5 bank */
+ K1_FUNC_PIN(99, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(100, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(101, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(102, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(103, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(104, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(105, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(106, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(107, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(108, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(109, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(110, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(111, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(112, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(113, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(114, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(115, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(116, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(117, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(118, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(119, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(120, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(121, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(122, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(123, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(124, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(125, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(126, 0, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(127, 0, IO_TYPE_EXTERNAL),
+
+ /* PMIC */
+ K1_FUNC_PIN(128, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(129, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(130, 0, IO_TYPE_1V8),
+ K1_FUNC_PIN(131, 0, IO_TYPE_1V8),
+
+ /* SD/MMC1 */
+ K1_FUNC_PIN(132, 1, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(133, 1, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(134, 1, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(135, 1, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(136, 1, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(137, 1, IO_TYPE_EXTERNAL),
+
+ /* QSPI */
+ K1_FUNC_PIN(138, 1, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(139, 1, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(140, 1, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(141, 1, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(142, 1, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(143, 1, IO_TYPE_EXTERNAL),
+ K1_FUNC_PIN(144, 1, IO_TYPE_EXTERNAL),
+
+ /* PMIC */
+ K1_FUNC_PIN(145, 1, IO_TYPE_1V8),
+ K1_FUNC_PIN(146, 1, IO_TYPE_1V8),
+ K1_FUNC_PIN(147, 1, IO_TYPE_1V8),
+ K1_FUNC_PIN(148, 1, IO_TYPE_1V8),
+ K1_FUNC_PIN(149, 1, IO_TYPE_1V8),
+ K1_FUNC_PIN(150, 1, IO_TYPE_1V8),
+ K1_FUNC_PIN(151, 1, IO_TYPE_1V8),
+ K1_FUNC_PIN(152, 1, IO_TYPE_1V8),
+};
+
+static const struct spacemit_pinctrl_data k3_pinctrl_data = {
+ .pins = k3_pin_desc,
+ .data = k3_pin_data,
+ .npins = ARRAY_SIZE(k3_pin_desc),
+ .pin_to_offset = spacemit_k3_pin_to_offset,
};
static const struct of_device_id k1_pinctrl_ids[] = {
{ .compatible = "spacemit,k1-pinctrl", .data = &k1_pinctrl_data },
+ { .compatible = "spacemit,k3-pinctrl", .data = &k3_pinctrl_data },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, k1_pinctrl_ids);
@@ -1061,5 +1407,5 @@ static struct platform_driver k1_pinctrl_driver = {
builtin_platform_driver(k1_pinctrl_driver);
MODULE_AUTHOR("Yixun Lan <dlan@gentoo.org>");
-MODULE_DESCRIPTION("Pinctrl driver for the SpacemiT K1 SoC");
+MODULE_DESCRIPTION("Pinctrl driver for the SpacemiT K1/K3 SoC");
MODULE_LICENSE("GPL");
--
2.53.0

325
SPECS/linux/0028-UPSTREAM-pinctrl-spacemit-k3-adjust-drive-strength-a.patch
View File

@@ -1,325 +0,0 @@
From ae030b4194eae8cc25f7290ebd1d7b1aa7791a2e Mon Sep 17 00:00:00 2001
From: Yixun Lan <dlan@gentoo.org>
Date: Fri, 2 Jan 2026 15:00:25 +0800
Subject: [PATCH 028/197] UPSTREAM: pinctrl: spacemit: k3: adjust drive
strength and schmitter trigger
K3 SoC expand drive strength to 4 bits which support even larger
settings table comparing to old SoC generation. Also schmitter trigger
setting is changed to 1 bit.
Signed-off-by: Yixun Lan <dlan@gentoo.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>
(cherry picked from commit 3f20bdf7151834547a85231c28538f49601481ee)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/pinctrl/spacemit/pinctrl-k1.c | 163 ++++++++++++++++++--------
1 file changed, 116 insertions(+), 47 deletions(-)
diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c
index 441817f539e3..07267c5f0f44 100644
--- a/drivers/pinctrl/spacemit/pinctrl-k1.c
+++ b/drivers/pinctrl/spacemit/pinctrl-k1.c
@@ -24,11 +24,12 @@
#include "pinctrl-k1.h"
/*
- * +---------+----------+-----------+--------+--------+----------+--------+
- * | pull | drive | schmitter | slew | edge | strong | mux |
- * | up/down | strength | trigger | rate | detect | pull | mode |
- * +---------+----------+-----------+--------+--------+----------+--------+
- * 3 bits 3 bits 2 bits 1 bit 3 bits 1 bit 3 bits
+ * | pull | drive | schmitter | slew | edge | strong | mux |
+ * SoC | up/down | strength | trigger | rate | detect | pull | mode |
+ *-----+---------+----------+-----------+-------+--------+--------+--------+
+ * K1 | 3 bits | 3 bits | 2 bits | 1 bit | 3 bits | 1 bit | 3 bits |
+ *-----+---------+----------+-----------+-------+--------+--------+--------+
+ * K3 | 3 bits | 4 bits | 1 bits | 1 bit | 3 bits | 1 bit | 3 bits |
*/
#define PAD_MUX GENMASK(2, 0)
@@ -38,12 +39,29 @@
#define PAD_EDGE_CLEAR BIT(6)
#define PAD_SLEW_RATE GENMASK(12, 11)
#define PAD_SLEW_RATE_EN BIT(7)
-#define PAD_SCHMITT GENMASK(9, 8)
-#define PAD_DRIVE GENMASK(12, 10)
+#define PAD_SCHMITT_K1 GENMASK(9, 8)
+#define PAD_DRIVE_K1 GENMASK(12, 10)
+#define PAD_SCHMITT_K3 BIT(8)
+#define PAD_DRIVE_K3 GENMASK(12, 9)
#define PAD_PULLDOWN BIT(13)
#define PAD_PULLUP BIT(14)
#define PAD_PULL_EN BIT(15)
+struct spacemit_pin_drv_strength {
+ u8 val;
+ u32 mA;
+};
+
+struct spacemit_pinctrl_dconf {
+ u64 schmitt_mask;
+ u64 drive_mask;
+
+ struct spacemit_pin_drv_strength *ds_1v8_tbl;
+ size_t ds_1v8_tbl_num;
+ struct spacemit_pin_drv_strength *ds_3v3_tbl;
+ size_t ds_3v3_tbl_num;
+};
+
struct spacemit_pin {
u16 pin;
u16 flags;
@@ -67,6 +85,7 @@ struct spacemit_pinctrl_data {
const struct spacemit_pin *data;
u16 npins;
unsigned int (*pin_to_offset)(unsigned int pin);
+ const struct spacemit_pinctrl_dconf *dconf;
};
struct spacemit_pin_mux_config {
@@ -74,11 +93,6 @@ struct spacemit_pin_mux_config {
u32 config;
};
-struct spacemit_pin_drv_strength {
- u8 val;
- u32 mA;
-};
-
/* map pin id to pinctrl register offset, refer MFPR definition */
static unsigned int spacemit_k1_pin_to_offset(unsigned int pin)
{
@@ -193,23 +207,70 @@ static void spacemit_pctrl_dbg_show(struct pinctrl_dev *pctldev,
seq_printf(seq, "mux: %ld reg: 0x%04x", (value & PAD_MUX), value);
}
-/* use IO high level output current as the table */
-static struct spacemit_pin_drv_strength spacemit_ds_1v8_tbl[4] = {
- { 0, 11 },
- { 2, 21 },
- { 4, 32 },
- { 6, 42 },
+static const struct spacemit_pinctrl_dconf k1_drive_conf = {
+ .drive_mask = PAD_DRIVE_K1,
+ .schmitt_mask = PAD_SCHMITT_K1,
+ .ds_1v8_tbl = (struct spacemit_pin_drv_strength[]) {
+ { 0, 11 },
+ { 2, 21 },
+ { 4, 32 },
+ { 6, 42 },
+ },
+ .ds_1v8_tbl_num = 4,
+ .ds_3v3_tbl = (struct spacemit_pin_drv_strength[]) {
+ { 0, 7 },
+ { 2, 10 },
+ { 4, 13 },
+ { 6, 16 },
+ { 1, 19 },
+ { 3, 23 },
+ { 5, 26 },
+ { 7, 29 },
+ },
+ .ds_3v3_tbl_num = 8,
};
-static struct spacemit_pin_drv_strength spacemit_ds_3v3_tbl[8] = {
- { 0, 7 },
- { 2, 10 },
- { 4, 13 },
- { 6, 16 },
- { 1, 19 },
- { 3, 23 },
- { 5, 26 },
- { 7, 29 },
+static const struct spacemit_pinctrl_dconf k3_drive_conf = {
+ .drive_mask = PAD_DRIVE_K3,
+ .schmitt_mask = PAD_SCHMITT_K3,
+ .ds_1v8_tbl = (struct spacemit_pin_drv_strength[]) {
+ { 0, 2 },
+ { 1, 4 },
+ { 2, 6 },
+ { 3, 7 },
+ { 4, 9 },
+ { 5, 11 },
+ { 6, 13 },
+ { 7, 14 },
+ { 8, 21 },
+ { 9, 23 },
+ { 10, 25 },
+ { 11, 26 },
+ { 12, 28 },
+ { 13, 30 },
+ { 14, 31 },
+ { 15, 33 },
+ },
+ .ds_1v8_tbl_num = 16,
+ .ds_3v3_tbl = (struct spacemit_pin_drv_strength[]) {
+ { 0, 3 },
+ { 1, 5 },
+ { 2, 7 },
+ { 3, 9 },
+ { 4, 11 },
+ { 5, 13 },
+ { 6, 15 },
+ { 7, 17 },
+ { 8, 25 },
+ { 9, 27 },
+ { 10, 29 },
+ { 11, 31 },
+ { 12, 33 },
+ { 13, 35 },
+ { 14, 37 },
+ { 15, 38 },
+ },
+ .ds_3v3_tbl_num = 16,
};
static inline u8 spacemit_get_ds_value(struct spacemit_pin_drv_strength *tbl,
@@ -237,16 +298,17 @@ static inline u32 spacemit_get_ds_mA(struct spacemit_pin_drv_strength *tbl,
}
static inline u8 spacemit_get_driver_strength(enum spacemit_pin_io_type type,
+ const struct spacemit_pinctrl_dconf *dconf,
u32 mA)
{
switch (type) {
case IO_TYPE_1V8:
- return spacemit_get_ds_value(spacemit_ds_1v8_tbl,
- ARRAY_SIZE(spacemit_ds_1v8_tbl),
+ return spacemit_get_ds_value(dconf->ds_1v8_tbl,
+ dconf->ds_1v8_tbl_num,
mA);
case IO_TYPE_3V3:
- return spacemit_get_ds_value(spacemit_ds_3v3_tbl,
- ARRAY_SIZE(spacemit_ds_3v3_tbl),
+ return spacemit_get_ds_value(dconf->ds_3v3_tbl,
+ dconf->ds_3v3_tbl_num,
mA);
default:
return 0;
@@ -254,16 +316,17 @@ static inline u8 spacemit_get_driver_strength(enum spacemit_pin_io_type type,
}
static inline u32 spacemit_get_drive_strength_mA(enum spacemit_pin_io_type type,
+ const struct spacemit_pinctrl_dconf *dconf,
u32 value)
{
switch (type) {
case IO_TYPE_1V8:
- return spacemit_get_ds_mA(spacemit_ds_1v8_tbl,
- ARRAY_SIZE(spacemit_ds_1v8_tbl),
- value & 0x6);
+ return spacemit_get_ds_mA(dconf->ds_1v8_tbl,
+ dconf->ds_1v8_tbl_num,
+ value);
case IO_TYPE_3V3:
- return spacemit_get_ds_mA(spacemit_ds_3v3_tbl,
- ARRAY_SIZE(spacemit_ds_3v3_tbl),
+ return spacemit_get_ds_mA(dconf->ds_3v3_tbl,
+ dconf->ds_3v3_tbl_num,
value);
default:
return 0;
@@ -510,6 +573,7 @@ static int spacemit_pinconf_get(struct pinctrl_dev *pctldev,
#define ENABLE_DRV_STRENGTH BIT(1)
#define ENABLE_SLEW_RATE BIT(2)
static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin,
+ const struct spacemit_pinctrl_dconf *dconf,
unsigned long *configs,
unsigned int num_configs,
u32 *value)
@@ -547,8 +611,8 @@ static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin,
drv_strength = arg;
break;
case PIN_CONFIG_INPUT_SCHMITT:
- v &= ~PAD_SCHMITT;
- v |= FIELD_PREP(PAD_SCHMITT, arg);
+ v &= ~dconf->schmitt_mask;
+ v |= (arg << __ffs(dconf->schmitt_mask)) & dconf->schmitt_mask;
break;
case PIN_CONFIG_POWER_SOURCE:
voltage = arg;
@@ -584,10 +648,10 @@ static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin,
}
}
- val = spacemit_get_driver_strength(type, drv_strength);
+ val = spacemit_get_driver_strength(type, dconf, drv_strength);
- v &= ~PAD_DRIVE;
- v |= FIELD_PREP(PAD_DRIVE, val);
+ v &= ~dconf->drive_mask;
+ v |= (val << __ffs(dconf->drive_mask)) & dconf->drive_mask;
}
if (flag & ENABLE_SLEW_RATE) {
@@ -637,7 +701,8 @@ static int spacemit_pinconf_set(struct pinctrl_dev *pctldev,
const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin);
u32 value;
- if (spacemit_pinconf_generate_config(spin, configs, num_configs, &value))
+ if (spacemit_pinconf_generate_config(spin, pctrl->data->dconf,
+ configs, num_configs, &value))
return -EINVAL;
return spacemit_pin_set_config(pctrl, pin, value);
@@ -659,7 +724,8 @@ static int spacemit_pinconf_group_set(struct pinctrl_dev *pctldev,
return -EINVAL;
spin = spacemit_get_pin(pctrl, group->grp.pins[0]);
- if (spacemit_pinconf_generate_config(spin, configs, num_configs, &value))
+ if (spacemit_pinconf_generate_config(spin, pctrl->data->dconf,
+ configs, num_configs, &value))
return -EINVAL;
for (i = 0; i < group->grp.npins; i++)
@@ -693,6 +759,7 @@ static void spacemit_pinconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *seq, unsigned int pin)
{
struct spacemit_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+ const struct spacemit_pinctrl_dconf *dconf = pctrl->data->dconf;
const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin);
enum spacemit_pin_io_type type = spacemit_to_pin_io_type(spin);
void __iomem *reg = spacemit_pin_to_reg(pctrl, pin);
@@ -703,17 +770,17 @@ static void spacemit_pinconf_dbg_show(struct pinctrl_dev *pctldev,
seq_printf(seq, ", io type (%s)", io_type_desc[type]);
- tmp = FIELD_GET(PAD_DRIVE, value);
+ tmp = (value & dconf->drive_mask) >> __ffs(dconf->drive_mask);
if (type == IO_TYPE_1V8 || type == IO_TYPE_3V3) {
- mA = spacemit_get_drive_strength_mA(type, tmp);
+ mA = spacemit_get_drive_strength_mA(type, dconf, tmp);
seq_printf(seq, ", drive strength (%d mA)", mA);
}
/* drive strength depend on power source, so show all values */
if (type == IO_TYPE_EXTERNAL)
seq_printf(seq, ", drive strength (%d or %d mA)",
- spacemit_get_drive_strength_mA(IO_TYPE_1V8, tmp),
- spacemit_get_drive_strength_mA(IO_TYPE_3V3, tmp));
+ spacemit_get_drive_strength_mA(IO_TYPE_1V8, dconf, tmp),
+ spacemit_get_drive_strength_mA(IO_TYPE_3V3, dconf, tmp));
seq_printf(seq, ", register (0x%04x)", value);
}
@@ -1051,6 +1118,7 @@ static const struct spacemit_pinctrl_data k1_pinctrl_data = {
.data = k1_pin_data,
.npins = ARRAY_SIZE(k1_pin_desc),
.pin_to_offset = spacemit_k1_pin_to_offset,
+ .dconf = &k1_drive_conf,
};
static const struct pinctrl_pin_desc k3_pin_desc[] = {
@@ -1387,6 +1455,7 @@ static const struct spacemit_pinctrl_data k3_pinctrl_data = {
.data = k3_pin_data,
.npins = ARRAY_SIZE(k3_pin_desc),
.pin_to_offset = spacemit_k3_pin_to_offset,
+ .dconf = &k3_drive_conf,
};
static const struct of_device_id k1_pinctrl_ids[] = {
--
2.53.0

15
SPECS/linux/0087-FROMLIST-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch → SPECS/linux/0028-UPSTREAM-riscv-dts-thead-add-DPU-and-HDMI-device-tre.patch
View File

@@ -1,7 +1,7 @@
From 20868282dcb05c6edacbbacfe70b8397d87a54b5 Mon Sep 17 00:00:00 2001
From a8352604a5480a6e9e683297580d5c1c248167ba Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <uwu@icenowy.me>
Date: Fri, 23 Jan 2026 17:28:27 +0800
Subject: [PATCH 087/197] FROMLIST: riscv: dts: thead: add DPU and HDMI device
Date: Thu, 29 Jan 2026 10:39:20 +0800
Subject: [PATCH 028/189] UPSTREAM: riscv: dts: thead: add DPU and HDMI device
tree nodes
T-Head TH1520 SoC contains a Verisilicon DC8200 display controller
@@ -13,17 +13,20 @@ Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Tested-by: Han Gao <gaohan@iscas.ac.cn>
Tested-by: Michal Wilczynski <m.wilczynski@samsung.com>
Link: https://lore.kernel.org/r/20260123092830.4046009-7-zhengxingda@iscas.ac.cn
Reviewed-by: Drew Fustini <fustini@kernel.org>
Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Signed-off-by: Drew Fustini <fustini@kernel.org>
(cherry picked from commit 5634f777a6a94db316f9b26c00525320c3b582c2)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/thead/th1520.dtsi | 66 +++++++++++++++++++++++++++
1 file changed, 66 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 6020d568ad7c..36a2fd82343f 100644
index bd5d33840884..b66307742894 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -620,6 +620,72 @@ clk_vo: clock-controller@ffef528050 {
@@ -585,6 +585,72 @@ clk_vo: clock-controller@ffef528050 {
#clock-cells = <1>;
};

49
SPECS/linux/0029-UPSTREAM-dt-bindings-pinctrl-spacemit-add-syscon-pro.patch
View File

@@ -1,49 +0,0 @@
From 1d52605fe4d4a464c0ef0f243bd5613daef02637 Mon Sep 17 00:00:00 2001
From: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Date: Thu, 8 Jan 2026 14:42:38 +0800
Subject: [PATCH 029/197] UPSTREAM: dt-bindings: pinctrl: spacemit: add syscon
property
In order to access the protected IO power domain registers, a valid
unlock sequence must be performed by writing the required keys to the
AIB Secure Access Register (ASAR).
The ASAR register resides within the APBC register address space.
A corresponding syscon property is added to allow the pinctrl driver
to access this register.
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>
(cherry picked from commit e817f0223d78818cd6c0e3480355c9a9cfbc0096)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml
index 9a76cffcbaee..141dcedb81fb 100644
--- a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml
@@ -32,6 +32,10 @@ properties:
resets:
maxItems: 1
+ spacemit,apbc:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Phandle to syscon that access the protected register
+
patternProperties:
'-cfg$':
type: object
@@ -138,6 +142,7 @@ examples:
clocks = <&syscon_apbc 42>,
<&syscon_apbc 94>;
clock-names = "func", "bus";
+ spacemit,apbc = <&syscon_apbc>;
uart0_2_cfg: uart0-2-cfg {
uart0-2-pins {
--
2.53.0

11
SPECS/linux/0088-FROMLIST-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch → SPECS/linux/0029-UPSTREAM-riscv-dts-thead-lichee-pi-4a-enable-HDMI.patch
View File

@@ -1,7 +1,7 @@
From 5fdcecddc3702aa9f8e4b52ddd2828e74d44e39b Mon Sep 17 00:00:00 2001
From 1c25729207cfdb4af35ae49cde85109184ef7f83 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Date: Fri, 23 Jan 2026 17:28:28 +0800
Subject: [PATCH 088/197] FROMLIST: riscv: dts: thead: lichee-pi-4a: enable
Date: Thu, 29 Jan 2026 10:39:21 +0800
Subject: [PATCH 029/189] UPSTREAM: riscv: dts: thead: lichee-pi-4a: enable
HDMI
Lichee Pi 4A board features a HDMI Type-A connector connected to the
@@ -14,7 +14,10 @@ Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Tested-by: Han Gao <gaohan@iscas.ac.cn>
Tested-by: Michal Wilczynski <m.wilczynski@samsung.com>
Link: https://lore.kernel.org/r/20260123092830.4046009-8-zhengxingda@iscas.ac.cn
Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Signed-off-by: Drew Fustini <fustini@kernel.org>
(cherry picked from commit 9c99a784d9117a192ebf779d4f72ebec435ada97)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../boot/dts/thead/th1520-lichee-pi-4a.dts | 25 +++++++++++++++++++

263
SPECS/linux/0030-UPSTREAM-pinctrl-spacemit-support-I-O-power-domain-c.patch
View File

@@ -1,263 +0,0 @@
From 07f58697b3206b186eaa735ea1d6f9525478c177 Mon Sep 17 00:00:00 2001
From: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Date: Thu, 8 Jan 2026 14:42:39 +0800
Subject: [PATCH 030/197] UPSTREAM: pinctrl: spacemit: support I/O power domain
configuration
Dual-voltage GPIO banks default to 3.3V operation. Even when a bank is
externally supplied with 1.8V, the internal logic remains in the 3.3V
domain, leading to functional failures.
Add support for programming the IO domain power control registers to
allow explicit configuration for 1.8V operation.
These registers are secure due to hardware safety constraints.
Specifically, configuring the domain for 1.8V while externally supplying
3.3V causes back-powering and potential pin damage. Consequently, access
requires unlocking the AIB Secure Access Register (ASAR) in the APBC
block before any read or write operation.
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
(cherry picked from commit 450e2487d5a28260f70ad7fbf3060e7f8304203d)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/pinctrl/spacemit/pinctrl-k1.c | 129 +++++++++++++++++++++++++-
1 file changed, 126 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c
index 07267c5f0f44..71390402aaa6 100644
--- a/drivers/pinctrl/spacemit/pinctrl-k1.c
+++ b/drivers/pinctrl/spacemit/pinctrl-k1.c
@@ -7,8 +7,10 @@
#include <linux/io.h>
#include <linux/of.h>
#include <linux/platform_device.h>
+#include <linux/regmap.h>
#include <linux/seq_file.h>
#include <linux/spinlock.h>
+#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/mutex.h>
@@ -47,6 +49,27 @@
#define PAD_PULLUP BIT(14)
#define PAD_PULL_EN BIT(15)
+#define IO_PWR_DOMAIN_OFFSET 0x800
+
+#define IO_PWR_DOMAIN_GPIO2_Kx 0x0c
+#define IO_PWR_DOMAIN_MMC_Kx 0x1c
+
+#define IO_PWR_DOMAIN_GPIO3_K1 0x10
+#define IO_PWR_DOMAIN_QSPI_K1 0x20
+
+#define IO_PWR_DOMAIN_GPIO1_K3 0x04
+#define IO_PWR_DOMAIN_GPIO5_K3 0x10
+#define IO_PWR_DOMAIN_GPIO4_K3 0x20
+#define IO_PWR_DOMAIN_QSPI_K3 0x2c
+
+#define IO_PWR_DOMAIN_V18EN BIT(2)
+
+#define APBC_ASFAR 0x50
+#define APBC_ASSAR 0x54
+
+#define APBC_ASFAR_AKEY 0xbaba
+#define APBC_ASSAR_AKEY 0xeb10
+
struct spacemit_pin_drv_strength {
u8 val;
u32 mA;
@@ -78,6 +101,8 @@ struct spacemit_pinctrl {
raw_spinlock_t lock;
void __iomem *regs;
+
+ struct regmap *regmap_apbc;
};
struct spacemit_pinctrl_data {
@@ -85,6 +110,7 @@ struct spacemit_pinctrl_data {
const struct spacemit_pin *data;
u16 npins;
unsigned int (*pin_to_offset)(unsigned int pin);
+ unsigned int (*pin_to_io_pd_offset)(unsigned int pin);
const struct spacemit_pinctrl_dconf *dconf;
};
@@ -146,6 +172,56 @@ static unsigned int spacemit_k3_pin_to_offset(unsigned int pin)
return offset << 2;
}
+static unsigned int spacemit_k1_pin_to_io_pd_offset(unsigned int pin)
+{
+ unsigned int offset = 0;
+
+ switch (pin) {
+ case 47 ... 52:
+ offset = IO_PWR_DOMAIN_GPIO3_K1;
+ break;
+ case 75 ... 80:
+ offset = IO_PWR_DOMAIN_GPIO2_Kx;
+ break;
+ case 98 ... 103:
+ offset = IO_PWR_DOMAIN_QSPI_K1;
+ break;
+ case 104 ... 109:
+ offset = IO_PWR_DOMAIN_MMC_Kx;
+ break;
+ }
+
+ return offset;
+}
+
+static unsigned int spacemit_k3_pin_to_io_pd_offset(unsigned int pin)
+{
+ unsigned int offset = 0;
+
+ switch (pin) {
+ case 0 ... 20:
+ offset = IO_PWR_DOMAIN_GPIO1_K3;
+ break;
+ case 21 ... 41:
+ offset = IO_PWR_DOMAIN_GPIO2_Kx;
+ break;
+ case 76 ... 98:
+ offset = IO_PWR_DOMAIN_GPIO4_K3;
+ break;
+ case 99 ... 127:
+ offset = IO_PWR_DOMAIN_GPIO5_K3;
+ break;
+ case 132 ... 137:
+ offset = IO_PWR_DOMAIN_MMC_Kx;
+ break;
+ case 138 ... 144:
+ offset = IO_PWR_DOMAIN_QSPI_K3;
+ break;
+ }
+
+ return offset;
+}
+
static inline void __iomem *spacemit_pin_to_reg(struct spacemit_pinctrl *pctrl,
unsigned int pin)
{
@@ -365,6 +441,42 @@ static int spacemit_pctrl_check_power(struct pinctrl_dev *pctldev,
return 0;
}
+static void spacemit_set_io_pwr_domain(struct spacemit_pinctrl *pctrl,
+ const struct spacemit_pin *spin,
+ const enum spacemit_pin_io_type type)
+{
+ u32 offset, val = 0;
+
+ if (!pctrl->regmap_apbc)
+ return;
+
+ offset = pctrl->data->pin_to_io_pd_offset(spin->pin);
+
+ /* Other bits are reserved so don't need to save them */
+ if (type == IO_TYPE_1V8)
+ val = IO_PWR_DOMAIN_V18EN;
+
+ /*
+ * IO power domain registers are protected and cannot be accessed
+ * directly. Before performing any read or write to the IO power
+ * domain registers, an explicit unlock sequence must be issued
+ * via the AIB Secure Access Register (ASAR).
+ *
+ * The unlock sequence allows exactly one subsequent access to the
+ * IO power domain registers. After that access completes, the ASAR
+ * keys are automatically cleared, and the registers become locked
+ * again.
+ *
+ * This mechanism ensures that IO power domain configuration is
+ * performed intentionally, as incorrect voltage settings may
+ * result in functional failures or hardware damage.
+ */
+ regmap_write(pctrl->regmap_apbc, APBC_ASFAR, APBC_ASFAR_AKEY);
+ regmap_write(pctrl->regmap_apbc, APBC_ASSAR, APBC_ASSAR_AKEY);
+
+ writel_relaxed(val, pctrl->regs + IO_PWR_DOMAIN_OFFSET + offset);
+}
+
static int spacemit_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np,
struct pinctrl_map **maps,
@@ -572,7 +684,8 @@ static int spacemit_pinconf_get(struct pinctrl_dev *pctldev,
#define ENABLE_DRV_STRENGTH BIT(1)
#define ENABLE_SLEW_RATE BIT(2)
-static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin,
+static int spacemit_pinconf_generate_config(struct spacemit_pinctrl *pctrl,
+ const struct spacemit_pin *spin,
const struct spacemit_pinctrl_dconf *dconf,
unsigned long *configs,
unsigned int num_configs,
@@ -646,6 +759,7 @@ static int spacemit_pinconf_generate_config(const struct spacemit_pin *spin,
default:
return -EINVAL;
}
+ spacemit_set_io_pwr_domain(pctrl, spin, type);
}
val = spacemit_get_driver_strength(type, dconf, drv_strength);
@@ -701,7 +815,7 @@ static int spacemit_pinconf_set(struct pinctrl_dev *pctldev,
const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin);
u32 value;
- if (spacemit_pinconf_generate_config(spin, pctrl->data->dconf,
+ if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf,
configs, num_configs, &value))
return -EINVAL;
@@ -724,7 +838,7 @@ static int spacemit_pinconf_group_set(struct pinctrl_dev *pctldev,
return -EINVAL;
spin = spacemit_get_pin(pctrl, group->grp.pins[0]);
- if (spacemit_pinconf_generate_config(spin, pctrl->data->dconf,
+ if (spacemit_pinconf_generate_config(pctrl, spin, pctrl->data->dconf,
configs, num_configs, &value))
return -EINVAL;
@@ -795,6 +909,7 @@ static const struct pinconf_ops spacemit_pinconf_ops = {
static int spacemit_pinctrl_probe(struct platform_device *pdev)
{
+ struct device_node *np = pdev->dev.of_node;
struct device *dev = &pdev->dev;
struct spacemit_pinctrl *pctrl;
struct clk *func_clk, *bus_clk;
@@ -816,6 +931,12 @@ static int spacemit_pinctrl_probe(struct platform_device *pdev)
if (IS_ERR(pctrl->regs))
return PTR_ERR(pctrl->regs);
+ pctrl->regmap_apbc = syscon_regmap_lookup_by_phandle(np, "spacemit,apbc");
+ if (IS_ERR(pctrl->regmap_apbc)) {
+ dev_warn(dev, "no syscon found, disable power voltage switch functionality\n");
+ pctrl->regmap_apbc = NULL;
+ }
+
func_clk = devm_clk_get_enabled(dev, "func");
if (IS_ERR(func_clk))
return dev_err_probe(dev, PTR_ERR(func_clk), "failed to get func clock\n");
@@ -1118,6 +1239,7 @@ static const struct spacemit_pinctrl_data k1_pinctrl_data = {
.data = k1_pin_data,
.npins = ARRAY_SIZE(k1_pin_desc),
.pin_to_offset = spacemit_k1_pin_to_offset,
+ .pin_to_io_pd_offset = spacemit_k1_pin_to_io_pd_offset,
.dconf = &k1_drive_conf,
};
@@ -1455,6 +1577,7 @@ static const struct spacemit_pinctrl_data k3_pinctrl_data = {
.data = k3_pin_data,
.npins = ARRAY_SIZE(k3_pin_desc),
.pin_to_offset = spacemit_k3_pin_to_offset,
+ .pin_to_io_pd_offset = spacemit_k3_pin_to_io_pd_offset,
.dconf = &k3_drive_conf,
};
--
2.53.0

11
SPECS/linux/0156-FROMLIST-riscv-dts-thead-th1520-add-coefficients-to-.patch → SPECS/linux/0030-UPSTREAM-riscv-dts-thead-th1520-add-coefficients-to-.patch
View File

@@ -1,7 +1,7 @@
From b8dcb064ee53ae9241c9c1b7775e857cd8311467 Mon Sep 17 00:00:00 2001
From c38cbebf080934e0b6fbac619f495d035d15ee10 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Date: Tue, 10 Mar 2026 00:24:57 +0800
Subject: [PATCH 156/197] FROMLIST: riscv: dts: thead: th1520: add coefficients
Subject: [PATCH 030/189] UPSTREAM: riscv: dts: thead: th1520: add coefficients
to the PVT node
The manual of TH1520 contains a set of coefficients a little different
@@ -12,17 +12,18 @@ Add them to the device tree node of PVT.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Link: https://lore.kernel.org/r/20260309162457.4128205-3-zhengxingda@iscas.ac.cn
Signed-off-by: Drew Fustini <fustini@kernel.org>
(cherry picked from commit a7aa874b69460896349985833059a764e688f1d0)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/thead/th1520.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 36a2fd82343f..2910249e1f0c 100644
index b66307742894..5e91dc1d2b9b 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -854,6 +854,10 @@ pvt: pvt@fffff4e000 {
@@ -819,6 +819,10 @@ pvt: pvt@fffff4e000 {
reg-names = "common", "ts", "pd", "vm";
clocks = <&aonsys_clk>;
#thermal-sensor-cells = <1>;

48
SPECS/linux/0031-UPSTREAM-riscv-dts-spacemit-pinctrl-update-register-.patch
View File

@@ -1,48 +0,0 @@
From f56f07fc62ff716010837cc9e4f091db2f21440a Mon Sep 17 00:00:00 2001
From: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Date: Thu, 8 Jan 2026 14:42:40 +0800
Subject: [PATCH 031/197] UPSTREAM: riscv: dts: spacemit: pinctrl: update
register and IO power
Change the size of the reg register to 0x1000 to match the hardware.
This register range covers the IO power domain's register addresses.
The IO power domain registers are protected. In order to access the
protected IO power domain registers, a valid unlock sequence must be
performed by writing the required keys to the AIB Secure Access Register
(ASAR).
The ASAR register resides within the APBC register address space.
A corresponding syscon property `spacemit,apbc` is added to allow
the pinctrl driver to access this register.
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Acked-by: Linus Walleij <linusw@kernel.org>
Link: https://lore.kernel.org/r/20260108-kx-pinctrl-aib-io-pwr-domain-v2-3-6bcb46146e53@linux.spacemit.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
(cherry picked from commit 4083d8d6c0aa445fc440d70a5258351c47547ee2)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/spacemit/k1.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index 137fc26ddc29..e22a5f030fa2 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -628,10 +628,11 @@ i2c8: i2c@d401d800 {
pinctrl: pinctrl@d401e000 {
compatible = "spacemit,k1-pinctrl";
- reg = <0x0 0xd401e000 0x0 0x400>;
+ reg = <0x0 0xd401e000 0x0 0x1000>;
clocks = <&syscon_apbc CLK_AIB>,
<&syscon_apbc CLK_AIB_BUS>;
clock-names = "func", "bus";
+ spacemit,apbc = <&syscon_apbc>;
};
pwm8: pwm@d4020000 {
--
2.53.0

67
SPECS/linux/0031-UPSTREAM-riscv-dts-thead-beaglev-ahead-enable-HDMI-o.patch Normal file
View File

@@ -0,0 +1,67 @@
From c55a3079f9fc3d738c426c78c7df88f40451a4bb Mon Sep 17 00:00:00 2001
From: Robert Mazur <robert.mazur@imgtec.com>
Date: Wed, 25 Mar 2026 09:18:59 +0100
Subject: [PATCH 031/189] UPSTREAM: riscv: dts: thead: beaglev-ahead: enable
HDMI output
The BeagleV Ahead board includes a micro HDMI connector (Type-D)
wired to the TH1520 SoC's HDMI transmitter.
Enable the display pipeline by adding the HDMI connector node,
connecting it to the HDMI controller, and activating the DPU
and HDMI nodes.
Signed-off-by: Robert Mazur <robert.mazur@imgtec.com>
Signed-off-by: Drew Fustini <fustini@kernel.org>
(cherry picked from commit 74ec3d52c0035b662ec295bef2bbffad68446391)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../boot/dts/thead/th1520-beaglev-ahead.dts | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
index 21c33f165ba9..91f3f9b987bc 100644
--- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
@@ -75,6 +75,17 @@ led-5 {
label = "led5";
};
};
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "d";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
};
&osc {
@@ -236,6 +247,20 @@ &sdio0 {
status = "okay";
};
+&dpu {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out_port {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
--
2.53.0

78
SPECS/linux/0032-UPSTREAM-dt-bindings-riscv-update-ratified-version-o.patch
View File

@@ -1,78 +0,0 @@
From fe19dd9e7fe30b94433c5d9d6acc2ceb2e451e90 Mon Sep 17 00:00:00 2001
From: Guodong Xu <guodong@riscstar.com>
Date: Thu, 25 Dec 2025 14:24:20 +0800
Subject: [PATCH 032/197] UPSTREAM: dt-bindings: riscv: update ratified version
of h, svinval, svnapot, svpbmt
The descriptions for h, svinval, svnapot, and svpbmt extensions currently
reference the "20191213 version of the privileged ISA specification".
While an Unprivileged ISA document exists with that date, there is no
corresponding ratified Privileged ISA specification.
These extensions were ratified in the RISC-V Instruction Set Manual,
Volume II: Privileged Architecture, Version 20211203. Update the
descriptions to reference the correct specification version.
RISC-V International hosts a website [1] for ratified specifications.
Following the "Ratified ISA Specifications", historical versions of
Volume II Privileged ISA can be found.
Link: https://riscv.org/specifications/ratified/ [1]
Fixes: aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa")
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
(cherry picked from commit fff010c776f715904ba0823bb347eac00dccffa2)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../devicetree/bindings/riscv/extensions.yaml | 19 +++++++++++--------
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 5bab356addc8..b615083f2544 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -117,8 +117,9 @@ properties:
- const: h
description:
- The standard H extension for hypervisors as ratified in the 20191213
- version of the privileged ISA specification.
+ The standard H extension for hypervisors as ratified in the RISC-V
+ Instruction Set Manual, Volume II Privileged Architecture,
+ Document Version 20211203.
# multi-letter extensions, sorted alphanumerically
- const: smaia
@@ -202,20 +203,22 @@ properties:
- const: svinval
description:
The standard Svinval supervisor-level extension for fine-grained
- address-translation cache invalidation as ratified in the 20191213
- version of the privileged ISA specification.
+ address-translation cache invalidation as ratified in the RISC-V
+ Instruction Set Manual, Volume II Privileged Architecture,
+ Document Version 20211203.
- const: svnapot
description:
The standard Svnapot supervisor-level extensions for napot
- translation contiguity as ratified in the 20191213 version of the
- privileged ISA specification.
+ translation contiguity as ratified in the RISC-V Instruction Set
+ Manual, Volume II Privileged Architecture, Document Version
+ 20211203.
- const: svpbmt
description:
The standard Svpbmt supervisor-level extensions for page-based
- memory types as ratified in the 20191213 version of the privileged
- ISA specification.
+ memory types as ratified in the RISC-V Instruction Set Manual,
+ Volume II Privileged Architecture, Document Version 20211203.
- const: svrsw60t59b
description:
--
2.53.0

8
SPECS/linux/0102-FROMLIST-i2c-spacemit-move-i2c_xfer_msg.patch → SPECS/linux/0032-UPSTREAM-i2c-spacemit-move-i2c_xfer_msg.patch
View File

@@ -1,7 +1,7 @@
From b4d0a4f81e5c76178876df139d2719443a56641c Mon Sep 17 00:00:00 2001
From 2aeae8505a1fcd52cd8ef9520efcbe48a2f50858 Mon Sep 17 00:00:00 2001
From: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Date: Sat, 7 Feb 2026 23:08:21 +0800
Subject: [PATCH 102/197] FROMLIST: i2c: spacemit: move i2c_xfer_msg()
Subject: [PATCH 032/189] UPSTREAM: i2c: spacemit: move i2c_xfer_msg()
The upcoming PIO support requires a wait_pio_xfer() helper, which is
invoked from xfer_msg().
@@ -14,14 +14,16 @@ Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Alex Elder <elder@riscstar.com>
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20260207-b4-k3-i2c-pio-v7-1-626942d94d91@linux.spacemit.com
(cherry picked from commit 5b74da8e6cf7e2b5aed0836c733238c0fd7235af)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/i2c/busses/i2c-k1.c | 62 ++++++++++++++++++-------------------
1 file changed, 31 insertions(+), 31 deletions(-)
diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c
index d0948a16de3e..6787a51e7391 100644
index 6e93da576bbd..913aaea853e3 100644
--- a/drivers/i2c/busses/i2c-k1.c
+++ b/drivers/i2c/busses/i2c-k1.c
@@ -305,37 +305,6 @@ static void spacemit_i2c_start(struct spacemit_i2c_dev *i2c)

91
SPECS/linux/0033-UPSTREAM-dt-bindings-riscv-Add-B-ISA-extension-descr.patch
View File

@@ -1,91 +0,0 @@
From 8adbe4544e5a0b25d6cf49d7427ec4e74bbddf3f Mon Sep 17 00:00:00 2001
From: Guodong Xu <guodong@riscstar.com>
Date: Sat, 10 Jan 2026 13:18:18 +0800
Subject: [PATCH 033/197] UPSTREAM: dt-bindings: riscv: Add B ISA extension
description
Add description of the single-letter B extension for Bit Manipulation.
B is mandatory for RVA23U64.
The B extension is ratified in the 20240411 version of the unprivileged
ISA specification. According to the ratified spec, the B standard
extension comprises instructions provided by the Zba, Zbb, and Zbs
extensions.
Add two-way dependency check to enforce that B implies Zba/Zbb/Zbs; and
when Zba/Zbb/Zbs (all of them) are specified, then B must be added too.
The reason why B/Zba/Zbb/Zbs must coexist at the same time is that
unlike other single-letter extensions, B was ratified (Apr/2024) much
later than its component extensions Zba/Zbb/Zbs (Jun/2021).
When "b" is specified, zba/zbb/zbs must be present to ensure
backward compatibility with existing software and kernels that only
look for the explicit component strings.
When all three components zba/zbb/zbs are specified, "b" should also be
present. Making "b" mandatory when all three components are present.
Existing devicetrees with zba/zbb/zbs but without "b" will generate
warnings that can be fixed in follow-up patches.
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
(cherry picked from commit 0cdb7fc1879b1b858463125630f4dd5af6b111ad)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../devicetree/bindings/riscv/extensions.yaml | 31 +++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index b615083f2544..f671299ac819 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -109,6 +109,13 @@ properties:
The standard C extension for compressed instructions, as ratified in
the 20191213 version of the unprivileged ISA specification.
+ - const: b
+ description:
+ The standard B extension for bit manipulation instructions, as
+ ratified in the 20240411 version of the unprivileged ISA
+ specification. The B standard extension comprises instructions
+ provided by the Zba, Zbb, and Zbs extensions.
+
- const: v
description:
The standard V extension for vector operations, as ratified
@@ -752,6 +759,30 @@ properties:
then:
contains:
const: f
+ # B comprises Zba, Zbb, and Zbs
+ - if:
+ contains:
+ const: b
+ then:
+ allOf:
+ - contains:
+ const: zba
+ - contains:
+ const: zbb
+ - contains:
+ const: zbs
+ # Zba, Zbb, Zbs together require B
+ - if:
+ allOf:
+ - contains:
+ const: zba
+ - contains:
+ const: zbb
+ - contains:
+ const: zbs
+ then:
+ contains:
+ const: b
# Zcb depends on Zca
- if:
contains:
--
2.53.0

8
SPECS/linux/0103-FROMLIST-i2c-spacemit-introduce-pio-for-k1.patch → SPECS/linux/0033-UPSTREAM-i2c-spacemit-introduce-pio-for-k1.patch
View File

@@ -1,7 +1,7 @@
From 2f01ce645d333d4b0768f42dd1b9720dc319274b Mon Sep 17 00:00:00 2001
From d271b6ae87cd9c7ae3db7aad34420ffc678a278a Mon Sep 17 00:00:00 2001
From: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Date: Sat, 7 Feb 2026 23:08:22 +0800
Subject: [PATCH 103/197] FROMLIST: i2c: spacemit: introduce pio for k1
Subject: [PATCH 033/189] UPSTREAM: i2c: spacemit: introduce pio for k1
This patch introduces I2C PIO functionality for the Spacemit K1 SoC,
enabling the use of I2C in atomic context.
@@ -16,14 +16,16 @@ be performed by polling the relevant status bits in the ISR.
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://lore.kernel.org/r/20260207-b4-k3-i2c-pio-v7-2-626942d94d91@linux.spacemit.com
(cherry picked from commit 5dd75dac1b35e5b24f5051d01fc85105adcc2e15)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/i2c/busses/i2c-k1.c | 300 +++++++++++++++++++++++++++---------
1 file changed, 228 insertions(+), 72 deletions(-)
diff --git a/drivers/i2c/busses/i2c-k1.c b/drivers/i2c/busses/i2c-k1.c
index 6787a51e7391..afc6bdd68bd4 100644
index 913aaea853e3..9152cf436bea 100644
--- a/drivers/i2c/busses/i2c-k1.c
+++ b/drivers/i2c/busses/i2c-k1.c
@@ -98,6 +98,10 @@

131
SPECS/linux/0034-UPSTREAM-dt-bindings-riscv-Add-descriptions-for-Za64.patch
View File

@@ -1,131 +0,0 @@
From 9333a4985b91bef42dccb8f001c2a2bc9d521145 Mon Sep 17 00:00:00 2001
From: Guodong Xu <guodong@riscstar.com>
Date: Sat, 10 Jan 2026 13:18:19 +0800
Subject: [PATCH 034/197] UPSTREAM: dt-bindings: riscv: Add descriptions for
Za64rs, Ziccamoa, Ziccif, and Zicclsm
Add descriptions for four extensions: Za64rs, Ziccamoa, Ziccif, and
Zicclsm. These extensions are ratified in RISC-V Profiles Version 1.0
(commit b1d806605f87 "Updated to ratified state.").
They are introduced as new extension names for existing features and
regulate implementation details for RISC-V Profile compliance. According
to RISC-V Profiles Version 1.0 and RVA23 Profiles Version 1.0, they are
mandatory for the following profiles:
- za64rs: Mandatory in RVA22U64, RVA23U64
- ziccamoa: Mandatory in RVA20U64, RVA22U64, RVA23U64
- ziccif: Mandatory in RVA20U64, RVA22U64, RVA23U64
- zicclsm: Mandatory in RVA20U64, RVA22U64, RVA23U64
Ziccrse specifies the main memory must support "RsrvEventual", which is
one (totally there are four) of the support level for Load-Reserved/
Store-Conditional (LR/SC) atomic instructions. Thus it depends on Zalrsc.
Ziccamoa specifies the main memory must support AMOArithmetic, among the
four levels of PMA support defined for AMOs in the A extension. Thus it
depends on Zaamo.
Za64rs defines reservation sets are contiguous, naturally aligned, and a
maximum of 64 bytes. Za64rs is consumed by two extensions: Zalrsc and
Zawrs. Zawrs itself depends on Zalrsc too.
Based on the relationship that "A" = Zaamo + Zalrsc, add the following
dependencies checks:
Za64rs -> Zalrsc or A
Ziccrse -> Zalrsc or A
Ziccamoa -> Zaamo or A
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
(cherry picked from commit b321256a4f36227e0c1ae54e8c6c48524dcba83d)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../devicetree/bindings/riscv/extensions.yaml | 49 +++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index f671299ac819..345624326e9f 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -240,6 +240,12 @@ properties:
as ratified at commit 4a69197e5617 ("Update to ratified state") of
riscv-svvptc.
+ - const: za64rs
+ description:
+ The standard Za64rs extension for reservation set size of at most
+ 64 bytes, as ratified in RISC-V Profiles Version 1.0, with commit
+ b1d806605f87 ("Updated to ratified state.")
+
- const: zaamo
description: |
The standard Zaamo extension for atomic memory operations as
@@ -381,6 +387,27 @@ properties:
in commit 64074bc ("Update version numbers for Zfh/Zfinx") of
riscv-isa-manual.
+ - const: ziccamoa
+ description:
+ The standard Ziccamoa extension for main memory (cacheability and
+ coherence) must support all atomics in A, as ratified in RISC-V
+ Profiles Version 1.0, with commit b1d806605f87 ("Updated to
+ ratified state.")
+
+ - const: ziccif
+ description:
+ The standard Ziccif extension for main memory (cacheability and
+ coherence) instruction fetch atomicity, as ratified in RISC-V
+ Profiles Version 1.0, with commit b1d806605f87 ("Updated to
+ ratified state.")
+
+ - const: zicclsm
+ description:
+ The standard Zicclsm extension for main memory (cacheability and
+ coherence) must support misaligned loads and stores, as ratified
+ in RISC-V Profiles Version 1.0, with commit b1d806605f87 ("Updated
+ to ratified state.")
+
- const: ziccrse
description:
The standard Ziccrse extension which provides forward progress
@@ -783,6 +810,18 @@ properties:
then:
contains:
const: b
+ # Za64rs and Ziccrse depend on Zalrsc or A
+ - if:
+ contains:
+ anyOf:
+ - const: za64rs
+ - const: ziccrse
+ then:
+ oneOf:
+ - contains:
+ const: zalrsc
+ - contains:
+ const: a
# Zcb depends on Zca
- if:
contains:
@@ -824,6 +863,16 @@ properties:
then:
contains:
const: f
+ # Ziccamoa depends on Zaamo or A
+ - if:
+ contains:
+ const: ziccamoa
+ then:
+ oneOf:
+ - contains:
+ const: zaamo
+ - contains:
+ const: a
# Zvfbfmin depends on V or Zve32f
- if:
contains:
--
2.53.0

11
SPECS/linux/0157-FROMLIST-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch → SPECS/linux/0034-UPSTREAM-pinctrl-spacemit-return-ENOTSUPP-for-unsupp.patch
View File

@@ -1,7 +1,7 @@
From ecf53216e724527b2507d578ef763ce1d11edd25 Mon Sep 17 00:00:00 2001
From 50deee38ad989c10e5b55ec23352b639d1c64f5e Mon Sep 17 00:00:00 2001
From: Junhui Liu <junhui.liu@pigmoral.tech>
Date: Thu, 12 Mar 2026 16:42:42 +0800
Subject: [PATCH 157/197] FROMLIST: pinctrl: spacemit: return -ENOTSUPP for
Subject: [PATCH 034/189] UPSTREAM: pinctrl: spacemit: return -ENOTSUPP for
unsupported pin configurations
Return -ENOTSUPP instead of -EINVAL when encountering unsupported pin
@@ -11,15 +11,18 @@ gpio_set_config_with_argument_optional(), which specifically ignores
-ENOTSUPP but treats others as failure.
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260312-k1-gpio-set-config-v1-1-8c3541da16b1@pigmoral.tech
Signed-off-by: Linus Walleij <linusw@kernel.org>
(cherry picked from commit c3b0c06b73974d75c640a4ebc8678f8538654e5a)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/pinctrl/spacemit/pinctrl-k1.c | 21 ++++++++++++---------
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c
index 71390402aaa6..f3c754f78074 100644
index 62cab6f6cd0a..b0be62b1c816 100644
--- a/drivers/pinctrl/spacemit/pinctrl-k1.c
+++ b/drivers/pinctrl/spacemit/pinctrl-k1.c
@@ -674,7 +674,7 @@ static int spacemit_pinconf_get(struct pinctrl_dev *pctldev,

89
SPECS/linux/0035-UPSTREAM-dt-bindings-riscv-Add-Ssccptr-Sscounterenw-.patch
View File

@@ -1,89 +0,0 @@
From 5594394b4c89d452951650cd26904f1e8313d5ed Mon Sep 17 00:00:00 2001
From: Guodong Xu <guodong@riscstar.com>
Date: Sat, 10 Jan 2026 13:18:20 +0800
Subject: [PATCH 035/197] UPSTREAM: dt-bindings: riscv: Add Ssccptr,
Sscounterenw, Sstvala, Sstvecd, Ssu64xl
Add descriptions for five new extensions: Ssccptr, Sscounterenw, Sstvala,
Sstvecd, and Ssu64xl. These extensions are ratified in RISC-V Profiles
Version 1.0 (commit b1d806605f87 "Updated to ratified state.").
They are introduced as new extension names for existing features and
regulate implementation details for RISC-V Profile compliance. According
to RISC-V Profiles Version 1.0 and RVA23 Profiles Version 1.0, their
requirement status are:
- Ssccptr: Mandatory in RVA20S64, RVA22S64, RVA23S64
- Sscounterenw: Mandatory in RVA22S64, RVA23S64
- Sstvala: Mandatory in RVA20S64, RVA22S64, RVA23S64
- Sstvecd: Mandatory in RVA20S64, RVA22S64, RVA23S64
- Ssu64xl: Optional in RVA20S64, RVA22S64; Mandatory in RVA23S64
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
(cherry picked from commit c712413333f8e19cc3de4e9cd1a3ed8a53169cc9)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../devicetree/bindings/riscv/extensions.yaml | 32 +++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 345624326e9f..900270e8d22e 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -161,12 +161,26 @@ properties:
behavioural changes to interrupts as frozen at commit ccbddab
("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
+ - const: ssccptr
+ description: |
+ The standard Ssccptr extension for main memory (cacheability and
+ coherence) hardware page-table reads, as ratified in RISC-V
+ Profiles Version 1.0, with commit b1d806605f87 ("Updated to
+ ratified state.")
+
- const: sscofpmf
description: |
The standard Sscofpmf supervisor-level extension for count overflow
and mode-based filtering as ratified at commit 01d1df0 ("Add ability
to manually trigger workflow. (#2)") of riscv-count-overflow.
+ - const: sscounterenw
+ description: |
+ The standard Sscounterenw extension for support writable enables
+ in scounteren for any supported counter, as ratified in RISC-V
+ Profiles Version 1.0, with commit b1d806605f87 ("Updated to
+ ratified state.")
+
- const: ssnpm
description: |
The standard Ssnpm extension for next-mode pointer masking as
@@ -179,6 +193,24 @@ properties:
ratified at commit 3f9ed34 ("Add ability to manually trigger
workflow. (#2)") of riscv-time-compare.
+ - const: sstvala
+ description: |
+ The standard Sstvala extension for stval provides all needed values
+ as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
+ ("Updated to ratified state.")
+
+ - const: sstvecd
+ description: |
+ The standard Sstvecd extension for stvec supports Direct mode as
+ ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
+ ("Updated to ratified state.")
+
+ - const: ssu64xl
+ description: |
+ The standard Ssu64xl extension for UXLEN=64 must be supported, as
+ ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
+ ("Updated to ratified state.")
+
- const: svade
description: |
The standard Svade supervisor-level extension for SW-managed PTE A/D
--
2.53.0

9
SPECS/linux/0158-FROMLIST-gpio-spacemit-k1-Add-set_config-callback-su.patch → SPECS/linux/0035-UPSTREAM-gpio-spacemit-k1-Add-set_config-callback-su.patch
View File

@@ -1,7 +1,7 @@
From 29c5a04816e39ba91b18faedf5e7e443a11c52ad Mon Sep 17 00:00:00 2001
From 19ebb6769d800d1ba24edc2b00825dbb60f891a7 Mon Sep 17 00:00:00 2001
From: Junhui Liu <junhui.liu@pigmoral.tech>
Date: Thu, 12 Mar 2026 16:42:43 +0800
Subject: [PATCH 158/197] FROMLIST: gpio: spacemit-k1: Add set_config callback
Subject: [PATCH 035/189] UPSTREAM: gpio: spacemit-k1: Add set_config callback
support
Assign gpiochip_generic_config() to the set_config() callback to support
@@ -10,8 +10,11 @@ configure GPIO pin attributes like pull-up/down when specifying a GPIO
line in the Device Tree.
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260312-k1-gpio-set-config-v1-2-8c3541da16b1@pigmoral.tech
Signed-off-by: Linus Walleij <linusw@kernel.org>
(cherry picked from commit 47a9050e678c7929ada33c3f1f28ac4403423181)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/gpio/gpio-spacemit-k1.c | 1 +

118
SPECS/linux/0036-UPSTREAM-dt-bindings-riscv-Add-Sha-and-its-comprised.patch
View File

@@ -1,118 +0,0 @@
From 9c2e6681c420bae3fc4a444a7304982523881750 Mon Sep 17 00:00:00 2001
From: Guodong Xu <guodong@riscstar.com>
Date: Sat, 10 Jan 2026 13:18:21 +0800
Subject: [PATCH 036/197] UPSTREAM: dt-bindings: riscv: Add Sha and its
comprised extensions
Add descriptions for the Sha extension and the seven extensions it
comprises: Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, Shvstvecd,
and Ssstateen.
Sha is ratified in the RVA23 Profiles Version 1.0 (commit 0273f3c921b6
"rva23/rvb23 ratified") as a new profile-defined extension that captures
the full set of features that are mandated to be supported along with
the H extension.
Extensions Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, Shvstvecd,
and Ssstateen are ratified in the RISC-V Profiles Version 1.0 (commit
b1d806605f87 "Updated to ratified state").
The requirement status for Sha and its comprised extension in RISC-V
Profiles are:
- Sha: Mandatory in RVA23S64
- H: Optional in RVA22S64; Mandatory in RVA23S64
- Shcounterenw: Optional in RVA22S64; Mandatory in RVA23S64
- Shgatpa: Optional in RVA22S64; Mandatory in RVA23S64
- Shtvala: Optional in RVA22S64; Mandatory in RVA23S64
- Shvsatpa: Optional in RVA22S64; Mandatory in RVA23S64
- Shvstvala: Optional in RVA22S64; Mandatory in RVA23S64
- Shvstvecd: Optional in RVA22S64; Mandatory in RVA23S64
- Ssstateen: Optional in RVA22S64; Mandatory in RVA23S64
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
(cherry picked from commit 89febd6a02768200fcfc86ee57f1ece632805bff)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../devicetree/bindings/riscv/extensions.yaml | 57 +++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 900270e8d22e..41cb4aeb2667 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -129,6 +129,57 @@ properties:
Document Version 20211203.
# multi-letter extensions, sorted alphanumerically
+ - const: sha
+ description: |
+ The standard Sha extension for augmented hypervisor extension as
+ ratified in RVA23 Profiles Version 1.0, with commit 0273f3c921b6
+ ("rva23/rvb23 ratified").
+
+ Sha captures the full set of features that are mandated to be
+ supported along with the H extension. Sha comprises the following
+ extensions: H, Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala,
+ Shvstvecd, and Ssstateen.
+
+ - const: shcounterenw
+ description: |
+ The standard Shcounterenw extension for support writable enables
+ in hcounteren for any supported counter, as ratified in RISC-V
+ Profiles Version 1.0, with commit b1d806605f87 ("Updated to
+ ratified state.")
+
+ - const: shgatpa
+ description: |
+ The standard Shgatpa extension indicates that for each supported
+ virtual memory scheme SvNN supported in satp, the corresponding
+ hgatp SvNNx4 mode must be supported. The hgatp mode Bare must
+ also be supported. It is ratified in RISC-V Profiles Version 1.0,
+ with commit b1d806605f87 ("Updated to ratified state.")
+
+ - const: shtvala
+ description: |
+ The standard Shtvala extension for htval be written with the
+ faulting guest physical address in all circumstances permitted by
+ the ISA. It is ratified in RISC-V Profiles Version 1.0, with
+ commit b1d806605f87 ("Updated to ratified state.")
+
+ - const: shvsatpa
+ description: |
+ The standard Shvsatpa extension for vsatp supporting all translation
+ modes supported in satp, as ratified in RISC-V Profiles Version 1.0,
+ with commit b1d806605f87 ("Updated to ratified state.")
+
+ - const: shvstvala
+ description: |
+ The standard Shvstvala extension for vstval provides all needed
+ values as ratified in RISC-V Profiles Version 1.0, with commit
+ b1d806605f87 ("Updated to ratified state.")
+
+ - const: shvstvecd
+ description: |
+ The standard Shvstvecd extension for vstvec supporting Direct mode,
+ as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87
+ ("Updated to ratified state.")
+
- const: smaia
description: |
The standard Smaia supervisor-level extension for the advanced
@@ -187,6 +238,12 @@ properties:
ratified at commit d70011dde6c2 ("Update to ratified state")
of riscv-j-extension.
+ - const: ssstateen
+ description: |
+ The standard Ssstateen extension for supervisor-mode view of the
+ state-enable extension, as ratified in RISC-V Profiles Version 1.0,
+ with commit b1d806605f87 ("Updated to ratified state.")
+
- const: sstc
description: |
The standard Sstc supervisor-level extension for time compare as
--
2.53.0

13
SPECS/linux/0122-FROMLIST-riscv-dts-spacemit-pcie-fix-missing-power-r.patch → SPECS/linux/0036-UPSTREAM-riscv-dts-spacemit-pcie-fix-missing-power-r.patch
View File

@@ -1,7 +1,7 @@
From 53748f2b36ef538e5db3f1b7845c36ec08ff1b84 Mon Sep 17 00:00:00 2001
From 3c0a662d357f68828d2c1f95136711b738f2624a Mon Sep 17 00:00:00 2001
From: Yixun Lan <dlan@kernel.org>
Date: Thu, 26 Feb 2026 08:17:55 +0000
Subject: [PATCH 122/197] FROMLIST: riscv: dts: spacemit: pcie: fix missing
Subject: [PATCH 036/189] UPSTREAM: riscv: dts: spacemit: pcie: fix missing
power regulator
The PCIe port require 3.3v power regulator for device to work properly, So
@@ -12,18 +12,19 @@ arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dtb: pcie@ca400000 (spacemit,k1-pcie
Fixes: 0be016a4b5d1 ("riscv: dts: spacemit: PCIe and PHY-related updates")
Reported-by: Conor Dooley <conor@kernel.org>
Signed-off-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260226-k1-pcie-fix-pwr-v1-1-94b493cd27e5@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
(cherry picked from commit 8a9071299dec817a544c0fb48f7302396fafdc4b)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index 55fb87234e7f..af0176f50b19 100644
index 5971605754b3..51f6c6a774b0 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -314,6 +314,7 @@ &pcie1_phy {
@@ -305,6 +305,7 @@ &pcie1_phy {
&pcie1_port {
phys = <&pcie1_phy>;
@@ -31,7 +32,7 @@ index 55fb87234e7f..af0176f50b19 100644
};
&pcie1 {
@@ -329,6 +330,7 @@ &pcie2_phy {
@@ -320,6 +321,7 @@ &pcie2_phy {
&pcie2_port {
phys = <&pcie2_phy>;

868
SPECS/linux/0037-UPSTREAM-riscv-dts-sophgo-sg2044-Add-b-ISA-extension.patch
View File

@@ -1,868 +0,0 @@
From be505ee427473e215ec14cb8644a152ee7d6922f Mon Sep 17 00:00:00 2001
From: Guodong Xu <guodong@riscstar.com>
Date: Thu, 15 Jan 2026 07:18:59 +0800
Subject: [PATCH 037/197] UPSTREAM: riscv: dts: sophgo: sg2044: Add "b" ISA
extension
"b" is ratified (Apr/2024) much later than its components zba/zbb/zbs
(Jun/2021). With "b" added into riscv/extensions.yaml, a dependency
checking rule is now enforced, which requires that when zba, zbb, and zbs
are all specified, "b" must be added as well. Failing to do this will
cause dtbs_check schema check warnings.
According to uabi.rst, as a single-letter extension, "b" should be added
after "c" in canonical order.
Update sg2044-cpus.dtsi to conform to this rule.
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Reviewed-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20260115-adding-b-dtsi-v2-3-254dd61cf947@riscstar.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
(cherry picked from commit f16ae81b80ca4e721f4c4ed1f28390115f7721eb)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 256 ++++++++++----------
1 file changed, 128 insertions(+), 128 deletions(-)
diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
index 523799a1a8b8..3135409c2149 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
@@ -24,10 +24,10 @@ cpu0: cpu@0 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache0>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -60,10 +60,10 @@ cpu1: cpu@1 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache0>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -96,10 +96,10 @@ cpu2: cpu@2 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache0>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -132,10 +132,10 @@ cpu3: cpu@3 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache0>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -168,10 +168,10 @@ cpu4: cpu@4 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache1>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -204,10 +204,10 @@ cpu5: cpu@5 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache1>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -240,10 +240,10 @@ cpu6: cpu@6 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache1>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -276,10 +276,10 @@ cpu7: cpu@7 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache1>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -312,10 +312,10 @@ cpu8: cpu@8 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache2>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -348,10 +348,10 @@ cpu9: cpu@9 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache2>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -384,10 +384,10 @@ cpu10: cpu@10 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache2>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -420,10 +420,10 @@ cpu11: cpu@11 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache2>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -456,10 +456,10 @@ cpu12: cpu@12 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache3>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -492,10 +492,10 @@ cpu13: cpu@13 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache3>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -528,10 +528,10 @@ cpu14: cpu@14 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache3>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -564,10 +564,10 @@ cpu15: cpu@15 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache3>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -600,10 +600,10 @@ cpu16: cpu@16 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache4>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -636,10 +636,10 @@ cpu17: cpu@17 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache4>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -672,10 +672,10 @@ cpu18: cpu@18 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache4>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -708,10 +708,10 @@ cpu19: cpu@19 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache4>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -744,10 +744,10 @@ cpu20: cpu@20 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache5>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -780,10 +780,10 @@ cpu21: cpu@21 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache5>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -816,10 +816,10 @@ cpu22: cpu@22 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache5>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -852,10 +852,10 @@ cpu23: cpu@23 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache5>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -888,10 +888,10 @@ cpu24: cpu@24 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache6>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -924,10 +924,10 @@ cpu25: cpu@25 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache6>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -960,10 +960,10 @@ cpu26: cpu@26 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache6>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -996,10 +996,10 @@ cpu27: cpu@27 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache6>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1032,10 +1032,10 @@ cpu28: cpu@28 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache7>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1068,10 +1068,10 @@ cpu29: cpu@29 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache7>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1104,10 +1104,10 @@ cpu30: cpu@30 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache7>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1140,10 +1140,10 @@ cpu31: cpu@31 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache7>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1176,10 +1176,10 @@ cpu32: cpu@32 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache8>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1212,10 +1212,10 @@ cpu33: cpu@33 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache8>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1248,10 +1248,10 @@ cpu34: cpu@34 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache8>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1284,10 +1284,10 @@ cpu35: cpu@35 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache8>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1320,10 +1320,10 @@ cpu36: cpu@36 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache9>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1356,10 +1356,10 @@ cpu37: cpu@37 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache9>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1392,10 +1392,10 @@ cpu38: cpu@38 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache9>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1428,10 +1428,10 @@ cpu39: cpu@39 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache9>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1464,10 +1464,10 @@ cpu40: cpu@40 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache10>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1500,10 +1500,10 @@ cpu41: cpu@41 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache10>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1536,10 +1536,10 @@ cpu42: cpu@42 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache10>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1572,10 +1572,10 @@ cpu43: cpu@43 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache10>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1608,10 +1608,10 @@ cpu44: cpu@44 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache11>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1644,10 +1644,10 @@ cpu45: cpu@45 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache11>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1680,10 +1680,10 @@ cpu46: cpu@46 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache11>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1716,10 +1716,10 @@ cpu47: cpu@47 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache11>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1752,10 +1752,10 @@ cpu48: cpu@48 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache12>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1788,10 +1788,10 @@ cpu49: cpu@49 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache12>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1824,10 +1824,10 @@ cpu50: cpu@50 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache12>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1860,10 +1860,10 @@ cpu51: cpu@51 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache12>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1896,10 +1896,10 @@ cpu52: cpu@52 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache13>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1932,10 +1932,10 @@ cpu53: cpu@53 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache13>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -1968,10 +1968,10 @@ cpu54: cpu@54 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache13>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -2004,10 +2004,10 @@ cpu55: cpu@55 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache13>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -2040,10 +2040,10 @@ cpu56: cpu@56 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache14>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -2076,10 +2076,10 @@ cpu57: cpu@57 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache14>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -2112,10 +2112,10 @@ cpu58: cpu@58 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache14>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -2148,10 +2148,10 @@ cpu59: cpu@59 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache14>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -2184,10 +2184,10 @@ cpu60: cpu@60 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache15>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -2220,10 +2220,10 @@ cpu61: cpu@61 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache15>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -2256,10 +2256,10 @@ cpu62: cpu@62 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache15>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@@ -2292,10 +2292,10 @@ cpu63: cpu@63 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache15>;
- riscv,isa = "rv64imafdcv";
+ riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
- "v", "sscofpmf", "sstc",
+ "b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
--
2.53.0

25
SPECS/linux/0116-FROMLIST-riscv-dts-spacemit-Update-PMIC-supply-prope.patch → SPECS/linux/0037-UPSTREAM-riscv-dts-spacemit-Update-PMIC-supply-prope.patch
View File

@@ -1,18 +1,17 @@
From acbb48383856ddfcb972a0f96d07fdfc53d0c78a Mon Sep 17 00:00:00 2001
From 0c4f026d521ec1e5583082d0fd896fdd920b4f13 Mon Sep 17 00:00:00 2001
From: Guodong Xu <guodong@riscstar.com>
Date: Sat, 24 Jan 2026 08:20:19 +0800
Subject: [PATCH 116/197] FROMLIST: riscv: dts: spacemit: Update PMIC supply
Date: Fri, 6 Feb 2026 10:32:04 +0800
Subject: [PATCH 037/189] UPSTREAM: riscv: dts: spacemit: Update PMIC supply
properties for BPI-F3 and Jupiter
Update individual supply properties in pmic "spacemit,p1" node to specify
the board's power tree topology for BananaPi F3 and Milk-V Jupiter.
Previously these relationships were hardcoded in the driver; now they
are explicitly defined in the devicetree per the updated binding
document spacemit,p1.yaml.
Use per-regulator supply names in pmic "spacemit,p1" node to specify
each board's power tree topology and match the updated dt-binding.
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Link: https://lore.kernel.org/r/20260124-spacemit-p1-v2-4-2c86b06694ba@riscstar.com
Reviewed-by: Alex Elder <elder@riscstar.com>
Link: https://lore.kernel.org/r/20260206-spacemit-p1-v4-3-8f695d93811e@riscstar.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
(cherry picked from commit 108c77b34b929e6bdb7ac9613ed65c90da8bcb9f)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 12 ++++++++++--
@@ -20,10 +19,10 @@ Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
2 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index da5af14c6432..9b25bb30811c 100644
index 51f6c6a774b0..ed88507b84e9 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -191,7 +191,15 @@ pmic@41 {
@@ -190,7 +190,15 @@ pmic@41 {
compatible = "spacemit,p1";
reg = <0x41>;
interrupts = <64>;
@@ -40,7 +39,7 @@ index da5af14c6432..9b25bb30811c 100644
regulators {
buck1 {
@@ -222,7 +230,7 @@ buck4 {
@@ -221,7 +229,7 @@ buck4 {
regulator-always-on;
};

21
SPECS/linux/0121-FROMLIST-riscv-dts-spacemit-adapt-regulator-node-nam.patch → SPECS/linux/0038-UPSTREAM-riscv-dts-spacemit-adapt-regulator-node-nam.patch
View File

@@ -1,7 +1,7 @@
From 6fe07239b65fd52af2632c6f13713fa421f3ffb4 Mon Sep 17 00:00:00 2001
From da6462543d172a008d0f0e0a105550c25ac0241e Mon Sep 17 00:00:00 2001
From: Yixun Lan <dlan@kernel.org>
Date: Thu, 26 Feb 2026 09:35:00 +0000
Subject: [PATCH 121/197] FROMLIST: riscv: dts: spacemit: adapt regulator node
Subject: [PATCH 038/189] UPSTREAM: riscv: dts: spacemit: adapt regulator node
name to preferred form
The preferred node name for fixed-regulators has changed to pattern [1]:
@@ -9,10 +9,11 @@ The preferred node name for fixed-regulators has changed to pattern [1]:
Adjust all SpacemiT DT regulator node names to fix this.
Link: https://lore.kernel.org/r/20240426215147.3138211-1-robh@kernel.org [1]
Signed-off-by: Yixun Lan <dlan@kernel.org>
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
Link: https://lore.kernel.org/r/20240426215147.3138211-1-robh@kernel.org [1]
Link: https://lore.kernel.org/r/20260226-02-k1-regulator-names-v1-1-e87695d50159@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
(cherry picked from commit ec1fb4e55df47ed043ab2ccc6787e39b9d67e49b)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 10 +++++-----
@@ -20,10 +21,10 @@ Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index 9b25bb30811c..55fb87234e7f 100644
index ed88507b84e9..404b69c47b91 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -34,7 +34,7 @@ led1 {
@@ -33,7 +33,7 @@ led1 {
};
};
@@ -32,7 +33,7 @@ index 9b25bb30811c..55fb87234e7f 100644
compatible = "regulator-fixed";
regulator-name = "PCIE_VCC3V3";
regulator-min-microvolt = <3300000>;
@@ -42,7 +42,7 @@ pcie_vcc_3v3: pcie-vcc3v3 {
@@ -41,7 +41,7 @@ pcie_vcc_3v3: pcie-vcc3v3 {
regulator-always-on;
};
@@ -41,7 +42,7 @@ index 9b25bb30811c..55fb87234e7f 100644
compatible = "regulator-fixed";
regulator-name = "dc_in_12v";
regulator-min-microvolt = <12000000>;
@@ -51,7 +51,7 @@ reg_dc_in: dc-in-12v {
@@ -50,7 +50,7 @@ reg_dc_in: dc-in-12v {
regulator-always-on;
};
@@ -50,7 +51,7 @@ index 9b25bb30811c..55fb87234e7f 100644
compatible = "regulator-fixed";
regulator-name = "vcc_4v";
regulator-min-microvolt = <4000000>;
@@ -61,7 +61,7 @@ reg_vcc_4v: vcc-4v {
@@ -60,7 +60,7 @@ reg_vcc_4v: vcc-4v {
vin-supply = <&reg_dc_in>;
};
@@ -59,7 +60,7 @@ index 9b25bb30811c..55fb87234e7f 100644
compatible = "regulator-fixed";
regulator-name = "USB30_VBUS";
regulator-min-microvolt = <5000000>;
@@ -71,7 +71,7 @@ usb3-vbus-5v {
@@ -70,7 +70,7 @@ usb3-vbus-5v {
enable-active-high;
};

130
SPECS/linux/0038-UPSTREAM-riscv-dts-spacemit-k1-Add-b-ISA-extension.patch
View File

@@ -1,130 +0,0 @@
From b14cc99422fb620e7c20afd2aeb4076597523b65 Mon Sep 17 00:00:00 2001
From: Guodong Xu <guodong@riscstar.com>
Date: Thu, 15 Jan 2026 07:19:00 +0800
Subject: [PATCH 038/197] UPSTREAM: riscv: dts: spacemit: k1: Add "b" ISA
extension
"b" is ratified (Apr/2024) much later than its components zba/zbb/zbs
(Jun/2021). With "b" added into riscv/extensions.yaml, a dependency
checking rule is now enforced, which requires that when zba, zbb, and zbs
are all specified, "b" must be added as well. Failing to do this will
cause dtbs_check schema check warnings.
According to uabi.rst, as a single-letter extension, "b" should be added
after "c" in canonical order.
Update k1.dtsi to conform to this rule.
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20260115-adding-b-dtsi-v2-4-254dd61cf947@riscstar.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
(cherry picked from commit 4168630825f95bf57729dad46d2a097096e73e4d)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/spacemit/k1.dtsi | 32 ++++++++++++++--------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index e22a5f030fa2..0a884947fda4 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -54,9 +54,9 @@ cpu_0: cpu@0 {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <0>;
- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
@@ -84,9 +84,9 @@ cpu_1: cpu@1 {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <1>;
- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
@@ -114,9 +114,9 @@ cpu_2: cpu@2 {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <2>;
- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
@@ -144,9 +144,9 @@ cpu_3: cpu@3 {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <3>;
- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
@@ -174,9 +174,9 @@ cpu_4: cpu@4 {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <4>;
- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
@@ -204,9 +204,9 @@ cpu_5: cpu@5 {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <5>;
- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
@@ -234,9 +234,9 @@ cpu_6: cpu@6 {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <6>;
- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
@@ -264,9 +264,9 @@ cpu_7: cpu@7 {
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <7>;
- riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
+ riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
--
2.53.0

48
SPECS/linux/0039-UPSTREAM-dt-bindings-riscv-add-SpacemiT-X100-CPU-com.patch
View File

@@ -1,48 +0,0 @@
From 65fc385e8d3ded88e3bd2776e77b51f86af06e5a Mon Sep 17 00:00:00 2001
From: Guodong Xu <guodong@riscstar.com>
Date: Thu, 15 Jan 2026 14:51:40 +0800
Subject: [PATCH 039/197] UPSTREAM: dt-bindings: riscv: add SpacemiT X100 CPU
compatible
Add compatible string for the SpacemiT X100 core. [1]
The X100 is a 64-bit RVA23-compliant RISC-V core from SpacemiT. X100
supports the RISC-V vector and hypervisor extensions and all mandatory
extersions as required by the RVA23U64 and RVA23S64 profiles, per the
definition in 'RVA23 Profile, Version 1.0'. [2]
From a microarchieture viewpoint, the X100 features a 4-issue
out-of-order pipeline.
X100 is used in SpacemiT K3 SoC.
Acked-by: Paul Walmsley <pjw@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://www.spacemit.com/en/spacemit-x100-core/ [1]
Link: https://docs.riscv.org/reference/profiles/rva23/_attachments/rva23-profile.pdf [2]
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-1-6990ac9f4308@riscstar.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
(cherry picked from commit 81a52103b90f5cddc41c34f633c014a956236abc)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index d733c0bd534f..5feeb2203050 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -61,6 +61,7 @@ properties:
- sifive,u7
- sifive,u74
- sifive,u74-mc
+ - spacemit,x100
- spacemit,x60
- thead,c906
- thead,c908
--
2.53.0

17
SPECS/linux/0146-FROMLIST-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch → SPECS/linux/0039-UPSTREAM-riscv-dts-spacemit-Add-linux-pci-domain-to-.patch
View File

@@ -1,7 +1,7 @@
From b58e745f79d4a7cc5acd9f350f795f7bda25f20a Mon Sep 17 00:00:00 2001
From 2f310982d85033ae77bd901d941f329bd545ad6d Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Mon, 9 Mar 2026 11:00:00 +0800
Subject: [PATCH 146/197] FROMLIST: riscv: dts: spacemit: Add
Subject: [PATCH 039/189] UPSTREAM: riscv: dts: spacemit: Add
'linux,pci-domain' to PCIe nodes for K1
The SpacemiT K1 SoC has 3 PCIe EP controller nodes. Add the
@@ -12,17 +12,20 @@ This creates a stable sysfs path, allowing userspace scripts
to reliably target specific PCIe devices (such as PCIe NICs).
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260309030000.1157040-1-amadeus@jmu.edu.cn
Signed-off-by: Yixun Lan <dlan@kernel.org>
(cherry picked from commit 86314111f654310a69c9775e35e263c036031675)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/spacemit/k1.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index 7e89bc53e00f..9f83dd04acc7 100644
index 529ec68e9c23..d2015201f8e5 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -1235,6 +1235,7 @@ pcie-bus {
@@ -1033,6 +1033,7 @@ pcie-bus {
#size-cells = <2>;
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
<0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>;
@@ -30,7 +33,7 @@ index 7e89bc53e00f..9f83dd04acc7 100644
pcie0: pcie@ca000000 {
device_type = "pci";
compatible = "spacemit,k1-pcie";
@@ -1246,6 +1247,7 @@ pcie0: pcie@ca000000 {
@@ -1044,6 +1045,7 @@ pcie0: pcie@ca000000 {
"atu",
"config",
"link";
@@ -38,7 +41,7 @@ index 7e89bc53e00f..9f83dd04acc7 100644
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>,
@@ -1289,6 +1291,7 @@ pcie1: pcie@ca400000 {
@@ -1087,6 +1089,7 @@ pcie1: pcie@ca400000 {
"atu",
"config",
"link";
@@ -46,7 +49,7 @@ index 7e89bc53e00f..9f83dd04acc7 100644
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>,
@@ -1332,6 +1335,7 @@ pcie2: pcie@ca800000 {
@@ -1130,6 +1133,7 @@ pcie2: pcie@ca800000 {
"atu",
"config",
"link";

12
SPECS/linux/0130-FROMLIST-dt-bindings-serial-8250-spacemit-fix-clock-.patch → SPECS/linux/0040-UPSTREAM-dt-bindings-serial-8250-spacemit-fix-clock-.patch
View File

@@ -1,23 +1,25 @@
From 81ab157ac0e9e1736c18bc84c18d22cc6b324ec0 Mon Sep 17 00:00:00 2001
From 70dcbd8f7abc63be15d0703dc573d68e22beb03c Mon Sep 17 00:00:00 2001
From: Yixun Lan <dlan@kernel.org>
Date: Wed, 4 Mar 2026 07:19:39 +0000
Subject: [PATCH 130/197] FROMLIST: dt-bindings: serial: 8250: spacemit: fix
Subject: [PATCH 040/189] UPSTREAM: dt-bindings: serial: 8250: spacemit: fix
clock property for K3 SoC
The UART of SpacemiT K3 SoC has same clock property as K1 generation which
request two clock sources, fix the binding otherwise will get DT check
warnings.
Fixes: b5024e804ee0 ("dt-bindings: serial: 8250: add SpacemiT K3 UART compatible")
Signed-off-by: Yixun Lan <dlan@kernel.org>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20260304-01-uart-clock-names-v1-1-338483f04a8b@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
(cherry picked from commit 606a6b8bca570aa4f838ddd410345a2937bd98eb)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
Documentation/devicetree/bindings/serial/8250.yaml | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml
index 167ddcbd8800..45a7f5cd9d62 100644
index 73851f19330d..e9e07c2356bc 100644
--- a/Documentation/devicetree/bindings/serial/8250.yaml
+++ b/Documentation/devicetree/bindings/serial/8250.yaml
@@ -63,7 +63,9 @@ allOf:

32
SPECS/linux/0040-UPSTREAM-dt-bindings-timer-add-SpacemiT-K3-CLINT.patch
View File

@@ -1,32 +0,0 @@
From c91ecc1b75e1a6c47765917a901bcda7f2bbabd9 Mon Sep 17 00:00:00 2001
From: Guodong Xu <guodong@riscstar.com>
Date: Thu, 15 Jan 2026 14:51:41 +0800
Subject: [PATCH 040/197] UPSTREAM: dt-bindings: timer: add SpacemiT K3 CLINT
Add compatible string for SpacemiT K3 CLINT.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-2-6990ac9f4308@riscstar.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
(cherry picked from commit 6cdeb30db4d8faf9f1fa7ab863d91d36a584716d)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index 0d3b8dc362ba..3bab40500df9 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -33,6 +33,7 @@ properties:
- eswin,eic7700-clint # ESWIN EIC7700
- sifive,fu540-c000-clint # SiFive FU540
- spacemit,k1-clint # SpacemiT K1
+ - spacemit,k3-clint # SpacemiT K3
- starfive,jh7100-clint # StarFive JH7100
- starfive,jh7110-clint # StarFive JH7110
- starfive,jh8100-clint # StarFive JH8100
--
2.53.0

33
SPECS/linux/0041-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch
View File

@@ -1,33 +0,0 @@
From 4ab8a58b0724708741c1c5d57134e7b6df20e68f Mon Sep 17 00:00:00 2001
From: Guodong Xu <guodong@riscstar.com>
Date: Thu, 15 Jan 2026 14:51:42 +0800
Subject: [PATCH 041/197] UPSTREAM: dt-bindings: interrupt-controller: add
SpacemiT K3 APLIC
Add compatible string for SpacemiT K3 APLIC.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-3-6990ac9f4308@riscstar.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
(cherry picked from commit 60490ca6d54b6f0a00223a4fe59bb180bb1538bf)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../devicetree/bindings/interrupt-controller/riscv,aplic.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
index bef00521d5da..0718071444d2 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
@@ -28,6 +28,7 @@ properties:
items:
- enum:
- qemu,aplic
+ - spacemit,k3-aplic
- const: riscv,aplic
reg:
--
2.53.0

7
SPECS/linux/0131-FROMLIST-riscv-dts-spacemit-k3-add-clock-tree.patch → SPECS/linux/0041-UPSTREAM-riscv-dts-spacemit-k3-add-clock-tree.patch
View File

@@ -1,13 +1,14 @@
From 0134901cbbe7e46c71966acfd113840cbc565379 Mon Sep 17 00:00:00 2001
From dcc4c02754e361ca35e9087c868b09e11db86713 Mon Sep 17 00:00:00 2001
From: Yixun Lan <dlan@kernel.org>
Date: Wed, 4 Mar 2026 07:36:42 +0000
Subject: [PATCH 131/197] FROMLIST: riscv: dts: spacemit: k3: add clock tree
Subject: [PATCH 041/189] UPSTREAM: riscv: dts: spacemit: k3: add clock tree
Add clock support to SpacemiT K3 SoC, the clock tree consist of several
blocks which are APBC, APMU, DCIU, MPUM.
Signed-off-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-1-50a0aa53a245@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
(cherry picked from commit 67072c8cd48c1fbb95cea39239eba5526395fcf5)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/spacemit/k3.dtsi | 75 ++++++++++++++++++++++++++++

33
SPECS/linux/0042-UPSTREAM-dt-bindings-interrupt-controller-add-Spacem.patch
View File

@@ -1,33 +0,0 @@
From ccf8e224cf51b3d541a238e3693959599135a32f Mon Sep 17 00:00:00 2001
From: Guodong Xu <guodong@riscstar.com>
Date: Thu, 15 Jan 2026 14:51:43 +0800
Subject: [PATCH 042/197] UPSTREAM: dt-bindings: interrupt-controller: add
SpacemiT K3 IMSIC
Add compatible string for SpacemiT K3 IMSIC.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-4-6990ac9f4308@riscstar.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
(cherry picked from commit a716729a3ce1055efab477030235777d2be0852b)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
.../devicetree/bindings/interrupt-controller/riscv,imsics.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
index c23b5c09fdb9..feec122bddde 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
@@ -48,6 +48,7 @@ properties:
items:
- enum:
- qemu,imsics
+ - spacemit,k3-imsics
- const: riscv,imsics
reg:
--
2.53.0

7
SPECS/linux/0132-FROMLIST-riscv-dts-spacemit-k3-add-pinctrl-support.patch → SPECS/linux/0042-UPSTREAM-riscv-dts-spacemit-k3-add-pinctrl-support.patch
View File

@@ -1,14 +1,15 @@
From b1067acb327782e4dd406ca251cf3749b8649e0c Mon Sep 17 00:00:00 2001
From b417e6639f8bba519619ada091beec04bcc8b6ad Mon Sep 17 00:00:00 2001
From: Yixun Lan <dlan@kernel.org>
Date: Wed, 4 Mar 2026 07:36:43 +0000
Subject: [PATCH 132/197] FROMLIST: riscv: dts: spacemit: k3: add pinctrl
Subject: [PATCH 042/189] UPSTREAM: riscv: dts: spacemit: k3: add pinctrl
support
Populate pinctrl node in Device Tree for SpacemiT K3 SoC, So devices
can request pinctrl resource properly.
Signed-off-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-2-50a0aa53a245@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
(cherry picked from commit d8944577496b5b99061d3b2020704fc86ab1f9e6)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/spacemit/k3.dtsi | 8 ++++++++

46
SPECS/linux/0043-UPSTREAM-dt-bindings-riscv-spacemit-add-K3-and-Pico-.patch
View File

@@ -1,46 +0,0 @@
From c89679509c0c7cb5eea6b374b3c594a96391c350 Mon Sep 17 00:00:00 2001
From: Guodong Xu <guodong@riscstar.com>
Date: Thu, 15 Jan 2026 14:51:44 +0800
Subject: [PATCH 043/197] UPSTREAM: dt-bindings: riscv: spacemit: add K3 and
Pico-ITX board bindings
Add DT binding documentation for the SpacemiT K3 SoC and the board Pico-ITX
which is a 2.5-inch single-board computer.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-5-6990ac9f4308@riscstar.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
(cherry picked from commit 7cb5fafc180f6e188af7943d6b162051f22490fc)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
Documentation/devicetree/bindings/riscv/spacemit.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml
index 9c49482002f7..b958b94a924d 100644
--- a/Documentation/devicetree/bindings/riscv/spacemit.yaml
+++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml
@@ -7,6 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: SpacemiT SoC-based boards
maintainers:
+ - Guodong Xu <guodong@riscstar.com>
- Yangyu Chen <cyy@cyyself.name>
- Yixun Lan <dlan@gentoo.org>
@@ -26,6 +27,10 @@ properties:
- xunlong,orangepi-r2s
- xunlong,orangepi-rv2
- const: spacemit,k1
+ - items:
+ - enum:
+ - spacemit,k3-pico-itx
+ - const: spacemit,k3
additionalProperties: true
--
2.53.0

7
SPECS/linux/0133-FROMLIST-riscv-dts-spacemit-k3-add-GPIO-support.patch → SPECS/linux/0043-UPSTREAM-riscv-dts-spacemit-k3-add-GPIO-support.patch
View File

@@ -1,13 +1,14 @@
From 32a9039479a485b029a1a5a12042f3f4133e73ce Mon Sep 17 00:00:00 2001
From a5c52113515a6e54f7db974edcf6d18addf58c1b Mon Sep 17 00:00:00 2001
From: Yixun Lan <dlan@kernel.org>
Date: Wed, 4 Mar 2026 07:36:44 +0000
Subject: [PATCH 133/197] FROMLIST: riscv: dts: spacemit: k3: add GPIO support
Subject: [PATCH 043/189] UPSTREAM: riscv: dts: spacemit: k3: add GPIO support
Add GPIO node in the Device Tree, so devices are able to request GPIO
resource properly.
Signed-off-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-3-50a0aa53a245@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
(cherry picked from commit 20b77926864203e10b85af5276b17c2812d92ec1)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/spacemit/k3.dtsi | 18 ++++++++++++++++++

608
SPECS/linux/0044-UPSTREAM-riscv-dts-spacemit-add-initial-support-for-.patch
View File

@@ -1,608 +0,0 @@
From 43a1eafba55d7d69ce30744ac6962eebea2ce1d6 Mon Sep 17 00:00:00 2001
From: Guodong Xu <guodong@riscstar.com>
Date: Thu, 15 Jan 2026 14:51:45 +0800
Subject: [PATCH 044/197] UPSTREAM: riscv: dts: spacemit: add initial support
for K3 SoC
SpacemiT K3 is equipped with 8 X100 cores, which are RVA23 compliant.
Add nodes of uarts, timer and interrupt-controllers. Also add M-mode
APLIC (maplic) and IMSIC (mimsic) nodes to represent the hardware
topology and ready for potential firmware usage.
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-6-6990ac9f4308@riscstar.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
(cherry picked from commit 56f37e391a626f964615ee5939710eff212b621f)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/spacemit/k3.dtsi | 578 +++++++++++++++++++++++++++
1 file changed, 578 insertions(+)
create mode 100644 arch/riscv/boot/dts/spacemit/k3.dtsi
diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
new file mode 100644
index 000000000000..b69cf81b5d55
--- /dev/null
+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
@@ -0,0 +1,578 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd
+ * Copyright (c) 2026 Guodong Xu <guodong@riscstar.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/dts-v1/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "SpacemiT K3";
+ compatible = "spacemit,k3";
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <24000000>;
+
+ cpu_0: cpu@0 {
+ compatible = "spacemit,x100", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+ "sha", "shcounterenw", "shgatpa", "shtvala",
+ "shvsatpa", "shvstvala", "shvstvecd", "smaia",
+ "smstateen", "ssaia", "ssccptr", "sscofpmf",
+ "sscounterenw", "ssnpm", "ssstateen", "sstc",
+ "sstvala", "sstvecd", "ssu64xl", "svade",
+ "svinval", "svnapot", "svpbmt", "za64rs",
+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
+ "ziccamoa", "ziccif", "zicclsm", "zicntr",
+ "zicond", "zicsr", "zifencei", "zihintntl",
+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <256>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache0>;
+ mmu-type = "riscv,sv39";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu_1: cpu@1 {
+ compatible = "spacemit,x100", "riscv";
+ device_type = "cpu";
+ reg = <1>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+ "sha", "shcounterenw", "shgatpa", "shtvala",
+ "shvsatpa", "shvstvala", "shvstvecd", "smaia",
+ "smstateen", "ssaia", "ssccptr", "sscofpmf",
+ "sscounterenw", "ssnpm", "ssstateen", "sstc",
+ "sstvala", "sstvecd", "ssu64xl", "svade",
+ "svinval", "svnapot", "svpbmt", "za64rs",
+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
+ "ziccamoa", "ziccif", "zicclsm", "zicntr",
+ "zicond", "zicsr", "zifencei", "zihintntl",
+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <256>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache0>;
+ mmu-type = "riscv,sv39";
+
+ cpu1_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu_2: cpu@2 {
+ compatible = "spacemit,x100", "riscv";
+ device_type = "cpu";
+ reg = <2>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+ "sha", "shcounterenw", "shgatpa", "shtvala",
+ "shvsatpa", "shvstvala", "shvstvecd", "smaia",
+ "smstateen", "ssaia", "ssccptr", "sscofpmf",
+ "sscounterenw", "ssnpm", "ssstateen", "sstc",
+ "sstvala", "sstvecd", "ssu64xl", "svade",
+ "svinval", "svnapot", "svpbmt", "za64rs",
+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
+ "ziccamoa", "ziccif", "zicclsm", "zicntr",
+ "zicond", "zicsr", "zifencei", "zihintntl",
+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <256>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache0>;
+ mmu-type = "riscv,sv39";
+
+ cpu2_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu_3: cpu@3 {
+ compatible = "spacemit,x100", "riscv";
+ device_type = "cpu";
+ reg = <3>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+ "sha", "shcounterenw", "shgatpa", "shtvala",
+ "shvsatpa", "shvstvala", "shvstvecd", "smaia",
+ "smstateen", "ssaia", "ssccptr", "sscofpmf",
+ "sscounterenw", "ssnpm", "ssstateen", "sstc",
+ "sstvala", "sstvecd", "ssu64xl", "svade",
+ "svinval", "svnapot", "svpbmt", "za64rs",
+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
+ "ziccamoa", "ziccif", "zicclsm", "zicntr",
+ "zicond", "zicsr", "zifencei", "zihintntl",
+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <256>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache0>;
+ mmu-type = "riscv,sv39";
+
+ cpu3_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu_4: cpu@4 {
+ compatible = "spacemit,x100", "riscv";
+ device_type = "cpu";
+ reg = <4>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+ "sha", "shcounterenw", "shgatpa", "shtvala",
+ "shvsatpa", "shvstvala", "shvstvecd", "smaia",
+ "smstateen", "ssaia", "ssccptr", "sscofpmf",
+ "sscounterenw", "ssnpm", "ssstateen", "sstc",
+ "sstvala", "sstvecd", "ssu64xl", "svade",
+ "svinval", "svnapot", "svpbmt", "za64rs",
+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
+ "ziccamoa", "ziccif", "zicclsm", "zicntr",
+ "zicond", "zicsr", "zifencei", "zihintntl",
+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <256>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache1>;
+ mmu-type = "riscv,sv39";
+
+ cpu4_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu_5: cpu@5 {
+ compatible = "spacemit,x100", "riscv";
+ device_type = "cpu";
+ reg = <5>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+ "sha", "shcounterenw", "shgatpa", "shtvala",
+ "shvsatpa", "shvstvala", "shvstvecd", "smaia",
+ "smstateen", "ssaia", "ssccptr", "sscofpmf",
+ "sscounterenw", "ssnpm", "ssstateen", "sstc",
+ "sstvala", "sstvecd", "ssu64xl", "svade",
+ "svinval", "svnapot", "svpbmt", "za64rs",
+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
+ "ziccamoa", "ziccif", "zicclsm", "zicntr",
+ "zicond", "zicsr", "zifencei", "zihintntl",
+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <256>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache1>;
+ mmu-type = "riscv,sv39";
+
+ cpu5_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu_6: cpu@6 {
+ compatible = "spacemit,x100", "riscv";
+ device_type = "cpu";
+ reg = <6>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+ "sha", "shcounterenw", "shgatpa", "shtvala",
+ "shvsatpa", "shvstvala", "shvstvecd", "smaia",
+ "smstateen", "ssaia", "ssccptr", "sscofpmf",
+ "sscounterenw", "ssnpm", "ssstateen", "sstc",
+ "sstvala", "sstvecd", "ssu64xl", "svade",
+ "svinval", "svnapot", "svpbmt", "za64rs",
+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
+ "ziccamoa", "ziccif", "zicclsm", "zicntr",
+ "zicond", "zicsr", "zifencei", "zihintntl",
+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <256>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache1>;
+ mmu-type = "riscv,sv39";
+
+ cpu6_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu_7: cpu@7 {
+ compatible = "spacemit,x100", "riscv";
+ device_type = "cpu";
+ reg = <7>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h",
+ "sha", "shcounterenw", "shgatpa", "shtvala",
+ "shvsatpa", "shvstvala", "shvstvecd", "smaia",
+ "smstateen", "ssaia", "ssccptr", "sscofpmf",
+ "sscounterenw", "ssnpm", "ssstateen", "sstc",
+ "sstvala", "sstvecd", "ssu64xl", "svade",
+ "svinval", "svnapot", "svpbmt", "za64rs",
+ "zawrs", "zba", "zbb", "zbc", "zbs", "zca",
+ "zcb", "zcd", "zcmop", "zfa", "zfbfmin",
+ "zfh", "zfhmin", "zicbom", "zicbop", "zicboz",
+ "ziccamoa", "ziccif", "zicclsm", "zicntr",
+ "zicond", "zicsr", "zifencei", "zihintntl",
+ "zihintpause", "zihpm", "zimop", "zkt", "zvbb",
+ "zvbc", "zvfbfmin", "zvfbfwma", "zvfh",
+ "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc",
+ "zvkned", "zvkng", "zvknha", "zvknhb", "zvks",
+ "zvksc", "zvksed", "zvksg", "zvksh", "zvkt";
+ riscv,cbom-block-size = <64>;
+ riscv,cbop-block-size = <64>;
+ riscv,cboz-block-size = <64>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <256>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_cache1>;
+ mmu-type = "riscv,sv39";
+
+ cpu7_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ l2_cache0: cache-controller-0 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <4194304>;
+ cache-sets = <4096>;
+ cache-unified;
+ };
+
+ l2_cache1: cache-controller-1 {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <4194304>;
+ cache-sets = <4096>;
+ cache-unified;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu_0>;
+ };
+ core1 {
+ cpu = <&cpu_1>;
+ };
+ core2 {
+ cpu = <&cpu_2>;
+ };
+ core3 {
+ cpu = <&cpu_3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu_4>;
+ };
+ core1 {
+ cpu = <&cpu_5>;
+ };
+ core2 {
+ cpu = <&cpu_6>;
+ };
+ core3 {
+ cpu = <&cpu_7>;
+ };
+ };
+ };
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&saplic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-noncoherent;
+ ranges;
+
+ uart0: serial@d4017000 {
+ compatible = "spacemit,k3-uart", "intel,xscale-uart";
+ reg = <0x0 0xd4017000 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <14700000>;
+ interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart2: serial@d4017100 {
+ compatible = "spacemit,k3-uart", "intel,xscale-uart";
+ reg = <0x0 0xd4017100 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <14700000>;
+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart3: serial@d4017200 {
+ compatible = "spacemit,k3-uart", "intel,xscale-uart";
+ reg = <0x0 0xd4017200 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <14700000>;
+ interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart4: serial@d4017300 {
+ compatible = "spacemit,k3-uart", "intel,xscale-uart";
+ reg = <0x0 0xd4017300 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <14700000>;
+ interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart5: serial@d4017400 {
+ compatible = "spacemit,k3-uart", "intel,xscale-uart";
+ reg = <0x0 0xd4017400 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <14700000>;
+ interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart6: serial@d4017500 {
+ compatible = "spacemit,k3-uart", "intel,xscale-uart";
+ reg = <0x0 0xd4017500 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <14700000>;
+ interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart7: serial@d4017600 {
+ compatible = "spacemit,k3-uart", "intel,xscale-uart";
+ reg = <0x0 0xd4017600 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <14700000>;
+ interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart8: serial@d4017700 {
+ compatible = "spacemit,k3-uart", "intel,xscale-uart";
+ reg = <0x0 0xd4017700 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <14700000>;
+ interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart9: serial@d4017800 {
+ compatible = "spacemit,k3-uart", "intel,xscale-uart";
+ reg = <0x0 0xd4017800 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <14700000>;
+ interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart10: serial@d401f000 {
+ compatible = "spacemit,k3-uart", "intel,xscale-uart";
+ reg = <0x0 0xd401f000 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <14700000>;
+ interrupts = <281 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ simsic: interrupt-controller@e0400000 {
+ compatible = "spacemit,k3-imsics", "riscv,imsics";
+ reg = <0x0 0xe0400000 0x0 0x200000>;
+ #interrupt-cells = <0>;
+ #msi-cells = <0>;
+ interrupt-controller;
+ interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>,
+ <&cpu2_intc 9>, <&cpu3_intc 9>,
+ <&cpu4_intc 9>, <&cpu5_intc 9>,
+ <&cpu6_intc 9>, <&cpu7_intc 9>;
+ msi-controller;
+ riscv,guest-index-bits = <6>;
+ riscv,hart-index-bits = <4>;
+ riscv,num-guest-ids = <511>;
+ riscv,num-ids = <511>;
+ };
+
+ saplic: interrupt-controller@e0804000 {
+ compatible = "spacemit,k3-aplic", "riscv,aplic";
+ reg = <0x0 0xe0804000 0x0 0x4000>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ msi-parent = <&simsic>;
+ riscv,num-sources = <512>;
+ };
+
+ clint: timer@e081c000 {
+ compatible = "spacemit,k3-clint", "sifive,clint0";
+ reg = <0x0 0xe081c000 0x0 0x4000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+ <&cpu1_intc 3>, <&cpu1_intc 7>,
+ <&cpu2_intc 3>, <&cpu2_intc 7>,
+ <&cpu3_intc 3>, <&cpu3_intc 7>,
+ <&cpu4_intc 3>, <&cpu4_intc 7>,
+ <&cpu5_intc 3>, <&cpu5_intc 7>,
+ <&cpu6_intc 3>, <&cpu6_intc 7>,
+ <&cpu7_intc 3>, <&cpu7_intc 7>;
+ };
+
+ mimsic: interrupt-controller@f1000000 {
+ compatible = "spacemit,k3-imsics", "riscv,imsics";
+ reg = <0x0 0xf1000000 0x0 0x10000>;
+ #interrupt-cells = <0>;
+ #msi-cells = <0>;
+ interrupt-controller;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>,
+ <&cpu2_intc 11>, <&cpu3_intc 11>,
+ <&cpu4_intc 11>, <&cpu5_intc 11>,
+ <&cpu6_intc 11>, <&cpu7_intc 11>;
+ msi-controller;
+ riscv,guest-index-bits = <6>;
+ riscv,hart-index-bits = <4>;
+ riscv,num-guest-ids = <511>;
+ riscv,num-ids = <511>;
+ status = "reserved";
+ };
+
+ maplic: interrupt-controller@f1800000 {
+ compatible = "spacemit,k3-aplic", "riscv,aplic";
+ reg = <0x0 0xf1800000 0x0 0x4000>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ msi-parent = <&mimsic>;
+ riscv,children = <&saplic>;
+ riscv,delegation = <&saplic 1 512>;
+ riscv,num-sources = <512>;
+ status = "reserved";
+ };
+ };
+};
--
2.53.0

7
SPECS/linux/0134-FROMLIST-riscv-dts-spacemit-k3-add-full-resource-to-.patch → SPECS/linux/0044-UPSTREAM-riscv-dts-spacemit-k3-add-full-resource-to-.patch
View File

@@ -1,15 +1,16 @@
From fbcb2204dd939bf889dfc7d9a23718479f035f54 Mon Sep 17 00:00:00 2001
From 8b66fcbc9725abd2131aa4094638285293700f35 Mon Sep 17 00:00:00 2001
From: Yixun Lan <dlan@kernel.org>
Date: Wed, 4 Mar 2026 07:36:45 +0000
Subject: [PATCH 134/197] FROMLIST: riscv: dts: spacemit: k3: add full resource
Subject: [PATCH 044/189] UPSTREAM: riscv: dts: spacemit: k3: add full resource
to UART
Previously the UART rely on external bootloader to initialize clock,
pinctrl and reset, to solve this, explicitly adding those resource in
Device Tree, so UART driver will handle them properly.
Signed-off-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260304-01-dts-uart-full-v1-4-50a0aa53a245@kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
(cherry picked from commit 28a7f755d7c9a4b9c41c12620fb4885f39b554ad)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 3 ++

9
SPECS/linux/0169-FROMLIST-dt-bindings-usb-dwc3-spacemit-add-support-f.patch → SPECS/linux/0045-UPSTREAM-dt-bindings-usb-dwc3-spacemit-add-support-f.patch
View File

@@ -1,7 +1,7 @@
From 9972baac6d447c928fc7cd6578d534f4086bb228 Mon Sep 17 00:00:00 2001
From 931cd12835a83873f114827eec919335181df7af Mon Sep 17 00:00:00 2001
From: Yixun Lan <dlan@kernel.org>
Date: Fri, 20 Mar 2026 07:15:37 +0000
Subject: [PATCH 169/197] FROMLIST: dt-bindings: usb: dwc3: spacemit: add
Subject: [PATCH 045/189] UPSTREAM: dt-bindings: usb: dwc3: spacemit: add
support for K3 SoC
Add compatible string for DWC3 USB controller found in SpacemiT K3 SoC.
@@ -16,7 +16,10 @@ and K3 SoC are able to work in the USB2.0 mode which requires one PHY.
Explicitly reduce number of phy property to minimal one.
Signed-off-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260320-02-k3-usb20-support-v2-1-308ea0e44038@kernel.org
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20260320-02-k3-usb20-support-v2-1-308ea0e44038@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit e7e86965a69d0f6797116e54dda01b56deca71c0)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 6 +++++-

70
SPECS/linux/0045-UPSTREAM-riscv-dts-spacemit-add-K3-Pico-ITX-board-su.patch
View File

@@ -1,70 +0,0 @@
From 137decdbbfa3b25dffa616d83de89e8b17664d45 Mon Sep 17 00:00:00 2001
From: Guodong Xu <guodong@riscstar.com>
Date: Thu, 15 Jan 2026 14:51:46 +0800
Subject: [PATCH 045/197] UPSTREAM: riscv: dts: spacemit: add K3 Pico-ITX board
support
K3 Pico-ITX is a 2.5-inch single-board computer equipted with a SpacemiT
K3 SoC.
This minimal device tree enables booting into a serial console with UART
output.
Signed-off-by: Guodong Xu <guodong@riscstar.com>
Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-7-6990ac9f4308@riscstar.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
(cherry picked from commit 7a61318049861b777f098d7148d892d7dc79b010)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/spacemit/Makefile | 1 +
arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 29 ++++++++++++++++++++
2 files changed, 30 insertions(+)
create mode 100644 arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile
index 95889e7269d1..7e2b87702571 100644
--- a/arch/riscv/boot/dts/spacemit/Makefile
+++ b/arch/riscv/boot/dts/spacemit/Makefile
@@ -4,3 +4,4 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb
dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb
dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb
dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb
+dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb
diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
new file mode 100644
index 000000000000..b691304d4b74
--- /dev/null
+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd
+ * Copyright (c) 2026 Guodong Xu <guodong@riscstar.com>
+ */
+
+#include "k3.dtsi"
+
+/ {
+ model = "SpacemiT K3 Pico-ITX";
+ compatible = "spacemit,k3-pico-itx", "spacemit,k3";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ memory@100000000 {
+ device_type = "memory";
+ reg = <0x1 0x00000000 0x4 0x00000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
--
2.53.0

53
SPECS/linux/0046-UPSTREAM-clk-spacemit-Hide-common-clock-driver-from-.patch
View File

@@ -1,53 +0,0 @@
From f6fce6c9b52f3606b9c9072e435d90b61da41bb4 Mon Sep 17 00:00:00 2001
From: Inochi Amaoto <inochiama@gmail.com>
Date: Fri, 19 Dec 2025 09:28:18 +0800
Subject: [PATCH 046/197] UPSTREAM: clk: spacemit: Hide common clock driver
from user controller
Since the common clock driver is only a dependency for other spacemit
clock driver, it should not be enabled individually, so hide this in
the Kconfig UI and let other spacemit clock driver select it.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Yixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20251219012819.440972-3-inochiama@gmail.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
(cherry picked from commit 99735a742f7e9a3e7f4cb6c58edf1b38101e7657)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/clk/spacemit/Kconfig | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/spacemit/Kconfig b/drivers/clk/spacemit/Kconfig
index 3854f6ae6d0e..3351e8bc801d 100644
--- a/drivers/clk/spacemit/Kconfig
+++ b/drivers/clk/spacemit/Kconfig
@@ -1,19 +1,17 @@
# SPDX-License-Identifier: GPL-2.0-only
-config SPACEMIT_CCU
- tristate "Clock support for SpacemiT SoCs"
+menu "Clock support for SpacemiT platforms"
depends on ARCH_SPACEMIT || COMPILE_TEST
+
+config SPACEMIT_CCU
+ tristate
select AUXILIARY_BUS
select MFD_SYSCON
- help
- Say Y to enable clock controller unit support for SpacemiT SoCs.
-
-if SPACEMIT_CCU
config SPACEMIT_K1_CCU
tristate "Support for SpacemiT K1 SoC"
- depends on ARCH_SPACEMIT || COMPILE_TEST
+ select SPACEMIT_CCU
help
Support for clock controller unit in SpacemiT K1 SoC.
-endif
+endmenu
--
2.53.0

8
SPECS/linux/0170-FROMLIST-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch → SPECS/linux/0046-UPSTREAM-usb-dwc3-dwc3-generic-plat-spacemit-add-sup.patch
View File

@@ -1,14 +1,16 @@
From 7e58dee2e02c8afaf7efd5c5f0ca9613b7049245 Mon Sep 17 00:00:00 2001
From 0389d01cd6770f6ce883ceb81e1c7e36f3f8afb2 Mon Sep 17 00:00:00 2001
From: Yixun Lan <dlan@kernel.org>
Date: Fri, 20 Mar 2026 07:15:38 +0000
Subject: [PATCH 170/197] FROMLIST: usb: dwc3: dwc3-generic-plat: spacemit: add
Subject: [PATCH 046/189] UPSTREAM: usb: dwc3: dwc3-generic-plat: spacemit: add
support for K3 SoC
Add support for the DWC3 USB controller which found in SpacemiT K3 SoC.
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Signed-off-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260320-02-k3-usb20-support-v2-2-308ea0e44038@kernel.org
Link: https://patch.msgid.link/20260320-02-k3-usb20-support-v2-2-308ea0e44038@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit c05cf9d274daf72dc7e433480cf2e0e888f6bd89)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/usb/dwc3/dwc3-generic-plat.c | 1 +

73
SPECS/linux/0047-UPSTREAM-clk-spacemit-prepare-common-ccu-header.patch
View File

@@ -1,73 +0,0 @@
From 698523c2a0854291770439c28fcd4b6cdcee4d54 Mon Sep 17 00:00:00 2001
From: Yixun Lan <dlan@gentoo.org>
Date: Fri, 19 Dec 2025 21:52:08 +0800
Subject: [PATCH 047/197] UPSTREAM: clk: spacemit: prepare common ccu header
In order to prepare adding clock driver for new K3 SoC, extract generic
code to a separate common ccu header file, so they are not defined
in K1 SoC-specific file, and then can be shared by all clock drivers.
Link: https://lore.kernel.org/r/20260108-06-k1-clk-common-v4-1-badf635993d3@gentoo.org
Reviewed-by: Alex Elder <elder@riscstar.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
(cherry picked from commit 2b7a02c322922a37cc5fc15d055b794cc2193062)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
include/soc/spacemit/ccu.h | 21 +++++++++++++++++++++
include/soc/spacemit/k1-syscon.h | 12 +-----------
2 files changed, 22 insertions(+), 11 deletions(-)
create mode 100644 include/soc/spacemit/ccu.h
diff --git a/include/soc/spacemit/ccu.h b/include/soc/spacemit/ccu.h
new file mode 100644
index 000000000000..84dcdecccc05
--- /dev/null
+++ b/include/soc/spacemit/ccu.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_SPACEMIT_CCU_H__
+#define __SOC_SPACEMIT_CCU_H__
+
+#include <linux/auxiliary_bus.h>
+#include <linux/regmap.h>
+
+/* Auxiliary device used to represent a CCU reset controller */
+struct spacemit_ccu_adev {
+ struct auxiliary_device adev;
+ struct regmap *regmap;
+};
+
+static inline struct spacemit_ccu_adev *
+to_spacemit_ccu_adev(struct auxiliary_device *adev)
+{
+ return container_of(adev, struct spacemit_ccu_adev, adev);
+}
+
+#endif /* __SOC_SPACEMIT_CCU_H__ */
diff --git a/include/soc/spacemit/k1-syscon.h b/include/soc/spacemit/k1-syscon.h
index 354751562c55..0be7a2e8d445 100644
--- a/include/soc/spacemit/k1-syscon.h
+++ b/include/soc/spacemit/k1-syscon.h
@@ -5,17 +5,7 @@
#ifndef __SOC_K1_SYSCON_H__
#define __SOC_K1_SYSCON_H__
-/* Auxiliary device used to represent a CCU reset controller */
-struct spacemit_ccu_adev {
- struct auxiliary_device adev;
- struct regmap *regmap;
-};
-
-static inline struct spacemit_ccu_adev *
-to_spacemit_ccu_adev(struct auxiliary_device *adev)
-{
- return container_of(adev, struct spacemit_ccu_adev, adev);
-}
+#include "ccu.h"
/* APBS register offset */
#define APBS_PLL1_SWCR1 0x100
--
2.53.0

34
SPECS/linux/0172-FROMLIST-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch → SPECS/linux/0047-UPSTREAM-usb-dwc3-Add-optional-VBUS-regulator-suppor.patch
View File

@@ -1,7 +1,7 @@
From 8bbd9433ee23bcb7a19420aa2bcfc89d1ec6adeb Mon Sep 17 00:00:00 2001
From ed5a8e4f7467acf07ddfa577267b419196568dc4 Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Fri, 20 Mar 2026 18:01:20 +0800
Subject: [PATCH 172/197] FROMLIST: usb: dwc3: Add optional VBUS regulator
Date: Thu, 26 Mar 2026 18:00:10 +0800
Subject: [PATCH 047/189] UPSTREAM: usb: dwc3: Add optional VBUS regulator
support to SpacemiT K1
Some SpacemiT K1 boards (like OrangePi R2S) provide USB VBUS
@@ -14,14 +14,18 @@ The enabled and disabled actions of the regulator are handled
automatically by devm_regulator_get_enable_optional().
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20260320100120.1343629-2-amadeus@jmu.edu.cn
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Link: https://patch.msgid.link/20260326100010.3588454-2-amadeus@jmu.edu.cn
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
(cherry picked from commit 764c2e6e60bf17910d84e7179fee14129e053b96)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/usb/dwc3/dwc3-generic-plat.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
drivers/usb/dwc3/dwc3-generic-plat.c | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c
index 28219968b8b0..cadd101a6382 100644
index 28219968b8b0..69b7e6227b3b 100644
--- a/drivers/usb/dwc3/dwc3-generic-plat.c
+++ b/drivers/usb/dwc3/dwc3-generic-plat.c
@@ -12,6 +12,8 @@
@@ -54,23 +58,27 @@ index 28219968b8b0..cadd101a6382 100644
static int dwc3_generic_probe(struct platform_device *pdev)
{
const struct dwc3_generic_config *plat_config;
@@ -210,11 +226,15 @@ static const struct dwc3_generic_config eic7700_dwc3 = {
.properties = DWC3_DEFAULT_PROPERTIES,
@@ -201,6 +217,11 @@ static const struct dev_pm_ops dwc3_generic_dev_pm_ops = {
dwc3_generic_runtime_idle)
};
+static const struct dwc3_generic_config spacemit_k1_dwc3 = {
+ .init = dwc3_spacemit_k1_init,
+ .properties = DWC3_DEFAULT_PROPERTIES,
+};
+
static const struct dwc3_generic_config fsl_ls1028_dwc3 = {
.properties.gsbuscfg0_reqinfo = 0x2222,
};
@@ -211,7 +232,7 @@ static const struct dwc3_generic_config eic7700_dwc3 = {
};
static const struct of_device_id dwc3_generic_of_match[] = {
- { .compatible = "spacemit,k1-dwc3", },
+ { .compatible = "spacemit,k1-dwc3", &spacemit_k1_dwc3},
{ .compatible = "spacemit,k3-dwc3", },
{ .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3},
{ .compatible = "eswin,eic7700-dwc3", &eic7700_dwc3},
+ { .compatible = "spacemit,k1-dwc3", &spacemit_k1_dwc3},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, dwc3_generic_of_match);
--
2.53.0

463
SPECS/linux/0048-UPSTREAM-clk-spacemit-extract-common-ccu-functions.patch
View File

@@ -1,463 +0,0 @@
From a27b70287b7022b0394ae8d546a15f37739d16d2 Mon Sep 17 00:00:00 2001
From: Yixun Lan <dlan@gentoo.org>
Date: Fri, 19 Dec 2025 08:07:23 +0800
Subject: [PATCH 048/197] UPSTREAM: clk: spacemit: extract common ccu functions
Refactor the probe function of SpacemiT's clock, and extract a common ccu
file, so new clock driver added in the future can share the same code,
which would lower the burden of maintenance. Since this commit changes the
module name from spacemit_ccu_k1 to spacemit_ccu where the auxiliary device
registered, the auxiliary device id need to be adjusted. Idea of the patch
comes from the review of K3 clock driver, please refer to this disucssion[1]
for more detail.
This change will introduce a runtime break to reset driver, and will be
fixed in follow-up commit:
ecff77f7c041 ("reset: spacemit: fix auxiliary device id")
Link: https://lore.kernel.org/all/aTo8sCPpVM1o9PKX@pie/ [1]
Link: https://lore.kernel.org/r/20260108-06-k1-clk-common-v4-2-badf635993d3@gentoo.org
Suggested-by: Yao Zi <me@ziyao.cc>
Reviewed-by: Alex Elder <elder@riscstar.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
(cherry picked from commit 99669468d24ce21be12f3751e7381c47ab2c9ecd)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/clk/spacemit/ccu-k1.c | 179 +-----------------------------
drivers/clk/spacemit/ccu_common.c | 171 ++++++++++++++++++++++++++++
drivers/clk/spacemit/ccu_common.h | 10 ++
3 files changed, 186 insertions(+), 174 deletions(-)
diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c
index 01d9485b615d..02c792a73759 100644
--- a/drivers/clk/spacemit/ccu-k1.c
+++ b/drivers/clk/spacemit/ccu-k1.c
@@ -5,15 +5,10 @@
*/
#include <linux/array_size.h>
-#include <linux/auxiliary_bus.h>
#include <linux/clk-provider.h>
-#include <linux/delay.h>
-#include <linux/idr.h>
-#include <linux/mfd/syscon.h>
#include <linux/minmax.h>
#include <linux/module.h>
#include <linux/platform_device.h>
-#include <linux/slab.h>
#include <soc/spacemit/k1-syscon.h>
#include "ccu_common.h"
@@ -23,14 +18,6 @@
#include <dt-bindings/clock/spacemit,k1-syscon.h>
-struct spacemit_ccu_data {
- const char *reset_name;
- struct clk_hw **hws;
- size_t num;
-};
-
-static DEFINE_IDA(auxiliary_ids);
-
/* APBS clocks start, APBS region contains and only contains all PLL clocks */
/*
@@ -1001,167 +988,6 @@ static const struct spacemit_ccu_data k1_ccu_apbc2_data = {
.reset_name = "apbc2-reset",
};
-static int spacemit_ccu_register(struct device *dev,
- struct regmap *regmap,
- struct regmap *lock_regmap,
- const struct spacemit_ccu_data *data)
-{
- struct clk_hw_onecell_data *clk_data;
- int i, ret;
-
- /* Nothing to do if the CCU does not implement any clocks */
- if (!data->hws)
- return 0;
-
- clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->num),
- GFP_KERNEL);
- if (!clk_data)
- return -ENOMEM;
-
- clk_data->num = data->num;
-
- for (i = 0; i < data->num; i++) {
- struct clk_hw *hw = data->hws[i];
- struct ccu_common *common;
- const char *name;
-
- if (!hw) {
- clk_data->hws[i] = ERR_PTR(-ENOENT);
- continue;
- }
-
- name = hw->init->name;
-
- common = hw_to_ccu_common(hw);
- common->regmap = regmap;
- common->lock_regmap = lock_regmap;
-
- ret = devm_clk_hw_register(dev, hw);
- if (ret) {
- dev_err(dev, "Cannot register clock %d - %s\n",
- i, name);
- return ret;
- }
-
- clk_data->hws[i] = hw;
- }
-
- ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
- if (ret)
- dev_err(dev, "failed to add clock hardware provider (%d)\n", ret);
-
- return ret;
-}
-
-static void spacemit_cadev_release(struct device *dev)
-{
- struct auxiliary_device *adev = to_auxiliary_dev(dev);
-
- ida_free(&auxiliary_ids, adev->id);
- kfree(to_spacemit_ccu_adev(adev));
-}
-
-static void spacemit_adev_unregister(void *data)
-{
- struct auxiliary_device *adev = data;
-
- auxiliary_device_delete(adev);
- auxiliary_device_uninit(adev);
-}
-
-static int spacemit_ccu_reset_register(struct device *dev,
- struct regmap *regmap,
- const char *reset_name)
-{
- struct spacemit_ccu_adev *cadev;
- struct auxiliary_device *adev;
- int ret;
-
- /* Nothing to do if the CCU does not implement a reset controller */
- if (!reset_name)
- return 0;
-
- cadev = kzalloc(sizeof(*cadev), GFP_KERNEL);
- if (!cadev)
- return -ENOMEM;
-
- cadev->regmap = regmap;
-
- adev = &cadev->adev;
- adev->name = reset_name;
- adev->dev.parent = dev;
- adev->dev.release = spacemit_cadev_release;
- adev->dev.of_node = dev->of_node;
- ret = ida_alloc(&auxiliary_ids, GFP_KERNEL);
- if (ret < 0)
- goto err_free_cadev;
- adev->id = ret;
-
- ret = auxiliary_device_init(adev);
- if (ret)
- goto err_free_aux_id;
-
- ret = auxiliary_device_add(adev);
- if (ret) {
- auxiliary_device_uninit(adev);
- return ret;
- }
-
- return devm_add_action_or_reset(dev, spacemit_adev_unregister, adev);
-
-err_free_aux_id:
- ida_free(&auxiliary_ids, adev->id);
-err_free_cadev:
- kfree(cadev);
-
- return ret;
-}
-
-static int k1_ccu_probe(struct platform_device *pdev)
-{
- struct regmap *base_regmap, *lock_regmap = NULL;
- const struct spacemit_ccu_data *data;
- struct device *dev = &pdev->dev;
- int ret;
-
- base_regmap = device_node_to_regmap(dev->of_node);
- if (IS_ERR(base_regmap))
- return dev_err_probe(dev, PTR_ERR(base_regmap),
- "failed to get regmap\n");
-
- /*
- * The lock status of PLLs locate in MPMU region, while PLLs themselves
- * are in APBS region. Reference to MPMU syscon is required to check PLL
- * status.
- */
- if (of_device_is_compatible(dev->of_node, "spacemit,k1-pll")) {
- struct device_node *mpmu = of_parse_phandle(dev->of_node,
- "spacemit,mpmu", 0);
- if (!mpmu)
- return dev_err_probe(dev, -ENODEV,
- "Cannot parse MPMU region\n");
-
- lock_regmap = device_node_to_regmap(mpmu);
- of_node_put(mpmu);
-
- if (IS_ERR(lock_regmap))
- return dev_err_probe(dev, PTR_ERR(lock_regmap),
- "failed to get lock regmap\n");
- }
-
- data = of_device_get_match_data(dev);
-
- ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, data);
- if (ret)
- return dev_err_probe(dev, ret, "failed to register clocks\n");
-
- ret = spacemit_ccu_reset_register(dev, base_regmap, data->reset_name);
- if (ret)
- return dev_err_probe(dev, ret, "failed to register resets\n");
-
- return 0;
-}
-
static const struct of_device_id of_k1_ccu_match[] = {
{
.compatible = "spacemit,k1-pll",
@@ -1195,6 +1021,11 @@ static const struct of_device_id of_k1_ccu_match[] = {
};
MODULE_DEVICE_TABLE(of, of_k1_ccu_match);
+static int k1_ccu_probe(struct platform_device *pdev)
+{
+ return spacemit_ccu_probe(pdev, "spacemit,k1-pll");
+}
+
static struct platform_driver k1_ccu_driver = {
.driver = {
.name = "spacemit,k1-ccu",
diff --git a/drivers/clk/spacemit/ccu_common.c b/drivers/clk/spacemit/ccu_common.c
index 4412c4104dab..5f05b17f8452 100644
--- a/drivers/clk/spacemit/ccu_common.c
+++ b/drivers/clk/spacemit/ccu_common.c
@@ -1,6 +1,177 @@
// SPDX-License-Identifier: GPL-2.0-only
+#include <linux/clk-provider.h>
+#include <linux/device/devres.h>
+#include <linux/mfd/syscon.h>
#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/slab.h>
+#include <soc/spacemit/ccu.h>
+
+#include "ccu_common.h"
+
+static DEFINE_IDA(auxiliary_ids);
+static int spacemit_ccu_register(struct device *dev,
+ struct regmap *regmap,
+ struct regmap *lock_regmap,
+ const struct spacemit_ccu_data *data)
+{
+ struct clk_hw_onecell_data *clk_data;
+ int i, ret;
+
+ /* Nothing to do if the CCU does not implement any clocks */
+ if (!data->hws)
+ return 0;
+
+ clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->num),
+ GFP_KERNEL);
+ if (!clk_data)
+ return -ENOMEM;
+
+ clk_data->num = data->num;
+
+ for (i = 0; i < data->num; i++) {
+ struct clk_hw *hw = data->hws[i];
+ struct ccu_common *common;
+ const char *name;
+
+ if (!hw) {
+ clk_data->hws[i] = ERR_PTR(-ENOENT);
+ continue;
+ }
+
+ name = hw->init->name;
+
+ common = hw_to_ccu_common(hw);
+ common->regmap = regmap;
+ common->lock_regmap = lock_regmap;
+
+ ret = devm_clk_hw_register(dev, hw);
+ if (ret) {
+ dev_err(dev, "Cannot register clock %d - %s\n",
+ i, name);
+ return ret;
+ }
+
+ clk_data->hws[i] = hw;
+ }
+
+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
+ if (ret)
+ dev_err(dev, "failed to add clock hardware provider (%d)\n", ret);
+
+ return ret;
+}
+
+static void spacemit_cadev_release(struct device *dev)
+{
+ struct auxiliary_device *adev = to_auxiliary_dev(dev);
+
+ ida_free(&auxiliary_ids, adev->id);
+ kfree(to_spacemit_ccu_adev(adev));
+}
+
+static void spacemit_adev_unregister(void *data)
+{
+ struct auxiliary_device *adev = data;
+
+ auxiliary_device_delete(adev);
+ auxiliary_device_uninit(adev);
+}
+
+static int spacemit_ccu_reset_register(struct device *dev,
+ struct regmap *regmap,
+ const char *reset_name)
+{
+ struct spacemit_ccu_adev *cadev;
+ struct auxiliary_device *adev;
+ int ret;
+
+ /* Nothing to do if the CCU does not implement a reset controller */
+ if (!reset_name)
+ return 0;
+
+ cadev = kzalloc(sizeof(*cadev), GFP_KERNEL);
+ if (!cadev)
+ return -ENOMEM;
+
+ cadev->regmap = regmap;
+
+ adev = &cadev->adev;
+ adev->name = reset_name;
+ adev->dev.parent = dev;
+ adev->dev.release = spacemit_cadev_release;
+ adev->dev.of_node = dev->of_node;
+ ret = ida_alloc(&auxiliary_ids, GFP_KERNEL);
+ if (ret < 0)
+ goto err_free_cadev;
+ adev->id = ret;
+
+ ret = auxiliary_device_init(adev);
+ if (ret)
+ goto err_free_aux_id;
+
+ ret = auxiliary_device_add(adev);
+ if (ret) {
+ auxiliary_device_uninit(adev);
+ return ret;
+ }
+
+ return devm_add_action_or_reset(dev, spacemit_adev_unregister, adev);
+
+err_free_aux_id:
+ ida_free(&auxiliary_ids, adev->id);
+err_free_cadev:
+ kfree(cadev);
+
+ return ret;
+}
+
+int spacemit_ccu_probe(struct platform_device *pdev, const char *compat)
+{
+ struct regmap *base_regmap, *lock_regmap = NULL;
+ const struct spacemit_ccu_data *data;
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ base_regmap = device_node_to_regmap(dev->of_node);
+ if (IS_ERR(base_regmap))
+ return dev_err_probe(dev, PTR_ERR(base_regmap),
+ "failed to get regmap\n");
+
+ /*
+ * The lock status of PLLs locate in MPMU region, while PLLs themselves
+ * are in APBS region. Reference to MPMU syscon is required to check PLL
+ * status.
+ */
+ if (compat && of_device_is_compatible(dev->of_node, compat)) {
+ struct device_node *mpmu = of_parse_phandle(dev->of_node,
+ "spacemit,mpmu", 0);
+ if (!mpmu)
+ return dev_err_probe(dev, -ENODEV,
+ "Cannot parse MPMU region\n");
+
+ lock_regmap = device_node_to_regmap(mpmu);
+ of_node_put(mpmu);
+
+ if (IS_ERR(lock_regmap))
+ return dev_err_probe(dev, PTR_ERR(lock_regmap),
+ "failed to get lock regmap\n");
+ }
+
+ data = of_device_get_match_data(dev);
+
+ ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, data);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to register clocks\n");
+
+ ret = spacemit_ccu_reset_register(dev, base_regmap, data->reset_name);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to register resets\n");
+
+ return 0;
+}
+EXPORT_SYMBOL_NS_GPL(spacemit_ccu_probe, "CLK_SPACEMIT");
MODULE_DESCRIPTION("SpacemiT CCU common clock driver");
MODULE_LICENSE("GPL");
diff --git a/drivers/clk/spacemit/ccu_common.h b/drivers/clk/spacemit/ccu_common.h
index da72f3836e0b..7ae244b5eace 100644
--- a/drivers/clk/spacemit/ccu_common.h
+++ b/drivers/clk/spacemit/ccu_common.h
@@ -7,6 +7,8 @@
#ifndef _CCU_COMMON_H_
#define _CCU_COMMON_H_
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
#include <linux/regmap.h>
struct ccu_common {
@@ -36,6 +38,12 @@ static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw)
return container_of(hw, struct ccu_common, hw);
}
+struct spacemit_ccu_data {
+ const char *reset_name;
+ struct clk_hw **hws;
+ size_t num;
+};
+
#define ccu_read(c, reg) \
({ \
u32 tmp; \
@@ -45,4 +53,6 @@ static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw)
#define ccu_update(c, reg, mask, val) \
regmap_update_bits((c)->regmap, (c)->reg_##reg, mask, val)
+int spacemit_ccu_probe(struct platform_device *pdev, const char *compat);
+
#endif /* _CCU_COMMON_H_ */
--
2.53.0

149
SPECS/linux/0048-UPSTREAM-riscv-dts-spacemit-reorder-phy-nodes-for-K1.patch Normal file
View File

@@ -0,0 +1,149 @@
From f0119bd5ff94570e25ad80e7313c8c24c0b04c5e Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Wed, 18 Mar 2026 18:00:00 +0800
Subject: [PATCH 048/189] UPSTREAM: riscv: dts: spacemit: reorder phy nodes for
K1
Reorder the PHY nodes of USB and PCIe to the correct positions based on
the register address. This improves the readability and maintainability
of the DT. No functional change is introduced by this reordering.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260318100000.3934516-1-amadeus@jmu.edu.cn
Signed-off-by: Yixun Lan <dlan@kernel.org>
(cherry picked from commit eac600d5cc42b04e799fb65169b8f4060773381b)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/spacemit/k1.dtsi | 108 +++++++++++++--------------
1 file changed, 54 insertions(+), 54 deletions(-)
diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index d2015201f8e5..f0bad6855c97 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -359,6 +359,60 @@ syscon_rcpu2: system-controller@c0888000 {
#reset-cells = <1>;
};
+ usbphy2: phy@c0a30000 {
+ compatible = "spacemit,k1-usb2-phy";
+ reg = <0x0 0xc0a30000 0x0 0x200>;
+ clocks = <&syscon_apmu CLK_USB30>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ combo_phy: phy@c0b10000 {
+ compatible = "spacemit,k1-combo-phy";
+ reg = <0x0 0xc0b10000 0x0 0x1000>;
+ clocks = <&vctcxo_24m>,
+ <&syscon_apmu CLK_PCIE0_DBI>,
+ <&syscon_apmu CLK_PCIE0_MASTER>,
+ <&syscon_apmu CLK_PCIE0_SLAVE>;
+ clock-names = "refclk",
+ "dbi",
+ "mstr",
+ "slv";
+ resets = <&syscon_apmu RESET_PCIE0_GLOBAL>,
+ <&syscon_apmu RESET_PCIE0_DBI>,
+ <&syscon_apmu RESET_PCIE0_MASTER>,
+ <&syscon_apmu RESET_PCIE0_SLAVE>;
+ reset-names = "phy",
+ "dbi",
+ "mstr",
+ "slv";
+ #phy-cells = <1>;
+ spacemit,apmu = <&syscon_apmu>;
+ status = "disabled";
+ };
+
+ pcie1_phy: phy@c0c10000 {
+ compatible = "spacemit,k1-pcie-phy";
+ reg = <0x0 0xc0c10000 0x0 0x1000>;
+ clocks = <&vctcxo_24m>;
+ clock-names = "refclk";
+ resets = <&syscon_apmu RESET_PCIE1_GLOBAL>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ pcie2_phy: phy@c0d10000 {
+ compatible = "spacemit,k1-pcie-phy";
+ reg = <0x0 0xc0d10000 0x0 0x1000>;
+ clocks = <&vctcxo_24m>;
+ clock-names = "refclk";
+ resets = <&syscon_apmu RESET_PCIE2_GLOBAL>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
i2c0: i2c@d4010800 {
compatible = "spacemit,k1-i2c";
reg = <0x0 0xd4010800 0x0 0x38>;
@@ -429,60 +483,6 @@ i2c5: i2c@d4013800 {
status = "disabled";
};
- usbphy2: phy@c0a30000 {
- compatible = "spacemit,k1-usb2-phy";
- reg = <0x0 0xc0a30000 0x0 0x200>;
- clocks = <&syscon_apmu CLK_USB30>;
- #phy-cells = <0>;
- status = "disabled";
- };
-
- combo_phy: phy@c0b10000 {
- compatible = "spacemit,k1-combo-phy";
- reg = <0x0 0xc0b10000 0x0 0x1000>;
- clocks = <&vctcxo_24m>,
- <&syscon_apmu CLK_PCIE0_DBI>,
- <&syscon_apmu CLK_PCIE0_MASTER>,
- <&syscon_apmu CLK_PCIE0_SLAVE>;
- clock-names = "refclk",
- "dbi",
- "mstr",
- "slv";
- resets = <&syscon_apmu RESET_PCIE0_GLOBAL>,
- <&syscon_apmu RESET_PCIE0_DBI>,
- <&syscon_apmu RESET_PCIE0_MASTER>,
- <&syscon_apmu RESET_PCIE0_SLAVE>;
- reset-names = "phy",
- "dbi",
- "mstr",
- "slv";
- #phy-cells = <1>;
- spacemit,apmu = <&syscon_apmu>;
- status = "disabled";
- };
-
- pcie1_phy: phy@c0c10000 {
- compatible = "spacemit,k1-pcie-phy";
- reg = <0x0 0xc0c10000 0x0 0x1000>;
- clocks = <&vctcxo_24m>;
- clock-names = "refclk";
- resets = <&syscon_apmu RESET_PCIE1_GLOBAL>;
- reset-names = "phy";
- #phy-cells = <0>;
- status = "disabled";
- };
-
- pcie2_phy: phy@c0d10000 {
- compatible = "spacemit,k1-pcie-phy";
- reg = <0x0 0xc0d10000 0x0 0x1000>;
- clocks = <&vctcxo_24m>;
- clock-names = "refclk";
- resets = <&syscon_apmu RESET_PCIE2_GLOBAL>;
- reset-names = "phy";
- #phy-cells = <0>;
- status = "disabled";
- };
-
syscon_apbc: system-controller@d4015000 {
compatible = "spacemit,k1-syscon-apbc";
reg = <0x0 0xd4015000 0x0 0x1000>;
--
2.53.0

79
SPECS/linux/0049-UPSTREAM-clk-spacemit-add-platform-SoC-prefix-to-res.patch
View File

@@ -1,79 +0,0 @@
From cadac076c4be33d754da138ac5b2015460e325fc Mon Sep 17 00:00:00 2001
From: Yixun Lan <dlan@gentoo.org>
Date: Sat, 3 Jan 2026 14:14:36 +0800
Subject: [PATCH 049/197] UPSTREAM: clk: spacemit: add platform SoC prefix to
reset name
This change is needed for adding future new SpacemiT K3 reset driver.
Since both K1 and K3 reset code register via the same module which its
name changed to spacemit_ccu, it's necessary to encode the platform/SoC
in the reset auxiliary device name to distinguish them, otherwise two
reset drivers will claim to support same "compatible" auxiliary device
even in the case of only one CCU clock driver got registered, which in
the end lead to a broken reset driver.
This change will introduce a runtime break to reset driver, and will be
fixed in follow-up commit:
ecff77f7c041 ("reset: spacemit: fix auxiliary device id")
Link: https://lore.kernel.org/r/20260108-06-k1-clk-common-v4-3-badf635993d3@gentoo.org
Reviewed-by: Alex Elder <elder@riscstar.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
(cherry picked from commit 0664a46f93e2fb2f75fa05b5f08949600cce88f9)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/clk/spacemit/ccu-k1.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c
index 02c792a73759..dee14d25f75d 100644
--- a/drivers/clk/spacemit/ccu-k1.c
+++ b/drivers/clk/spacemit/ccu-k1.c
@@ -789,7 +789,7 @@ static struct clk_hw *k1_ccu_mpmu_hws[] = {
};
static const struct spacemit_ccu_data k1_ccu_mpmu_data = {
- .reset_name = "mpmu-reset",
+ .reset_name = "k1-mpmu-reset",
.hws = k1_ccu_mpmu_hws,
.num = ARRAY_SIZE(k1_ccu_mpmu_hws),
};
@@ -900,7 +900,7 @@ static struct clk_hw *k1_ccu_apbc_hws[] = {
};
static const struct spacemit_ccu_data k1_ccu_apbc_data = {
- .reset_name = "apbc-reset",
+ .reset_name = "k1-apbc-reset",
.hws = k1_ccu_apbc_hws,
.num = ARRAY_SIZE(k1_ccu_apbc_hws),
};
@@ -971,21 +971,21 @@ static struct clk_hw *k1_ccu_apmu_hws[] = {
};
static const struct spacemit_ccu_data k1_ccu_apmu_data = {
- .reset_name = "apmu-reset",
+ .reset_name = "k1-apmu-reset",
.hws = k1_ccu_apmu_hws,
.num = ARRAY_SIZE(k1_ccu_apmu_hws),
};
static const struct spacemit_ccu_data k1_ccu_rcpu_data = {
- .reset_name = "rcpu-reset",
+ .reset_name = "k1-rcpu-reset",
};
static const struct spacemit_ccu_data k1_ccu_rcpu2_data = {
- .reset_name = "rcpu2-reset",
+ .reset_name = "k1-rcpu2-reset",
};
static const struct spacemit_ccu_data k1_ccu_apbc2_data = {
- .reset_name = "apbc2-reset",
+ .reset_name = "k1-apbc2-reset",
};
static const struct of_device_id of_k1_ccu_match[] = {
--
2.53.0

42
SPECS/linux/0049-UPSTREAM-riscv-dts-spacemit-drop-incorrect-pinctrl-f.patch Normal file
View File

@@ -0,0 +1,42 @@
From d3ef681bb4c9bc189a469dccc1cb6ab6d2d01443 Mon Sep 17 00:00:00 2001
From: Aurelien Jarno <aurelien@aurel32.net>
Date: Sun, 22 Mar 2026 21:25:01 +0100
Subject: [PATCH 049/189] UPSTREAM: riscv: dts: spacemit: drop incorrect
pinctrl for combo PHY
The combo PHY on the Banana Pi F3 is used for the USB 3.0 port. The high
speed differential lanes are always configured as such, and do not
require a pinctrl entry.
The existing pinctrl entry only configures PCIe secondary pins, which
are unused for USB and instead routed to the MIPI CSI1 connector.
Remove this incorrect pinctrl entry.
Fixes: 0be016a4b5d1b9 ("riscv: dts: spacemit: PCIe and PHY-related updates")
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260322202502.2205755-1-aurelien@aurel32.net
Signed-off-by: Yixun Lan <dlan@kernel.org>
(cherry picked from commit c68360c0d636dae71f766b7b296ddfcf2827ccc7)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index 404b69c47b91..5790d927b93d 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -81,8 +81,6 @@ usb3_hub_5v: regulator-usb3-hub-5v {
};
&combo_phy {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie0_3_cfg>;
status = "okay";
};
--
2.53.0

43
SPECS/linux/0050-UPSTREAM-reset-spacemit-fix-auxiliary-device-id.patch
View File

@@ -1,43 +0,0 @@
From 903a7d98f5bd85d316a29ac2e53fc2fc4f7a7694 Mon Sep 17 00:00:00 2001
From: Yixun Lan <dlan@gentoo.org>
Date: Fri, 19 Dec 2025 05:34:39 +0800
Subject: [PATCH 050/197] UPSTREAM: reset: spacemit: fix auxiliary device id
Due to the auxiliary register procedure moved to ccu common module where
the module name changed to spacemit_ccu, then the reset auxiliary device
register id also need to be adjusted in order to prepare for adding new
K3 reset driver, otherwise two reset drivers will claim to support same
"compatible" auxiliary device.
In order to prevent the reset driver breakage, this commit is necessary
as a post-fix for changes introduced by two patches below, and should be
merged with them to make the patch series runtime bisectable.
("clk: spacemit: add platform SoC prefix to reset name")
("clk: spacemit: extract common ccu functions")
Link: https://lore.kernel.org/r/20260108-06-k1-clk-common-v4-4-badf635993d3@gentoo.org
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Alex Elder <elder@riscstar.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
(cherry picked from commit ecff77f7c04141cc18ee2482936c96117060c0f2)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
drivers/reset/reset-spacemit.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/reset/reset-spacemit.c b/drivers/reset/reset-spacemit.c
index e1272aff28f7..cc7fd1f8750d 100644
--- a/drivers/reset/reset-spacemit.c
+++ b/drivers/reset/reset-spacemit.c
@@ -278,7 +278,7 @@ static int spacemit_reset_probe(struct auxiliary_device *adev,
#define K1_AUX_DEV_ID(_unit) \
{ \
- .name = "spacemit_ccu_k1." #_unit "-reset", \
+ .name = "spacemit_ccu.k1-" #_unit "-reset", \
.driver_data = (kernel_ulong_t)&k1_ ## _unit ## _reset_data, \
}
--
2.53.0

146
SPECS/linux/0138-FROMLIST-riscv-dts-spacemit-k3-Add-ethernet-device-n.patch → SPECS/linux/0050-UPSTREAM-riscv-dts-spacemit-Add-ethernet-device-for-.patch
View File

@@ -1,41 +1,50 @@
From 1e0ad332eafd4e3a1a0e29720015b94d551e0995 Mon Sep 17 00:00:00 2001
From dae38869a8aef12bbdde3ffba297c9828bfe0978 Mon Sep 17 00:00:00 2001
From: Inochi Amaoto <inochiama@gmail.com>
Date: Wed, 4 Mar 2026 16:25:41 +0800
Subject: [PATCH 138/197] FROMLIST: riscv: dts: spacemit: k3: Add ethernet
device node
Date: Thu, 26 Mar 2026 09:46:17 +0800
Subject: [PATCH 050/189] UPSTREAM: riscv: dts: spacemit: Add ethernet device
for K3
Add all ethernet device nodes for K3 SoC. And enable the available
ethernet device for the PICO ITX board.
Add all ethernet device nodes for K3 SoC.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20260304082541.1786223-1-inochiama@gmail.com
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://lore.kernel.org/r/20260326014617.1011732-1-inochiama@gmail.com
Signed-off-by: Yixun Lan <dlan@kernel.org>
(cherry picked from commit 74657a376960252e248089e518cfaaf813906989)
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
---
arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 20 ++++
arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 38 +++++++
arch/riscv/boot/dts/spacemit/k3.dtsi | 106 +++++++++++++++++++
3 files changed, 164 insertions(+)
arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 34 ++++++
arch/riscv/boot/dts/spacemit/k3.dtsi | 117 +++++++++++++++++++
3 files changed, 171 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
index b098dbd0e7a1..47e4fa824417 100644
index b098dbd0e7a1..504fe6bd46b2 100644
--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
@@ -6,6 +6,7 @@
@@ -3,6 +3,7 @@
* Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd
* Copyright (c) 2026 Guodong Xu <guodong@riscstar.com>
*/
+#include <dt-bindings/gpio/gpio.h>
#include "k3.dtsi"
#include "k3-pinctrl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
@@ -12,6 +13,7 @@ / {
compatible = "spacemit,k3-pico-itx", "spacemit,k3";
/ {
model = "SpacemiT K3 Pico-ITX";
@@ -25,6 +26,25 @@ memory@100000000 {
aliases {
+ ethernet0 = &eth0;
serial0 = &uart0;
};
@@ -25,6 +27,24 @@ memory@100000000 {
};
};
+&eth0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_cfg>;
+
+ pinctrl-0 = <&gmac0_rgmii_0_cfg>, <&gmac0_phy_0_cfg>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy0>;
+ status = "okay";
@@ -55,67 +64,58 @@ index b098dbd0e7a1..47e4fa824417 100644
pinctrl-names = "default";
pinctrl-0 = <&uart0_0_cfg>;
diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
index efb0f1572188..256880192846 100644
index efb0f1572188..a7b5d10c332e 100644
--- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi
@@ -21,4 +21,42 @@ uart0-0-pins {
drive-strength = <25>;
};
};
+
+ gmac0_cfg: gmac0-cfg {
+ gmac0_base_pins: gmac0-0-pins {
+ pinmux = <K3_PADCONF(0, 1)>,
+ <K3_PADCONF(1, 1)>,
+ <K3_PADCONF(2, 1)>,
+ <K3_PADCONF(3, 1)>,
+ <K3_PADCONF(6, 1)>,
+ <K3_PADCONF(7, 1)>,
+ <K3_PADCONF(11, 1)>,
+ <K3_PADCONF(12, 1)>,
+ <K3_PADCONF(13, 1)>;
@@ -11,6 +11,40 @@
#define K3_GPIO(x) (x / 32) (x % 32)
&pinctrl {
+ gmac0_rgmii_0_cfg: gmac0-rgmii-0-cfg {
+ gmac0-rgmii-0-pins {
+ pinmux = <K3_PADCONF(0, 1)>, /* gmac0_rxdv */
+ <K3_PADCONF(1, 1)>, /* gmac0_rx_d0 */
+ <K3_PADCONF(2, 1)>, /* gmac0_rx_d1 */
+ <K3_PADCONF(3, 1)>, /* gmac0_rx_clk */
+ <K3_PADCONF(4, 1)>, /* gmac0_rx_d2 */
+ <K3_PADCONF(5, 1)>, /* gmac0_rx_d3 */
+ <K3_PADCONF(6, 1)>, /* gmac0_tx_d0 */
+ <K3_PADCONF(7, 1)>, /* gmac0_tx_d1 */
+ <K3_PADCONF(8, 1)>, /* gmac0_tx_clk */
+ <K3_PADCONF(9, 1)>, /* gmac0_tx_d2 */
+ <K3_PADCONF(10, 1)>, /* gmac0_tx_d3 */
+ <K3_PADCONF(11, 1)>, /* gmac0_tx_en */
+ <K3_PADCONF(12, 1)>, /* gmac0_mdc */
+ <K3_PADCONF(13, 1)>; /* gmac0_mdio */
+
+ bias-disable;
+ drive-strength = <25>;
+ power-source = <1800>;
+ };
+
+ gmac0_rgmii_add_pins: gmac0-1-pins {
+ pinmux = <K3_PADCONF(4, 1)>,
+ <K3_PADCONF(5, 1)>,
+ <K3_PADCONF(8, 1)>,
+ <K3_PADCONF(9, 1)>,
+ <K3_PADCONF(10, 1)>;
+ };
+
+ bias-disable;
+ drive-strength = <25>;
+ power-source = <1800>;
+ };
+
+ gmac0_int_pins: gmac0-3-pins {
+ pinmux = <K3_PADCONF(14, 1)>;
+ gmac0_phy_0_cfg: gmac0-phy-0-cfg {
+ gmac0-phy-0-pins {
+ pinmux = <K3_PADCONF(14, 1)>; /* gmac0_int */
+
+ bias-disable;
+ drive-strength = <25>;
+ power-source = <1800>;
+ };
+ };
};
+
/omit-if-no-ref/
uart0_0_cfg: uart0-0-cfg {
uart0-0-pins {
diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
index a3a8ceddabec..237fb00e4bc4 100644
index a3a8ceddabec..5f4818cd5d6d 100644
--- a/arch/riscv/boot/dts/spacemit/k3.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
@@ -438,6 +438,112 @@ soc: soc {
@@ -438,6 +438,123 @@ soc: soc {
dma-noncoherent;
ranges;
+ gmac_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <0xf>;
+ snps,rd_osr_lmt = <0xf>;
+ /* max axi burst len is 256 */
+ snps,blen = <256 128 64 32 16 0 0>;
+ };
+
+ eth0: ethernet@cac80000 {
+ compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a";
+ reg = <0x0 0xcac80000 0x0 0x2000>;
@@ -123,7 +123,6 @@ index a3a8ceddabec..237fb00e4bc4 100644
+ <&syscon_apmu CLK_APMU_EMAC0_1588>,
+ <&syscon_apmu CLK_APMU_EMAC0_RGMII_TX>;
+ clock-names = "stmmaceth", "ptp_ref", "tx";
+ interrupt-parent = <&saplic>;
+ interrupts = <131 IRQ_TYPE_LEVEL_HIGH>,
+ <276 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
@@ -138,7 +137,7 @@ index a3a8ceddabec..237fb00e4bc4 100644
+ snps,txpbl = <8>;
+ snps,rxpbl = <8>;
+ snps,force_sf_dma_mode;
+ snps,axi-config = <&gmac_axi_setup>;
+ snps,axi-config = <&gmac0_axi_setup>;
+ spacemit,apmu = <&syscon_apmu 0x3e4 0x3e8>;
+ status = "disabled";
+
@@ -147,6 +146,13 @@ index a3a8ceddabec..237fb00e4bc4 100644
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ gmac0_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <0xf>;
+ snps,rd_osr_lmt = <0xf>;
+ /* max axi burst len is 256 */
+ snps,blen = <256 128 64 32 16 0 0>;
+ };
+ };
+
+ eth1: ethernet@cac82000 {
@@ -156,7 +162,6 @@ index a3a8ceddabec..237fb00e4bc4 100644
+ <&syscon_apmu CLK_APMU_EMAC1_1588>,
+ <&syscon_apmu CLK_APMU_EMAC1_RGMII_TX>;
+ clock-names = "stmmaceth", "ptp_ref", "tx";
+ interrupt-parent = <&saplic>;
+ interrupts = <133 IRQ_TYPE_LEVEL_HIGH>,
+ <277 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
@@ -171,7 +176,7 @@ index a3a8ceddabec..237fb00e4bc4 100644
+ snps,txpbl = <8>;
+ snps,rxpbl = <8>;
+ snps,force_sf_dma_mode;
+ snps,axi-config = <&gmac_axi_setup>;
+ snps,axi-config = <&gmac1_axi_setup>;
+ spacemit,apmu = <&syscon_apmu 0x3ec 0x3f0>;
+ status = "disabled";
+
@@ -180,6 +185,13 @@ index a3a8ceddabec..237fb00e4bc4 100644
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ gmac1_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <0xf>;
+ snps,rd_osr_lmt = <0xf>;
+ /* max axi burst len is 256 */
+ snps,blen = <256 128 64 32 16 0 0>;
+ };
+ };
+
+ eth2: ethernet@cac8e000 {
@@ -189,7 +201,6 @@ index a3a8ceddabec..237fb00e4bc4 100644
+ <&syscon_apmu CLK_APMU_EMAC2_1588>,
+ <&syscon_apmu CLK_APMU_EMAC2_RGMII_TX>;
+ clock-names = "stmmaceth", "ptp_ref", "tx";
+ interrupt-parent = <&saplic>;
+ interrupts = <130 IRQ_TYPE_LEVEL_HIGH>,
+ <278 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
@@ -204,7 +215,7 @@ index a3a8ceddabec..237fb00e4bc4 100644
+ snps,txpbl = <8>;
+ snps,rxpbl = <8>;
+ snps,force_sf_dma_mode;
+ snps,axi-config = <&gmac_axi_setup>;
+ snps,axi-config = <&gmac2_axi_setup>;
+ spacemit,apmu = <&syscon_apmu 0x248 0x24c>;
+ status = "disabled";
+
@@ -213,6 +224,13 @@ index a3a8ceddabec..237fb00e4bc4 100644
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ gmac2_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <0xf>;
+ snps,rd_osr_lmt = <0xf>;
+ /* max axi burst len is 256 */
+ snps,blen = <256 128 64 32 16 0 0>;
+ };
+ };
+
syscon_apbc: system-controller@d4015000 {

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