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kvmtool: Update architecture specific kvm.h files
Similarily to the generic uapi/linux/kvm.h, each architecture carries a kvm.h header in its arch/*/include/uapi/asm directory. These contain bits for the architecture specific interface. Since we use many recent features in kvmtool, the system headers provided by the distribution are usually not up-to-date. Copy the Linux v4.1-rc6 versions of those files for all supported architectures into the kvmtool tree to get access to the full glory. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Andre Przywara
committed by
Will Deacon
Will Deacon
parent
a08bb43a0c
commit
6002122071
@@ -0,0 +1,224 @@
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/*
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef __ARM_KVM_H__
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#define __ARM_KVM_H__
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#include <linux/types.h>
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#include <linux/psci.h>
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#include <asm/ptrace.h>
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#define __KVM_HAVE_GUEST_DEBUG
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#define __KVM_HAVE_IRQ_LINE
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#define __KVM_HAVE_READONLY_MEM
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#define KVM_REG_SIZE(id) \
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(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
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/* Valid for svc_regs, abt_regs, und_regs, irq_regs in struct kvm_regs */
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#define KVM_ARM_SVC_sp svc_regs[0]
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#define KVM_ARM_SVC_lr svc_regs[1]
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#define KVM_ARM_SVC_spsr svc_regs[2]
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#define KVM_ARM_ABT_sp abt_regs[0]
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#define KVM_ARM_ABT_lr abt_regs[1]
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#define KVM_ARM_ABT_spsr abt_regs[2]
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#define KVM_ARM_UND_sp und_regs[0]
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#define KVM_ARM_UND_lr und_regs[1]
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#define KVM_ARM_UND_spsr und_regs[2]
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#define KVM_ARM_IRQ_sp irq_regs[0]
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#define KVM_ARM_IRQ_lr irq_regs[1]
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#define KVM_ARM_IRQ_spsr irq_regs[2]
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/* Valid only for fiq_regs in struct kvm_regs */
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#define KVM_ARM_FIQ_r8 fiq_regs[0]
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#define KVM_ARM_FIQ_r9 fiq_regs[1]
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#define KVM_ARM_FIQ_r10 fiq_regs[2]
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#define KVM_ARM_FIQ_fp fiq_regs[3]
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#define KVM_ARM_FIQ_ip fiq_regs[4]
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#define KVM_ARM_FIQ_sp fiq_regs[5]
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#define KVM_ARM_FIQ_lr fiq_regs[6]
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#define KVM_ARM_FIQ_spsr fiq_regs[7]
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struct kvm_regs {
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struct pt_regs usr_regs; /* R0_usr - R14_usr, PC, CPSR */
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unsigned long svc_regs[3]; /* SP_svc, LR_svc, SPSR_svc */
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unsigned long abt_regs[3]; /* SP_abt, LR_abt, SPSR_abt */
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unsigned long und_regs[3]; /* SP_und, LR_und, SPSR_und */
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unsigned long irq_regs[3]; /* SP_irq, LR_irq, SPSR_irq */
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unsigned long fiq_regs[8]; /* R8_fiq - R14_fiq, SPSR_fiq */
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};
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/* Supported Processor Types */
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#define KVM_ARM_TARGET_CORTEX_A15 0
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#define KVM_ARM_TARGET_CORTEX_A7 1
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#define KVM_ARM_NUM_TARGETS 2
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/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
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#define KVM_ARM_DEVICE_TYPE_SHIFT 0
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#define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
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#define KVM_ARM_DEVICE_ID_SHIFT 16
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#define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
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/* Supported device IDs */
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#define KVM_ARM_DEVICE_VGIC_V2 0
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/* Supported VGIC address types */
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#define KVM_VGIC_V2_ADDR_TYPE_DIST 0
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#define KVM_VGIC_V2_ADDR_TYPE_CPU 1
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#define KVM_VGIC_V2_DIST_SIZE 0x1000
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#define KVM_VGIC_V2_CPU_SIZE 0x2000
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#define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */
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#define KVM_ARM_VCPU_PSCI_0_2 1 /* CPU uses PSCI v0.2 */
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struct kvm_vcpu_init {
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__u32 target;
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__u32 features[7];
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};
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struct kvm_sregs {
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};
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struct kvm_fpu {
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};
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struct kvm_guest_debug_arch {
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};
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struct kvm_debug_exit_arch {
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};
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struct kvm_sync_regs {
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};
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struct kvm_arch_memory_slot {
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};
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/* If you need to interpret the index values, here is the key: */
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#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
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#define KVM_REG_ARM_COPROC_SHIFT 16
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#define KVM_REG_ARM_32_OPC2_MASK 0x0000000000000007
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#define KVM_REG_ARM_32_OPC2_SHIFT 0
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#define KVM_REG_ARM_OPC1_MASK 0x0000000000000078
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#define KVM_REG_ARM_OPC1_SHIFT 3
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#define KVM_REG_ARM_CRM_MASK 0x0000000000000780
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#define KVM_REG_ARM_CRM_SHIFT 7
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#define KVM_REG_ARM_32_CRN_MASK 0x0000000000007800
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#define KVM_REG_ARM_32_CRN_SHIFT 11
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#define ARM_CP15_REG_SHIFT_MASK(x,n) \
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(((x) << KVM_REG_ARM_ ## n ## _SHIFT) & KVM_REG_ARM_ ## n ## _MASK)
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#define __ARM_CP15_REG(op1,crn,crm,op2) \
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(KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT) | \
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ARM_CP15_REG_SHIFT_MASK(op1, OPC1) | \
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ARM_CP15_REG_SHIFT_MASK(crn, 32_CRN) | \
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ARM_CP15_REG_SHIFT_MASK(crm, CRM) | \
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ARM_CP15_REG_SHIFT_MASK(op2, 32_OPC2))
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#define ARM_CP15_REG32(...) (__ARM_CP15_REG(__VA_ARGS__) | KVM_REG_SIZE_U32)
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#define __ARM_CP15_REG64(op1,crm) \
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(__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)
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#define ARM_CP15_REG64(...) __ARM_CP15_REG64(__VA_ARGS__)
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#define KVM_REG_ARM_TIMER_CTL ARM_CP15_REG32(0, 14, 3, 1)
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#define KVM_REG_ARM_TIMER_CNT ARM_CP15_REG64(1, 14)
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#define KVM_REG_ARM_TIMER_CVAL ARM_CP15_REG64(3, 14)
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/* Normal registers are mapped as coprocessor 16. */
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#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
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#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / 4)
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/* Some registers need more space to represent values. */
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#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
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#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00
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#define KVM_REG_ARM_DEMUX_ID_SHIFT 8
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#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
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#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF
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#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
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/* VFP registers: we could overload CP10 like ARM does, but that's ugly. */
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#define KVM_REG_ARM_VFP (0x0012 << KVM_REG_ARM_COPROC_SHIFT)
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#define KVM_REG_ARM_VFP_MASK 0x000000000000FFFF
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#define KVM_REG_ARM_VFP_BASE_REG 0x0
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#define KVM_REG_ARM_VFP_FPSID 0x1000
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#define KVM_REG_ARM_VFP_FPSCR 0x1001
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#define KVM_REG_ARM_VFP_MVFR1 0x1006
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#define KVM_REG_ARM_VFP_MVFR0 0x1007
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#define KVM_REG_ARM_VFP_FPEXC 0x1008
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#define KVM_REG_ARM_VFP_FPINST 0x1009
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#define KVM_REG_ARM_VFP_FPINST2 0x100A
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/* Device Control API: ARM VGIC */
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#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
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#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
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#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
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#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
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#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
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#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
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#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
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#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
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#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
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#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
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/* KVM_IRQ_LINE irq field index values */
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#define KVM_ARM_IRQ_TYPE_SHIFT 24
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#define KVM_ARM_IRQ_TYPE_MASK 0xff
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#define KVM_ARM_IRQ_VCPU_SHIFT 16
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#define KVM_ARM_IRQ_VCPU_MASK 0xff
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#define KVM_ARM_IRQ_NUM_SHIFT 0
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#define KVM_ARM_IRQ_NUM_MASK 0xffff
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/* irq_type field */
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#define KVM_ARM_IRQ_TYPE_CPU 0
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#define KVM_ARM_IRQ_TYPE_SPI 1
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#define KVM_ARM_IRQ_TYPE_PPI 2
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/* out-of-kernel GIC cpu interrupt injection irq_number field */
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#define KVM_ARM_IRQ_CPU_IRQ 0
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#define KVM_ARM_IRQ_CPU_FIQ 1
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/*
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* This used to hold the highest supported SPI, but it is now obsolete
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* and only here to provide source code level compatibility with older
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* userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS.
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*/
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#ifndef __KERNEL__
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#define KVM_ARM_IRQ_GIC_MAX 127
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#endif
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/* One single KVM irqchip, ie. the VGIC */
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#define KVM_NR_IRQCHIPS 1
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/* PSCI interface */
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#define KVM_PSCI_FN_BASE 0x95c1ba5e
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#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))
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#define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0)
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#define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1)
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#define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2)
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#define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3)
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#define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS
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#define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED
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#define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS
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#define KVM_PSCI_RET_DENIED PSCI_RET_DENIED
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#endif /* __ARM_KVM_H__ */
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@@ -0,0 +1,219 @@
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/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* Derived from arch/arm/include/uapi/asm/kvm.h:
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ARM_KVM_H__
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#define __ARM_KVM_H__
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#define KVM_SPSR_EL1 0
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#define KVM_SPSR_SVC KVM_SPSR_EL1
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#define KVM_SPSR_ABT 1
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#define KVM_SPSR_UND 2
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#define KVM_SPSR_IRQ 3
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#define KVM_SPSR_FIQ 4
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#define KVM_NR_SPSR 5
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#ifndef __ASSEMBLY__
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#include <linux/psci.h>
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#include <asm/types.h>
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#include <asm/ptrace.h>
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#define __KVM_HAVE_GUEST_DEBUG
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#define __KVM_HAVE_IRQ_LINE
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#define __KVM_HAVE_READONLY_MEM
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#define KVM_REG_SIZE(id) \
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(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
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struct kvm_regs {
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struct user_pt_regs regs; /* sp = sp_el0 */
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__u64 sp_el1;
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__u64 elr_el1;
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__u64 spsr[KVM_NR_SPSR];
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struct user_fpsimd_state fp_regs;
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};
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/* Supported Processor Types */
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#define KVM_ARM_TARGET_AEM_V8 0
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#define KVM_ARM_TARGET_FOUNDATION_V8 1
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#define KVM_ARM_TARGET_CORTEX_A57 2
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#define KVM_ARM_TARGET_XGENE_POTENZA 3
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#define KVM_ARM_TARGET_CORTEX_A53 4
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#define KVM_ARM_NUM_TARGETS 5
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/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
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#define KVM_ARM_DEVICE_TYPE_SHIFT 0
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#define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
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#define KVM_ARM_DEVICE_ID_SHIFT 16
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#define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
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/* Supported device IDs */
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#define KVM_ARM_DEVICE_VGIC_V2 0
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/* Supported VGIC address types */
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#define KVM_VGIC_V2_ADDR_TYPE_DIST 0
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#define KVM_VGIC_V2_ADDR_TYPE_CPU 1
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#define KVM_VGIC_V2_DIST_SIZE 0x1000
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#define KVM_VGIC_V2_CPU_SIZE 0x2000
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/* Supported VGICv3 address types */
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#define KVM_VGIC_V3_ADDR_TYPE_DIST 2
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#define KVM_VGIC_V3_ADDR_TYPE_REDIST 3
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#define KVM_VGIC_V3_DIST_SIZE SZ_64K
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#define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)
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#define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */
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#define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */
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#define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */
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struct kvm_vcpu_init {
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__u32 target;
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__u32 features[7];
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};
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struct kvm_sregs {
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};
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struct kvm_fpu {
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};
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struct kvm_guest_debug_arch {
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};
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struct kvm_debug_exit_arch {
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};
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struct kvm_sync_regs {
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};
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struct kvm_arch_memory_slot {
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};
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/* If you need to interpret the index values, here is the key: */
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#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
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#define KVM_REG_ARM_COPROC_SHIFT 16
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/* Normal registers are mapped as coprocessor 16. */
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#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
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#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32))
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/* Some registers need more space to represent values. */
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#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
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#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00
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#define KVM_REG_ARM_DEMUX_ID_SHIFT 8
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#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
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#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF
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#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
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/* AArch64 system registers */
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#define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT)
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#define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000
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#define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14
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#define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800
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#define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11
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#define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780
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#define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7
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#define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078
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#define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3
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#define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007
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#define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0
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#define ARM64_SYS_REG_SHIFT_MASK(x,n) \
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(((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \
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KVM_REG_ARM64_SYSREG_ ## n ## _MASK)
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#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \
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(KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \
|
||||
ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
|
||||
ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
|
||||
ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
|
||||
ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
|
||||
ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
|
||||
|
||||
#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64)
|
||||
|
||||
#define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1)
|
||||
#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)
|
||||
#define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)
|
||||
|
||||
/* Device Control API: ARM VGIC */
|
||||
#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
|
||||
#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
|
||||
#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
|
||||
#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
|
||||
#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
|
||||
#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
|
||||
#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
|
||||
#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
|
||||
#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
|
||||
#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
|
||||
|
||||
/* KVM_IRQ_LINE irq field index values */
|
||||
#define KVM_ARM_IRQ_TYPE_SHIFT 24
|
||||
#define KVM_ARM_IRQ_TYPE_MASK 0xff
|
||||
#define KVM_ARM_IRQ_VCPU_SHIFT 16
|
||||
#define KVM_ARM_IRQ_VCPU_MASK 0xff
|
||||
#define KVM_ARM_IRQ_NUM_SHIFT 0
|
||||
#define KVM_ARM_IRQ_NUM_MASK 0xffff
|
||||
|
||||
/* irq_type field */
|
||||
#define KVM_ARM_IRQ_TYPE_CPU 0
|
||||
#define KVM_ARM_IRQ_TYPE_SPI 1
|
||||
#define KVM_ARM_IRQ_TYPE_PPI 2
|
||||
|
||||
/* out-of-kernel GIC cpu interrupt injection irq_number field */
|
||||
#define KVM_ARM_IRQ_CPU_IRQ 0
|
||||
#define KVM_ARM_IRQ_CPU_FIQ 1
|
||||
|
||||
/*
|
||||
* This used to hold the highest supported SPI, but it is now obsolete
|
||||
* and only here to provide source code level compatibility with older
|
||||
* userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS.
|
||||
*/
|
||||
#ifndef __KERNEL__
|
||||
#define KVM_ARM_IRQ_GIC_MAX 127
|
||||
#endif
|
||||
|
||||
/* One single KVM irqchip, ie. the VGIC */
|
||||
#define KVM_NR_IRQCHIPS 1
|
||||
|
||||
/* PSCI interface */
|
||||
#define KVM_PSCI_FN_BASE 0x95c1ba5e
|
||||
#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))
|
||||
|
||||
#define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0)
|
||||
#define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1)
|
||||
#define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2)
|
||||
#define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3)
|
||||
|
||||
#define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS
|
||||
#define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED
|
||||
#define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS
|
||||
#define KVM_PSCI_RET_DENIED PSCI_RET_DENIED
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __ARM_KVM_H__ */
|
||||
@@ -0,0 +1,208 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
|
||||
* Copyright (C) 2013 Cavium, Inc.
|
||||
* Authors: Sanjay Lal <sanjayl@kymasys.com>
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_KVM_MIPS_H
|
||||
#define __LINUX_KVM_MIPS_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/*
|
||||
* KVM MIPS specific structures and definitions.
|
||||
*
|
||||
* Some parts derived from the x86 version of this file.
|
||||
*/
|
||||
|
||||
/*
|
||||
* for KVM_GET_REGS and KVM_SET_REGS
|
||||
*
|
||||
* If Config[AT] is zero (32-bit CPU), the register contents are
|
||||
* stored in the lower 32-bits of the struct kvm_regs fields and sign
|
||||
* extended to 64-bits.
|
||||
*/
|
||||
struct kvm_regs {
|
||||
/* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
|
||||
__u64 gpr[32];
|
||||
__u64 hi;
|
||||
__u64 lo;
|
||||
__u64 pc;
|
||||
};
|
||||
|
||||
/*
|
||||
* for KVM_GET_FPU and KVM_SET_FPU
|
||||
*/
|
||||
struct kvm_fpu {
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* For MIPS, we use KVM_SET_ONE_REG and KVM_GET_ONE_REG to access various
|
||||
* registers. The id field is broken down as follows:
|
||||
*
|
||||
* bits[63..52] - As per linux/kvm.h
|
||||
* bits[51..32] - Must be zero.
|
||||
* bits[31..16] - Register set.
|
||||
*
|
||||
* Register set = 0: GP registers from kvm_regs (see definitions below).
|
||||
*
|
||||
* Register set = 1: CP0 registers.
|
||||
* bits[15..8] - Must be zero.
|
||||
* bits[7..3] - Register 'rd' index.
|
||||
* bits[2..0] - Register 'sel' index.
|
||||
*
|
||||
* Register set = 2: KVM specific registers (see definitions below).
|
||||
*
|
||||
* Register set = 3: FPU / MSA registers (see definitions below).
|
||||
*
|
||||
* Other sets registers may be added in the future. Each set would
|
||||
* have its own identifier in bits[31..16].
|
||||
*/
|
||||
|
||||
#define KVM_REG_MIPS_GP (KVM_REG_MIPS | 0x0000000000000000ULL)
|
||||
#define KVM_REG_MIPS_CP0 (KVM_REG_MIPS | 0x0000000000010000ULL)
|
||||
#define KVM_REG_MIPS_KVM (KVM_REG_MIPS | 0x0000000000020000ULL)
|
||||
#define KVM_REG_MIPS_FPU (KVM_REG_MIPS | 0x0000000000030000ULL)
|
||||
|
||||
|
||||
/*
|
||||
* KVM_REG_MIPS_GP - General purpose registers from kvm_regs.
|
||||
*/
|
||||
|
||||
#define KVM_REG_MIPS_R0 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 0)
|
||||
#define KVM_REG_MIPS_R1 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 1)
|
||||
#define KVM_REG_MIPS_R2 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 2)
|
||||
#define KVM_REG_MIPS_R3 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 3)
|
||||
#define KVM_REG_MIPS_R4 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 4)
|
||||
#define KVM_REG_MIPS_R5 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 5)
|
||||
#define KVM_REG_MIPS_R6 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 6)
|
||||
#define KVM_REG_MIPS_R7 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 7)
|
||||
#define KVM_REG_MIPS_R8 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 8)
|
||||
#define KVM_REG_MIPS_R9 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 9)
|
||||
#define KVM_REG_MIPS_R10 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 10)
|
||||
#define KVM_REG_MIPS_R11 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 11)
|
||||
#define KVM_REG_MIPS_R12 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 12)
|
||||
#define KVM_REG_MIPS_R13 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 13)
|
||||
#define KVM_REG_MIPS_R14 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 14)
|
||||
#define KVM_REG_MIPS_R15 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 15)
|
||||
#define KVM_REG_MIPS_R16 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 16)
|
||||
#define KVM_REG_MIPS_R17 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 17)
|
||||
#define KVM_REG_MIPS_R18 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 18)
|
||||
#define KVM_REG_MIPS_R19 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 19)
|
||||
#define KVM_REG_MIPS_R20 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 20)
|
||||
#define KVM_REG_MIPS_R21 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 21)
|
||||
#define KVM_REG_MIPS_R22 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 22)
|
||||
#define KVM_REG_MIPS_R23 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 23)
|
||||
#define KVM_REG_MIPS_R24 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 24)
|
||||
#define KVM_REG_MIPS_R25 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 25)
|
||||
#define KVM_REG_MIPS_R26 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 26)
|
||||
#define KVM_REG_MIPS_R27 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 27)
|
||||
#define KVM_REG_MIPS_R28 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 28)
|
||||
#define KVM_REG_MIPS_R29 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 29)
|
||||
#define KVM_REG_MIPS_R30 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 30)
|
||||
#define KVM_REG_MIPS_R31 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 31)
|
||||
|
||||
#define KVM_REG_MIPS_HI (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 32)
|
||||
#define KVM_REG_MIPS_LO (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 33)
|
||||
#define KVM_REG_MIPS_PC (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 34)
|
||||
|
||||
|
||||
/*
|
||||
* KVM_REG_MIPS_KVM - KVM specific control registers.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CP0_Count control
|
||||
* DC: Set 0: Master disable CP0_Count and set COUNT_RESUME to now
|
||||
* Set 1: Master re-enable CP0_Count with unchanged bias, handling timer
|
||||
* interrupts since COUNT_RESUME
|
||||
* This can be used to freeze the timer to get a consistent snapshot of
|
||||
* the CP0_Count and timer interrupt pending state, while also resuming
|
||||
* safely without losing time or guest timer interrupts.
|
||||
* Other: Reserved, do not change.
|
||||
*/
|
||||
#define KVM_REG_MIPS_COUNT_CTL (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 0)
|
||||
#define KVM_REG_MIPS_COUNT_CTL_DC 0x00000001
|
||||
|
||||
/*
|
||||
* CP0_Count resume monotonic nanoseconds
|
||||
* The monotonic nanosecond time of the last set of COUNT_CTL.DC (master
|
||||
* disable). Any reads and writes of Count related registers while
|
||||
* COUNT_CTL.DC=1 will appear to occur at this time. When COUNT_CTL.DC is
|
||||
* cleared again (master enable) any timer interrupts since this time will be
|
||||
* emulated.
|
||||
* Modifications to times in the future are rejected.
|
||||
*/
|
||||
#define KVM_REG_MIPS_COUNT_RESUME (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 1)
|
||||
/*
|
||||
* CP0_Count rate in Hz
|
||||
* Specifies the rate of the CP0_Count timer in Hz. Modifications occur without
|
||||
* discontinuities in CP0_Count.
|
||||
*/
|
||||
#define KVM_REG_MIPS_COUNT_HZ (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 2)
|
||||
|
||||
|
||||
/*
|
||||
* KVM_REG_MIPS_FPU - Floating Point and MIPS SIMD Architecture (MSA) registers.
|
||||
*
|
||||
* bits[15..8] - Register subset (see definitions below).
|
||||
* bits[7..5] - Must be zero.
|
||||
* bits[4..0] - Register number within register subset.
|
||||
*/
|
||||
|
||||
#define KVM_REG_MIPS_FPR (KVM_REG_MIPS_FPU | 0x0000000000000000ULL)
|
||||
#define KVM_REG_MIPS_FCR (KVM_REG_MIPS_FPU | 0x0000000000000100ULL)
|
||||
#define KVM_REG_MIPS_MSACR (KVM_REG_MIPS_FPU | 0x0000000000000200ULL)
|
||||
|
||||
/*
|
||||
* KVM_REG_MIPS_FPR - Floating point / Vector registers.
|
||||
*/
|
||||
#define KVM_REG_MIPS_FPR_32(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U32 | (n))
|
||||
#define KVM_REG_MIPS_FPR_64(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U64 | (n))
|
||||
#define KVM_REG_MIPS_VEC_128(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U128 | (n))
|
||||
|
||||
/*
|
||||
* KVM_REG_MIPS_FCR - Floating point control registers.
|
||||
*/
|
||||
#define KVM_REG_MIPS_FCR_IR (KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 | 0)
|
||||
#define KVM_REG_MIPS_FCR_CSR (KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 | 31)
|
||||
|
||||
/*
|
||||
* KVM_REG_MIPS_MSACR - MIPS SIMD Architecture (MSA) control registers.
|
||||
*/
|
||||
#define KVM_REG_MIPS_MSA_IR (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 | 0)
|
||||
#define KVM_REG_MIPS_MSA_CSR (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 | 1)
|
||||
|
||||
|
||||
/*
|
||||
* KVM MIPS specific structures and definitions
|
||||
*
|
||||
*/
|
||||
struct kvm_debug_exit_arch {
|
||||
__u64 epc;
|
||||
};
|
||||
|
||||
/* for KVM_SET_GUEST_DEBUG */
|
||||
struct kvm_guest_debug_arch {
|
||||
};
|
||||
|
||||
/* definition of registers in kvm_run */
|
||||
struct kvm_sync_regs {
|
||||
};
|
||||
|
||||
/* dummy definition */
|
||||
struct kvm_sregs {
|
||||
};
|
||||
|
||||
struct kvm_mips_interrupt {
|
||||
/* in */
|
||||
__u32 cpu;
|
||||
__u32 irq;
|
||||
};
|
||||
|
||||
#endif /* __LINUX_KVM_MIPS_H */
|
||||
@@ -0,0 +1,603 @@
|
||||
/*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License, version 2, as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*
|
||||
* Copyright IBM Corp. 2007
|
||||
*
|
||||
* Authors: Hollis Blanchard <hollisb@us.ibm.com>
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_KVM_POWERPC_H
|
||||
#define __LINUX_KVM_POWERPC_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/* Select powerpc specific features in <linux/kvm.h> */
|
||||
#define __KVM_HAVE_SPAPR_TCE
|
||||
#define __KVM_HAVE_PPC_SMT
|
||||
#define __KVM_HAVE_IRQCHIP
|
||||
#define __KVM_HAVE_IRQ_LINE
|
||||
#define __KVM_HAVE_GUEST_DEBUG
|
||||
|
||||
struct kvm_regs {
|
||||
__u64 pc;
|
||||
__u64 cr;
|
||||
__u64 ctr;
|
||||
__u64 lr;
|
||||
__u64 xer;
|
||||
__u64 msr;
|
||||
__u64 srr0;
|
||||
__u64 srr1;
|
||||
__u64 pid;
|
||||
|
||||
__u64 sprg0;
|
||||
__u64 sprg1;
|
||||
__u64 sprg2;
|
||||
__u64 sprg3;
|
||||
__u64 sprg4;
|
||||
__u64 sprg5;
|
||||
__u64 sprg6;
|
||||
__u64 sprg7;
|
||||
|
||||
__u64 gpr[32];
|
||||
};
|
||||
|
||||
#define KVM_SREGS_E_IMPL_NONE 0
|
||||
#define KVM_SREGS_E_IMPL_FSL 1
|
||||
|
||||
#define KVM_SREGS_E_FSL_PIDn (1 << 0) /* PID1/PID2 */
|
||||
|
||||
/*
|
||||
* Feature bits indicate which sections of the sregs struct are valid,
|
||||
* both in KVM_GET_SREGS and KVM_SET_SREGS. On KVM_SET_SREGS, registers
|
||||
* corresponding to unset feature bits will not be modified. This allows
|
||||
* restoring a checkpoint made without that feature, while keeping the
|
||||
* default values of the new registers.
|
||||
*
|
||||
* KVM_SREGS_E_BASE contains:
|
||||
* CSRR0/1 (refers to SRR2/3 on 40x)
|
||||
* ESR
|
||||
* DEAR
|
||||
* MCSR
|
||||
* TSR
|
||||
* TCR
|
||||
* DEC
|
||||
* TB
|
||||
* VRSAVE (USPRG0)
|
||||
*/
|
||||
#define KVM_SREGS_E_BASE (1 << 0)
|
||||
|
||||
/*
|
||||
* KVM_SREGS_E_ARCH206 contains:
|
||||
*
|
||||
* PIR
|
||||
* MCSRR0/1
|
||||
* DECAR
|
||||
* IVPR
|
||||
*/
|
||||
#define KVM_SREGS_E_ARCH206 (1 << 1)
|
||||
|
||||
/*
|
||||
* Contains EPCR, plus the upper half of 64-bit registers
|
||||
* that are 32-bit on 32-bit implementations.
|
||||
*/
|
||||
#define KVM_SREGS_E_64 (1 << 2)
|
||||
|
||||
#define KVM_SREGS_E_SPRG8 (1 << 3)
|
||||
#define KVM_SREGS_E_MCIVPR (1 << 4)
|
||||
|
||||
/*
|
||||
* IVORs are used -- contains IVOR0-15, plus additional IVORs
|
||||
* in combination with an appropriate feature bit.
|
||||
*/
|
||||
#define KVM_SREGS_E_IVOR (1 << 5)
|
||||
|
||||
/*
|
||||
* Contains MAS0-4, MAS6-7, TLBnCFG, MMUCFG.
|
||||
* Also TLBnPS if MMUCFG[MAVN] = 1.
|
||||
*/
|
||||
#define KVM_SREGS_E_ARCH206_MMU (1 << 6)
|
||||
|
||||
/* DBSR, DBCR, IAC, DAC, DVC */
|
||||
#define KVM_SREGS_E_DEBUG (1 << 7)
|
||||
|
||||
/* Enhanced debug -- DSRR0/1, SPRG9 */
|
||||
#define KVM_SREGS_E_ED (1 << 8)
|
||||
|
||||
/* Embedded Floating Point (SPE) -- IVOR32-34 if KVM_SREGS_E_IVOR */
|
||||
#define KVM_SREGS_E_SPE (1 << 9)
|
||||
|
||||
/*
|
||||
* DEPRECATED! USE ONE_REG FOR THIS ONE!
|
||||
* External Proxy (EXP) -- EPR
|
||||
*/
|
||||
#define KVM_SREGS_EXP (1 << 10)
|
||||
|
||||
/* External PID (E.PD) -- EPSC/EPLC */
|
||||
#define KVM_SREGS_E_PD (1 << 11)
|
||||
|
||||
/* Processor Control (E.PC) -- IVOR36-37 if KVM_SREGS_E_IVOR */
|
||||
#define KVM_SREGS_E_PC (1 << 12)
|
||||
|
||||
/* Page table (E.PT) -- EPTCFG */
|
||||
#define KVM_SREGS_E_PT (1 << 13)
|
||||
|
||||
/* Embedded Performance Monitor (E.PM) -- IVOR35 if KVM_SREGS_E_IVOR */
|
||||
#define KVM_SREGS_E_PM (1 << 14)
|
||||
|
||||
/*
|
||||
* Special updates:
|
||||
*
|
||||
* Some registers may change even while a vcpu is not running.
|
||||
* To avoid losing these changes, by default these registers are
|
||||
* not updated by KVM_SET_SREGS. To force an update, set the bit
|
||||
* in u.e.update_special corresponding to the register to be updated.
|
||||
*
|
||||
* The update_special field is zero on return from KVM_GET_SREGS.
|
||||
*
|
||||
* When restoring a checkpoint, the caller can set update_special
|
||||
* to 0xffffffff to ensure that everything is restored, even new features
|
||||
* that the caller doesn't know about.
|
||||
*/
|
||||
#define KVM_SREGS_E_UPDATE_MCSR (1 << 0)
|
||||
#define KVM_SREGS_E_UPDATE_TSR (1 << 1)
|
||||
#define KVM_SREGS_E_UPDATE_DEC (1 << 2)
|
||||
#define KVM_SREGS_E_UPDATE_DBSR (1 << 3)
|
||||
|
||||
/*
|
||||
* In KVM_SET_SREGS, reserved/pad fields must be left untouched from a
|
||||
* previous KVM_GET_REGS.
|
||||
*
|
||||
* Unless otherwise indicated, setting any register with KVM_SET_SREGS
|
||||
* directly sets its value. It does not trigger any special semantics such
|
||||
* as write-one-to-clear. Calling KVM_SET_SREGS on an unmodified struct
|
||||
* just received from KVM_GET_SREGS is always a no-op.
|
||||
*/
|
||||
struct kvm_sregs {
|
||||
__u32 pvr;
|
||||
union {
|
||||
struct {
|
||||
__u64 sdr1;
|
||||
struct {
|
||||
struct {
|
||||
__u64 slbe;
|
||||
__u64 slbv;
|
||||
} slb[64];
|
||||
} ppc64;
|
||||
struct {
|
||||
__u32 sr[16];
|
||||
__u64 ibat[8];
|
||||
__u64 dbat[8];
|
||||
} ppc32;
|
||||
} s;
|
||||
struct {
|
||||
union {
|
||||
struct { /* KVM_SREGS_E_IMPL_FSL */
|
||||
__u32 features; /* KVM_SREGS_E_FSL_ */
|
||||
__u32 svr;
|
||||
__u64 mcar;
|
||||
__u32 hid0;
|
||||
|
||||
/* KVM_SREGS_E_FSL_PIDn */
|
||||
__u32 pid1, pid2;
|
||||
} fsl;
|
||||
__u8 pad[256];
|
||||
} impl;
|
||||
|
||||
__u32 features; /* KVM_SREGS_E_ */
|
||||
__u32 impl_id; /* KVM_SREGS_E_IMPL_ */
|
||||
__u32 update_special; /* KVM_SREGS_E_UPDATE_ */
|
||||
__u32 pir; /* read-only */
|
||||
__u64 sprg8;
|
||||
__u64 sprg9; /* E.ED */
|
||||
__u64 csrr0;
|
||||
__u64 dsrr0; /* E.ED */
|
||||
__u64 mcsrr0;
|
||||
__u32 csrr1;
|
||||
__u32 dsrr1; /* E.ED */
|
||||
__u32 mcsrr1;
|
||||
__u32 esr;
|
||||
__u64 dear;
|
||||
__u64 ivpr;
|
||||
__u64 mcivpr;
|
||||
__u64 mcsr; /* KVM_SREGS_E_UPDATE_MCSR */
|
||||
|
||||
__u32 tsr; /* KVM_SREGS_E_UPDATE_TSR */
|
||||
__u32 tcr;
|
||||
__u32 decar;
|
||||
__u32 dec; /* KVM_SREGS_E_UPDATE_DEC */
|
||||
|
||||
/*
|
||||
* Userspace can read TB directly, but the
|
||||
* value reported here is consistent with "dec".
|
||||
*
|
||||
* Read-only.
|
||||
*/
|
||||
__u64 tb;
|
||||
|
||||
__u32 dbsr; /* KVM_SREGS_E_UPDATE_DBSR */
|
||||
__u32 dbcr[3];
|
||||
/*
|
||||
* iac/dac registers are 64bit wide, while this API
|
||||
* interface provides only lower 32 bits on 64 bit
|
||||
* processors. ONE_REG interface is added for 64bit
|
||||
* iac/dac registers.
|
||||
*/
|
||||
__u32 iac[4];
|
||||
__u32 dac[2];
|
||||
__u32 dvc[2];
|
||||
__u8 num_iac; /* read-only */
|
||||
__u8 num_dac; /* read-only */
|
||||
__u8 num_dvc; /* read-only */
|
||||
__u8 pad;
|
||||
|
||||
__u32 epr; /* EXP */
|
||||
__u32 vrsave; /* a.k.a. USPRG0 */
|
||||
__u32 epcr; /* KVM_SREGS_E_64 */
|
||||
|
||||
__u32 mas0;
|
||||
__u32 mas1;
|
||||
__u64 mas2;
|
||||
__u64 mas7_3;
|
||||
__u32 mas4;
|
||||
__u32 mas6;
|
||||
|
||||
__u32 ivor_low[16]; /* IVOR0-15 */
|
||||
__u32 ivor_high[18]; /* IVOR32+, plus room to expand */
|
||||
|
||||
__u32 mmucfg; /* read-only */
|
||||
__u32 eptcfg; /* E.PT, read-only */
|
||||
__u32 tlbcfg[4];/* read-only */
|
||||
__u32 tlbps[4]; /* read-only */
|
||||
|
||||
__u32 eplc, epsc; /* E.PD */
|
||||
} e;
|
||||
__u8 pad[1020];
|
||||
} u;
|
||||
};
|
||||
|
||||
struct kvm_fpu {
|
||||
__u64 fpr[32];
|
||||
};
|
||||
|
||||
/*
|
||||
* Defines for h/w breakpoint, watchpoint (read, write or both) and
|
||||
* software breakpoint.
|
||||
* These are used as "type" in KVM_SET_GUEST_DEBUG ioctl and "status"
|
||||
* for KVM_DEBUG_EXIT.
|
||||
*/
|
||||
#define KVMPPC_DEBUG_NONE 0x0
|
||||
#define KVMPPC_DEBUG_BREAKPOINT (1UL << 1)
|
||||
#define KVMPPC_DEBUG_WATCH_WRITE (1UL << 2)
|
||||
#define KVMPPC_DEBUG_WATCH_READ (1UL << 3)
|
||||
struct kvm_debug_exit_arch {
|
||||
__u64 address;
|
||||
/*
|
||||
* exiting to userspace because of h/w breakpoint, watchpoint
|
||||
* (read, write or both) and software breakpoint.
|
||||
*/
|
||||
__u32 status;
|
||||
__u32 reserved;
|
||||
};
|
||||
|
||||
/* for KVM_SET_GUEST_DEBUG */
|
||||
struct kvm_guest_debug_arch {
|
||||
struct {
|
||||
/* H/W breakpoint/watchpoint address */
|
||||
__u64 addr;
|
||||
/*
|
||||
* Type denotes h/w breakpoint, read watchpoint, write
|
||||
* watchpoint or watchpoint (both read and write).
|
||||
*/
|
||||
__u32 type;
|
||||
__u32 reserved;
|
||||
} bp[16];
|
||||
};
|
||||
|
||||
/* Debug related defines */
|
||||
/*
|
||||
* kvm_guest_debug->control is a 32 bit field. The lower 16 bits are generic
|
||||
* and upper 16 bits are architecture specific. Architecture specific defines
|
||||
* that ioctl is for setting hardware breakpoint or software breakpoint.
|
||||
*/
|
||||
#define KVM_GUESTDBG_USE_SW_BP 0x00010000
|
||||
#define KVM_GUESTDBG_USE_HW_BP 0x00020000
|
||||
|
||||
/* definition of registers in kvm_run */
|
||||
struct kvm_sync_regs {
|
||||
};
|
||||
|
||||
#define KVM_INTERRUPT_SET -1U
|
||||
#define KVM_INTERRUPT_UNSET -2U
|
||||
#define KVM_INTERRUPT_SET_LEVEL -3U
|
||||
|
||||
#define KVM_CPU_440 1
|
||||
#define KVM_CPU_E500V2 2
|
||||
#define KVM_CPU_3S_32 3
|
||||
#define KVM_CPU_3S_64 4
|
||||
#define KVM_CPU_E500MC 5
|
||||
|
||||
/* for KVM_CAP_SPAPR_TCE */
|
||||
struct kvm_create_spapr_tce {
|
||||
__u64 liobn;
|
||||
__u32 window_size;
|
||||
};
|
||||
|
||||
/* for KVM_ALLOCATE_RMA */
|
||||
struct kvm_allocate_rma {
|
||||
__u64 rma_size;
|
||||
};
|
||||
|
||||
/* for KVM_CAP_PPC_RTAS */
|
||||
struct kvm_rtas_token_args {
|
||||
char name[120];
|
||||
__u64 token; /* Use a token of 0 to undefine a mapping */
|
||||
};
|
||||
|
||||
struct kvm_book3e_206_tlb_entry {
|
||||
__u32 mas8;
|
||||
__u32 mas1;
|
||||
__u64 mas2;
|
||||
__u64 mas7_3;
|
||||
};
|
||||
|
||||
struct kvm_book3e_206_tlb_params {
|
||||
/*
|
||||
* For mmu types KVM_MMU_FSL_BOOKE_NOHV and KVM_MMU_FSL_BOOKE_HV:
|
||||
*
|
||||
* - The number of ways of TLB0 must be a power of two between 2 and
|
||||
* 16.
|
||||
* - TLB1 must be fully associative.
|
||||
* - The size of TLB0 must be a multiple of the number of ways, and
|
||||
* the number of sets must be a power of two.
|
||||
* - The size of TLB1 may not exceed 64 entries.
|
||||
* - TLB0 supports 4 KiB pages.
|
||||
* - The page sizes supported by TLB1 are as indicated by
|
||||
* TLB1CFG (if MMUCFG[MAVN] = 0) or TLB1PS (if MMUCFG[MAVN] = 1)
|
||||
* as returned by KVM_GET_SREGS.
|
||||
* - TLB2 and TLB3 are reserved, and their entries in tlb_sizes[]
|
||||
* and tlb_ways[] must be zero.
|
||||
*
|
||||
* tlb_ways[n] = tlb_sizes[n] means the array is fully associative.
|
||||
*
|
||||
* KVM will adjust TLBnCFG based on the sizes configured here,
|
||||
* though arrays greater than 2048 entries will have TLBnCFG[NENTRY]
|
||||
* set to zero.
|
||||
*/
|
||||
__u32 tlb_sizes[4];
|
||||
__u32 tlb_ways[4];
|
||||
__u32 reserved[8];
|
||||
};
|
||||
|
||||
/* For KVM_PPC_GET_HTAB_FD */
|
||||
struct kvm_get_htab_fd {
|
||||
__u64 flags;
|
||||
__u64 start_index;
|
||||
__u64 reserved[2];
|
||||
};
|
||||
|
||||
/* Values for kvm_get_htab_fd.flags */
|
||||
#define KVM_GET_HTAB_BOLTED_ONLY ((__u64)0x1)
|
||||
#define KVM_GET_HTAB_WRITE ((__u64)0x2)
|
||||
|
||||
/*
|
||||
* Data read on the file descriptor is formatted as a series of
|
||||
* records, each consisting of a header followed by a series of
|
||||
* `n_valid' HPTEs (16 bytes each), which are all valid. Following
|
||||
* those valid HPTEs there are `n_invalid' invalid HPTEs, which
|
||||
* are not represented explicitly in the stream. The same format
|
||||
* is used for writing.
|
||||
*/
|
||||
struct kvm_get_htab_header {
|
||||
__u32 index;
|
||||
__u16 n_valid;
|
||||
__u16 n_invalid;
|
||||
};
|
||||
|
||||
/* Per-vcpu XICS interrupt controller state */
|
||||
#define KVM_REG_PPC_ICP_STATE (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8c)
|
||||
|
||||
#define KVM_REG_PPC_ICP_CPPR_SHIFT 56 /* current proc priority */
|
||||
#define KVM_REG_PPC_ICP_CPPR_MASK 0xff
|
||||
#define KVM_REG_PPC_ICP_XISR_SHIFT 32 /* interrupt status field */
|
||||
#define KVM_REG_PPC_ICP_XISR_MASK 0xffffff
|
||||
#define KVM_REG_PPC_ICP_MFRR_SHIFT 24 /* pending IPI priority */
|
||||
#define KVM_REG_PPC_ICP_MFRR_MASK 0xff
|
||||
#define KVM_REG_PPC_ICP_PPRI_SHIFT 16 /* pending irq priority */
|
||||
#define KVM_REG_PPC_ICP_PPRI_MASK 0xff
|
||||
|
||||
/* Device control API: PPC-specific devices */
|
||||
#define KVM_DEV_MPIC_GRP_MISC 1
|
||||
#define KVM_DEV_MPIC_BASE_ADDR 0 /* 64-bit */
|
||||
|
||||
#define KVM_DEV_MPIC_GRP_REGISTER 2 /* 32-bit */
|
||||
#define KVM_DEV_MPIC_GRP_IRQ_ACTIVE 3 /* 32-bit */
|
||||
|
||||
/* One-Reg API: PPC-specific registers */
|
||||
#define KVM_REG_PPC_HIOR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x1)
|
||||
#define KVM_REG_PPC_IAC1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x2)
|
||||
#define KVM_REG_PPC_IAC2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3)
|
||||
#define KVM_REG_PPC_IAC3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x4)
|
||||
#define KVM_REG_PPC_IAC4 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x5)
|
||||
#define KVM_REG_PPC_DAC1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x6)
|
||||
#define KVM_REG_PPC_DAC2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x7)
|
||||
#define KVM_REG_PPC_DABR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8)
|
||||
#define KVM_REG_PPC_DSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9)
|
||||
#define KVM_REG_PPC_PURR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa)
|
||||
#define KVM_REG_PPC_SPURR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb)
|
||||
#define KVM_REG_PPC_DAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc)
|
||||
#define KVM_REG_PPC_DSISR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xd)
|
||||
#define KVM_REG_PPC_AMR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xe)
|
||||
#define KVM_REG_PPC_UAMOR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xf)
|
||||
|
||||
#define KVM_REG_PPC_MMCR0 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x10)
|
||||
#define KVM_REG_PPC_MMCR1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x11)
|
||||
#define KVM_REG_PPC_MMCRA (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x12)
|
||||
#define KVM_REG_PPC_MMCR2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x13)
|
||||
#define KVM_REG_PPC_MMCRS (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x14)
|
||||
#define KVM_REG_PPC_SIAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x15)
|
||||
#define KVM_REG_PPC_SDAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x16)
|
||||
#define KVM_REG_PPC_SIER (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x17)
|
||||
|
||||
#define KVM_REG_PPC_PMC1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x18)
|
||||
#define KVM_REG_PPC_PMC2 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x19)
|
||||
#define KVM_REG_PPC_PMC3 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1a)
|
||||
#define KVM_REG_PPC_PMC4 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1b)
|
||||
#define KVM_REG_PPC_PMC5 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1c)
|
||||
#define KVM_REG_PPC_PMC6 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1d)
|
||||
#define KVM_REG_PPC_PMC7 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1e)
|
||||
#define KVM_REG_PPC_PMC8 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1f)
|
||||
|
||||
/* 32 floating-point registers */
|
||||
#define KVM_REG_PPC_FPR0 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x20)
|
||||
#define KVM_REG_PPC_FPR(n) (KVM_REG_PPC_FPR0 + (n))
|
||||
#define KVM_REG_PPC_FPR31 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3f)
|
||||
|
||||
/* 32 VMX/Altivec vector registers */
|
||||
#define KVM_REG_PPC_VR0 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x40)
|
||||
#define KVM_REG_PPC_VR(n) (KVM_REG_PPC_VR0 + (n))
|
||||
#define KVM_REG_PPC_VR31 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x5f)
|
||||
|
||||
/* 32 double-width FP registers for VSX */
|
||||
/* High-order halves overlap with FP regs */
|
||||
#define KVM_REG_PPC_VSR0 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x60)
|
||||
#define KVM_REG_PPC_VSR(n) (KVM_REG_PPC_VSR0 + (n))
|
||||
#define KVM_REG_PPC_VSR31 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x7f)
|
||||
|
||||
/* FP and vector status/control registers */
|
||||
#define KVM_REG_PPC_FPSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x80)
|
||||
/*
|
||||
* VSCR register is documented as a 32-bit register in the ISA, but it can
|
||||
* only be accesses via a vector register. Expose VSCR as a 32-bit register
|
||||
* even though the kernel represents it as a 128-bit vector.
|
||||
*/
|
||||
#define KVM_REG_PPC_VSCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x81)
|
||||
|
||||
/* Virtual processor areas */
|
||||
/* For SLB & DTL, address in high (first) half, length in low half */
|
||||
#define KVM_REG_PPC_VPA_ADDR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x82)
|
||||
#define KVM_REG_PPC_VPA_SLB (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x83)
|
||||
#define KVM_REG_PPC_VPA_DTL (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x84)
|
||||
|
||||
#define KVM_REG_PPC_EPCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x85)
|
||||
#define KVM_REG_PPC_EPR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x86)
|
||||
|
||||
/* Timer Status Register OR/CLEAR interface */
|
||||
#define KVM_REG_PPC_OR_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x87)
|
||||
#define KVM_REG_PPC_CLEAR_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x88)
|
||||
#define KVM_REG_PPC_TCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x89)
|
||||
#define KVM_REG_PPC_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8a)
|
||||
|
||||
/* Debugging: Special instruction for software breakpoint */
|
||||
#define KVM_REG_PPC_DEBUG_INST (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8b)
|
||||
|
||||
/* MMU registers */
|
||||
#define KVM_REG_PPC_MAS0 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8c)
|
||||
#define KVM_REG_PPC_MAS1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8d)
|
||||
#define KVM_REG_PPC_MAS2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8e)
|
||||
#define KVM_REG_PPC_MAS7_3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8f)
|
||||
#define KVM_REG_PPC_MAS4 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x90)
|
||||
#define KVM_REG_PPC_MAS6 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x91)
|
||||
#define KVM_REG_PPC_MMUCFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x92)
|
||||
/*
|
||||
* TLBnCFG fields TLBnCFG_N_ENTRY and TLBnCFG_ASSOC can be changed only using
|
||||
* KVM_CAP_SW_TLB ioctl
|
||||
*/
|
||||
#define KVM_REG_PPC_TLB0CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x93)
|
||||
#define KVM_REG_PPC_TLB1CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x94)
|
||||
#define KVM_REG_PPC_TLB2CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x95)
|
||||
#define KVM_REG_PPC_TLB3CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x96)
|
||||
#define KVM_REG_PPC_TLB0PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x97)
|
||||
#define KVM_REG_PPC_TLB1PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x98)
|
||||
#define KVM_REG_PPC_TLB2PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x99)
|
||||
#define KVM_REG_PPC_TLB3PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9a)
|
||||
#define KVM_REG_PPC_EPTCFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9b)
|
||||
|
||||
/* Timebase offset */
|
||||
#define KVM_REG_PPC_TB_OFFSET (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9c)
|
||||
|
||||
/* POWER8 registers */
|
||||
#define KVM_REG_PPC_SPMC1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9d)
|
||||
#define KVM_REG_PPC_SPMC2 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9e)
|
||||
#define KVM_REG_PPC_IAMR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9f)
|
||||
#define KVM_REG_PPC_TFHAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa0)
|
||||
#define KVM_REG_PPC_TFIAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa1)
|
||||
#define KVM_REG_PPC_TEXASR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa2)
|
||||
#define KVM_REG_PPC_FSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa3)
|
||||
#define KVM_REG_PPC_PSPB (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xa4)
|
||||
#define KVM_REG_PPC_EBBHR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa5)
|
||||
#define KVM_REG_PPC_EBBRR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa6)
|
||||
#define KVM_REG_PPC_BESCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa7)
|
||||
#define KVM_REG_PPC_TAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa8)
|
||||
#define KVM_REG_PPC_DPDES (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa9)
|
||||
#define KVM_REG_PPC_DAWR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xaa)
|
||||
#define KVM_REG_PPC_DAWRX (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xab)
|
||||
#define KVM_REG_PPC_CIABR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xac)
|
||||
#define KVM_REG_PPC_IC (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xad)
|
||||
#define KVM_REG_PPC_VTB (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xae)
|
||||
#define KVM_REG_PPC_CSIGR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xaf)
|
||||
#define KVM_REG_PPC_TACR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb0)
|
||||
#define KVM_REG_PPC_TCSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb1)
|
||||
#define KVM_REG_PPC_PID (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb2)
|
||||
#define KVM_REG_PPC_ACOP (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb3)
|
||||
|
||||
#define KVM_REG_PPC_VRSAVE (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb4)
|
||||
#define KVM_REG_PPC_LPCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb5)
|
||||
#define KVM_REG_PPC_LPCR_64 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb5)
|
||||
#define KVM_REG_PPC_PPR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb6)
|
||||
|
||||
/* Architecture compatibility level */
|
||||
#define KVM_REG_PPC_ARCH_COMPAT (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb7)
|
||||
|
||||
#define KVM_REG_PPC_DABRX (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb8)
|
||||
#define KVM_REG_PPC_WORT (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb9)
|
||||
#define KVM_REG_PPC_SPRG9 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xba)
|
||||
#define KVM_REG_PPC_DBSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbb)
|
||||
|
||||
/* Transactional Memory checkpointed state:
|
||||
* This is all GPRs, all VSX regs and a subset of SPRs
|
||||
*/
|
||||
#define KVM_REG_PPC_TM (KVM_REG_PPC | 0x80000000)
|
||||
/* TM GPRs */
|
||||
#define KVM_REG_PPC_TM_GPR0 (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0)
|
||||
#define KVM_REG_PPC_TM_GPR(n) (KVM_REG_PPC_TM_GPR0 + (n))
|
||||
#define KVM_REG_PPC_TM_GPR31 (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x1f)
|
||||
/* TM VSX */
|
||||
#define KVM_REG_PPC_TM_VSR0 (KVM_REG_PPC_TM | KVM_REG_SIZE_U128 | 0x20)
|
||||
#define KVM_REG_PPC_TM_VSR(n) (KVM_REG_PPC_TM_VSR0 + (n))
|
||||
#define KVM_REG_PPC_TM_VSR63 (KVM_REG_PPC_TM | KVM_REG_SIZE_U128 | 0x5f)
|
||||
/* TM SPRS */
|
||||
#define KVM_REG_PPC_TM_CR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x60)
|
||||
#define KVM_REG_PPC_TM_LR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x61)
|
||||
#define KVM_REG_PPC_TM_CTR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x62)
|
||||
#define KVM_REG_PPC_TM_FPSCR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x63)
|
||||
#define KVM_REG_PPC_TM_AMR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x64)
|
||||
#define KVM_REG_PPC_TM_PPR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x65)
|
||||
#define KVM_REG_PPC_TM_VRSAVE (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x66)
|
||||
#define KVM_REG_PPC_TM_VSCR (KVM_REG_PPC_TM | KVM_REG_SIZE_U32 | 0x67)
|
||||
#define KVM_REG_PPC_TM_DSCR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x68)
|
||||
#define KVM_REG_PPC_TM_TAR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x69)
|
||||
|
||||
/* PPC64 eXternal Interrupt Controller Specification */
|
||||
#define KVM_DEV_XICS_GRP_SOURCES 1 /* 64-bit source attributes */
|
||||
|
||||
/* Layout of 64-bit source attribute values */
|
||||
#define KVM_XICS_DESTINATION_SHIFT 0
|
||||
#define KVM_XICS_DESTINATION_MASK 0xffffffffULL
|
||||
#define KVM_XICS_PRIORITY_SHIFT 32
|
||||
#define KVM_XICS_PRIORITY_MASK 0xff
|
||||
#define KVM_XICS_LEVEL_SENSITIVE (1ULL << 40)
|
||||
#define KVM_XICS_MASKED (1ULL << 41)
|
||||
#define KVM_XICS_PENDING (1ULL << 42)
|
||||
|
||||
#endif /* __LINUX_KVM_POWERPC_H */
|
||||
@@ -0,0 +1,348 @@
|
||||
#ifndef _ASM_X86_KVM_H
|
||||
#define _ASM_X86_KVM_H
|
||||
|
||||
/*
|
||||
* KVM x86 specific structures and definitions
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/ioctl.h>
|
||||
|
||||
#define DE_VECTOR 0
|
||||
#define DB_VECTOR 1
|
||||
#define BP_VECTOR 3
|
||||
#define OF_VECTOR 4
|
||||
#define BR_VECTOR 5
|
||||
#define UD_VECTOR 6
|
||||
#define NM_VECTOR 7
|
||||
#define DF_VECTOR 8
|
||||
#define TS_VECTOR 10
|
||||
#define NP_VECTOR 11
|
||||
#define SS_VECTOR 12
|
||||
#define GP_VECTOR 13
|
||||
#define PF_VECTOR 14
|
||||
#define MF_VECTOR 16
|
||||
#define AC_VECTOR 17
|
||||
#define MC_VECTOR 18
|
||||
#define XM_VECTOR 19
|
||||
#define VE_VECTOR 20
|
||||
|
||||
/* Select x86 specific features in <linux/kvm.h> */
|
||||
#define __KVM_HAVE_PIT
|
||||
#define __KVM_HAVE_IOAPIC
|
||||
#define __KVM_HAVE_IRQ_LINE
|
||||
#define __KVM_HAVE_MSI
|
||||
#define __KVM_HAVE_USER_NMI
|
||||
#define __KVM_HAVE_GUEST_DEBUG
|
||||
#define __KVM_HAVE_MSIX
|
||||
#define __KVM_HAVE_MCE
|
||||
#define __KVM_HAVE_PIT_STATE2
|
||||
#define __KVM_HAVE_XEN_HVM
|
||||
#define __KVM_HAVE_VCPU_EVENTS
|
||||
#define __KVM_HAVE_DEBUGREGS
|
||||
#define __KVM_HAVE_XSAVE
|
||||
#define __KVM_HAVE_XCRS
|
||||
#define __KVM_HAVE_READONLY_MEM
|
||||
|
||||
/* Architectural interrupt line count. */
|
||||
#define KVM_NR_INTERRUPTS 256
|
||||
|
||||
struct kvm_memory_alias {
|
||||
__u32 slot; /* this has a different namespace than memory slots */
|
||||
__u32 flags;
|
||||
__u64 guest_phys_addr;
|
||||
__u64 memory_size;
|
||||
__u64 target_phys_addr;
|
||||
};
|
||||
|
||||
/* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
|
||||
struct kvm_pic_state {
|
||||
__u8 last_irr; /* edge detection */
|
||||
__u8 irr; /* interrupt request register */
|
||||
__u8 imr; /* interrupt mask register */
|
||||
__u8 isr; /* interrupt service register */
|
||||
__u8 priority_add; /* highest irq priority */
|
||||
__u8 irq_base;
|
||||
__u8 read_reg_select;
|
||||
__u8 poll;
|
||||
__u8 special_mask;
|
||||
__u8 init_state;
|
||||
__u8 auto_eoi;
|
||||
__u8 rotate_on_auto_eoi;
|
||||
__u8 special_fully_nested_mode;
|
||||
__u8 init4; /* true if 4 byte init */
|
||||
__u8 elcr; /* PIIX edge/trigger selection */
|
||||
__u8 elcr_mask;
|
||||
};
|
||||
|
||||
#define KVM_IOAPIC_NUM_PINS 24
|
||||
struct kvm_ioapic_state {
|
||||
__u64 base_address;
|
||||
__u32 ioregsel;
|
||||
__u32 id;
|
||||
__u32 irr;
|
||||
__u32 pad;
|
||||
union {
|
||||
__u64 bits;
|
||||
struct {
|
||||
__u8 vector;
|
||||
__u8 delivery_mode:3;
|
||||
__u8 dest_mode:1;
|
||||
__u8 delivery_status:1;
|
||||
__u8 polarity:1;
|
||||
__u8 remote_irr:1;
|
||||
__u8 trig_mode:1;
|
||||
__u8 mask:1;
|
||||
__u8 reserve:7;
|
||||
__u8 reserved[4];
|
||||
__u8 dest_id;
|
||||
} fields;
|
||||
} redirtbl[KVM_IOAPIC_NUM_PINS];
|
||||
};
|
||||
|
||||
#define KVM_IRQCHIP_PIC_MASTER 0
|
||||
#define KVM_IRQCHIP_PIC_SLAVE 1
|
||||
#define KVM_IRQCHIP_IOAPIC 2
|
||||
#define KVM_NR_IRQCHIPS 3
|
||||
|
||||
/* for KVM_GET_REGS and KVM_SET_REGS */
|
||||
struct kvm_regs {
|
||||
/* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
|
||||
__u64 rax, rbx, rcx, rdx;
|
||||
__u64 rsi, rdi, rsp, rbp;
|
||||
__u64 r8, r9, r10, r11;
|
||||
__u64 r12, r13, r14, r15;
|
||||
__u64 rip, rflags;
|
||||
};
|
||||
|
||||
/* for KVM_GET_LAPIC and KVM_SET_LAPIC */
|
||||
#define KVM_APIC_REG_SIZE 0x400
|
||||
struct kvm_lapic_state {
|
||||
char regs[KVM_APIC_REG_SIZE];
|
||||
};
|
||||
|
||||
struct kvm_segment {
|
||||
__u64 base;
|
||||
__u32 limit;
|
||||
__u16 selector;
|
||||
__u8 type;
|
||||
__u8 present, dpl, db, s, l, g, avl;
|
||||
__u8 unusable;
|
||||
__u8 padding;
|
||||
};
|
||||
|
||||
struct kvm_dtable {
|
||||
__u64 base;
|
||||
__u16 limit;
|
||||
__u16 padding[3];
|
||||
};
|
||||
|
||||
|
||||
/* for KVM_GET_SREGS and KVM_SET_SREGS */
|
||||
struct kvm_sregs {
|
||||
/* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
|
||||
struct kvm_segment cs, ds, es, fs, gs, ss;
|
||||
struct kvm_segment tr, ldt;
|
||||
struct kvm_dtable gdt, idt;
|
||||
__u64 cr0, cr2, cr3, cr4, cr8;
|
||||
__u64 efer;
|
||||
__u64 apic_base;
|
||||
__u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
|
||||
};
|
||||
|
||||
/* for KVM_GET_FPU and KVM_SET_FPU */
|
||||
struct kvm_fpu {
|
||||
__u8 fpr[8][16];
|
||||
__u16 fcw;
|
||||
__u16 fsw;
|
||||
__u8 ftwx; /* in fxsave format */
|
||||
__u8 pad1;
|
||||
__u16 last_opcode;
|
||||
__u64 last_ip;
|
||||
__u64 last_dp;
|
||||
__u8 xmm[16][16];
|
||||
__u32 mxcsr;
|
||||
__u32 pad2;
|
||||
};
|
||||
|
||||
struct kvm_msr_entry {
|
||||
__u32 index;
|
||||
__u32 reserved;
|
||||
__u64 data;
|
||||
};
|
||||
|
||||
/* for KVM_GET_MSRS and KVM_SET_MSRS */
|
||||
struct kvm_msrs {
|
||||
__u32 nmsrs; /* number of msrs in entries */
|
||||
__u32 pad;
|
||||
|
||||
struct kvm_msr_entry entries[0];
|
||||
};
|
||||
|
||||
/* for KVM_GET_MSR_INDEX_LIST */
|
||||
struct kvm_msr_list {
|
||||
__u32 nmsrs; /* number of msrs in entries */
|
||||
__u32 indices[0];
|
||||
};
|
||||
|
||||
|
||||
struct kvm_cpuid_entry {
|
||||
__u32 function;
|
||||
__u32 eax;
|
||||
__u32 ebx;
|
||||
__u32 ecx;
|
||||
__u32 edx;
|
||||
__u32 padding;
|
||||
};
|
||||
|
||||
/* for KVM_SET_CPUID */
|
||||
struct kvm_cpuid {
|
||||
__u32 nent;
|
||||
__u32 padding;
|
||||
struct kvm_cpuid_entry entries[0];
|
||||
};
|
||||
|
||||
struct kvm_cpuid_entry2 {
|
||||
__u32 function;
|
||||
__u32 index;
|
||||
__u32 flags;
|
||||
__u32 eax;
|
||||
__u32 ebx;
|
||||
__u32 ecx;
|
||||
__u32 edx;
|
||||
__u32 padding[3];
|
||||
};
|
||||
|
||||
#define KVM_CPUID_FLAG_SIGNIFCANT_INDEX BIT(0)
|
||||
#define KVM_CPUID_FLAG_STATEFUL_FUNC BIT(1)
|
||||
#define KVM_CPUID_FLAG_STATE_READ_NEXT BIT(2)
|
||||
|
||||
/* for KVM_SET_CPUID2 */
|
||||
struct kvm_cpuid2 {
|
||||
__u32 nent;
|
||||
__u32 padding;
|
||||
struct kvm_cpuid_entry2 entries[0];
|
||||
};
|
||||
|
||||
/* for KVM_GET_PIT and KVM_SET_PIT */
|
||||
struct kvm_pit_channel_state {
|
||||
__u32 count; /* can be 65536 */
|
||||
__u16 latched_count;
|
||||
__u8 count_latched;
|
||||
__u8 status_latched;
|
||||
__u8 status;
|
||||
__u8 read_state;
|
||||
__u8 write_state;
|
||||
__u8 write_latch;
|
||||
__u8 rw_mode;
|
||||
__u8 mode;
|
||||
__u8 bcd;
|
||||
__u8 gate;
|
||||
__s64 count_load_time;
|
||||
};
|
||||
|
||||
struct kvm_debug_exit_arch {
|
||||
__u32 exception;
|
||||
__u32 pad;
|
||||
__u64 pc;
|
||||
__u64 dr6;
|
||||
__u64 dr7;
|
||||
};
|
||||
|
||||
#define KVM_GUESTDBG_USE_SW_BP 0x00010000
|
||||
#define KVM_GUESTDBG_USE_HW_BP 0x00020000
|
||||
#define KVM_GUESTDBG_INJECT_DB 0x00040000
|
||||
#define KVM_GUESTDBG_INJECT_BP 0x00080000
|
||||
|
||||
/* for KVM_SET_GUEST_DEBUG */
|
||||
struct kvm_guest_debug_arch {
|
||||
__u64 debugreg[8];
|
||||
};
|
||||
|
||||
struct kvm_pit_state {
|
||||
struct kvm_pit_channel_state channels[3];
|
||||
};
|
||||
|
||||
#define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001
|
||||
|
||||
struct kvm_pit_state2 {
|
||||
struct kvm_pit_channel_state channels[3];
|
||||
__u32 flags;
|
||||
__u32 reserved[9];
|
||||
};
|
||||
|
||||
struct kvm_reinject_control {
|
||||
__u8 pit_reinject;
|
||||
__u8 reserved[31];
|
||||
};
|
||||
|
||||
/* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */
|
||||
#define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001
|
||||
#define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002
|
||||
#define KVM_VCPUEVENT_VALID_SHADOW 0x00000004
|
||||
|
||||
/* Interrupt shadow states */
|
||||
#define KVM_X86_SHADOW_INT_MOV_SS 0x01
|
||||
#define KVM_X86_SHADOW_INT_STI 0x02
|
||||
|
||||
/* for KVM_GET/SET_VCPU_EVENTS */
|
||||
struct kvm_vcpu_events {
|
||||
struct {
|
||||
__u8 injected;
|
||||
__u8 nr;
|
||||
__u8 has_error_code;
|
||||
__u8 pad;
|
||||
__u32 error_code;
|
||||
} exception;
|
||||
struct {
|
||||
__u8 injected;
|
||||
__u8 nr;
|
||||
__u8 soft;
|
||||
__u8 shadow;
|
||||
} interrupt;
|
||||
struct {
|
||||
__u8 injected;
|
||||
__u8 pending;
|
||||
__u8 masked;
|
||||
__u8 pad;
|
||||
} nmi;
|
||||
__u32 sipi_vector;
|
||||
__u32 flags;
|
||||
__u32 reserved[10];
|
||||
};
|
||||
|
||||
/* for KVM_GET/SET_DEBUGREGS */
|
||||
struct kvm_debugregs {
|
||||
__u64 db[4];
|
||||
__u64 dr6;
|
||||
__u64 dr7;
|
||||
__u64 flags;
|
||||
__u64 reserved[9];
|
||||
};
|
||||
|
||||
/* for KVM_CAP_XSAVE */
|
||||
struct kvm_xsave {
|
||||
__u32 region[1024];
|
||||
};
|
||||
|
||||
#define KVM_MAX_XCRS 16
|
||||
|
||||
struct kvm_xcr {
|
||||
__u32 xcr;
|
||||
__u32 reserved;
|
||||
__u64 value;
|
||||
};
|
||||
|
||||
struct kvm_xcrs {
|
||||
__u32 nr_xcrs;
|
||||
__u32 flags;
|
||||
struct kvm_xcr xcrs[KVM_MAX_XCRS];
|
||||
__u64 padding[16];
|
||||
};
|
||||
|
||||
/* definition of registers in kvm_run */
|
||||
struct kvm_sync_regs {
|
||||
};
|
||||
|
||||
#endif /* _ASM_X86_KVM_H */
|
||||
Reference in New Issue
Block a user