OERV-BSP/kernel-sophgo-sg2044
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Author SHA1 Message Date
Han Gao
310e621d9f REVYOS: ci: add cross/native build 
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-22 19:36:14 +08:00
Han Gao
a2386f751a REVYOS: config: add linuxboot config 
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-22 19:36:14 +08:00
Han Gao
441cd15528 REVYOS: config: enable AMD HSA feature 
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-22 19:36:13 +08:00
Han Gao
a49828d263 REVYOS: config: enable i2c for gd32 
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-22 19:36:13 +08:00
Han Gao
e83e1ff9c9 REVYOS: config: add SG2044 config 
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-22 19:36:13 +08:00
Han Gao
1400c54c18 REVYOS: config: remove sign & compress module 
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-22 19:36:13 +08:00
Han Gao
6c28fd56a0 REVYOS: config: sync debian 6.12.20 config 
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-22 19:36:13 +08:00
Han Gao
257bbf3b37 REVYOS: package: debian: linux-image provide wireguard-modules 
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-22 19:36:13 +08:00
Han Gao
a388581827 REVYOS: HACK: using the major version number as package name 
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-22 19:36:13 +08:00
Inochi Amaoto
6701248212 REVYOS: SG2044: irqchip/sg2042-msi: Set MSI_FLAG_MULTI_PCI_MSI flags for SG2044 
The MSI controller on SG2044 has the ability to allocate
multiple PCI MSI interrupt if the controller supports it.
Add the missing flag so the controller can make full use
of it.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
 2025-07-22 19:36:13 +08:00
Inochi Amaoto
616a7b35af REVYOS: SG2044: irqchip/sg2042-msi: Use enable irq for irq_unmask 
The PLIC only reapply affinity when the irq is enabled in
irq_set_affinity, which makes the affinity is not be set
when the msi controller unmask the interrupt. So use
irq_chip_enable_parent for irq_unmask to force setting
the affinity.

Reported-by: Han Gao <rabenda.cn@gmail.com>
Fixes: e96b93a97c ("irqchip/sg2042-msi: Add the Sophgo SG2044 MSI interrupt controller")
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
 2025-07-22 19:36:13 +08:00
Inochi Amaoto
5bd7edeb7f SOPHGO: i2c: designware: Add ACPI HID for DWAPB I2C controller on Sophgo SG2044 
Add ACPI ID for DWAPB I2C controller on Sophgo SG2044 so
the SoC can enumerated the device via ACPI.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-22 19:35:37 +08:00
Inochi Amaoto
b047020e54 SOPHGO: spi: dw: Add ACPI ID for the Sophgo SG2044 SoC SPI 
The Sophgo SG2044 SoC can enumerated its SPI device via ACPI.
Add ACPI ID for it.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-22 19:35:37 +08:00
Inochi Amaoto
4f14715bc5 SOPHGO: serial: 8250_dw: Add ACPI ID for Sophgo SG2044 UART 
The UART on Sophgo SG2044 can be enumerated via ACPI.
Add ACPI ID for it.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-22 19:35:37 +08:00
Inochi Amaoto
2f75d3cc55 SOPHGO: perf vendor events riscv: add T-HEAD C920V2 JSON file 
Add JSON file of T-HEAD C920V2 core events.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
 2025-07-22 19:35:37 +08:00
Inochi Amaoto
970cf0f22b SOPHGO: riscv: dts: sophgo: sg2044: Add eFUSE device 
Add eFUSE controller node for SG2044.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
 2025-07-22 19:35:37 +08:00
Inochi Amaoto
13157be954 SOPHGO: nvmem: Add Sophgo SG2044 eFuse driver 
Sophgo SoCs such as SG2044 contain eFuses used to store
factory-programmed data.

As for SG2044, HW automatically loads the eFuse content
into shadow registers which are organized as 32bit values
exposed as MMIO.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
 2025-07-22 19:35:37 +08:00
Inochi Amaoto
b3af53269b SOPHGO: dt-bindings: nvmem: Add SG2044 eFuse controller 
Sophgo SG2044 uses eFuses used to store factory-programmed data
such as ROM patch, public keys and other factory information.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
 2025-07-22 19:35:37 +08:00
Icenowy Zheng
71791aa3ad FROMLIST: drm/ttm: add pgprot handling for RISC-V 
The RISC-V Svpbmt privileged extension provides support for overriding
page memory coherency attributes, and, along with vendor extensions like
Xtheadmae, supports pgprot_{writecombine,noncached} on RISC-V.

Adapt the codepath that maps ttm_write_combined to pgprot_writecombine
and ttm_noncached to pgprot_noncached to RISC-V, to allow proper page
access attributes.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Tested-by: Han Gao <rabenda.cn@gmail.com>
Link: https://lore.kernel.org/r/20250722112050.909616-1-uwu@icenowy.me
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-22 19:35:37 +08:00
Yunhui Cui
3d19b5cfb9 FROMLIST: riscv: introduce ioremap_wc() 
Compared with IO attributes, NC attributes can improve performance,
specifically in these aspects: Relaxed Order, Gathering, Supports Read
Speculation, Supports Unaligned Access.

Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com>
Signed-off-by: Qingfang Deng <qingfang.deng@siflower.com.cn>
Link: https://lore.kernel.org/r/20250722091504.45974-2-cuiyunhui@bytedance.com
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-22 19:35:37 +08:00
Inochi Amaoto
7dac5e1152 FROMLIST: riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property 
The kernel complains no "riscv,cbop-block-size" and disables the Zicbop
extension. Add the missing property to keep it functional.

Fixes: ae5bac370e ("riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10")
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20250613074513.1683624-1-inochiama@gmail.com
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:59 +08:00
Han Gao
009ac1e9b8 FROMLIST: riscv: dts: sophgo: sg2044: add ziccrse extension 
sg2044 support ziccrse extension.

Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com>
Link: https://lore.kernel.org/r/0889174f2e013e095b94940614f4a0a6e614b09c.1751858054.git.rabenda.cn@gmail.com
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:59 +08:00
Inochi Amaoto
9926171070 FROMLIST: riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device 
As the uart0 is already occupied by the firmware, reserve it
to avoid this port is used by mistake.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20250703004024.85221-1-inochiama@gmail.com
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:59 +08:00
Inochi Amaoto
8f168e0335 FROMLIST: riscv: dts: sophgo: sg2044: add pmu configuration 
Add PMU configuration for the cpu of sg2044, which is the V2
version of C920.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20250703003844.84617-1-inochiama@gmail.com
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:58 +08:00
Inochi Amaoto
afe37798b2 FROMLIST: riscv: dts: sophgo: sg2044: add PCIe device support for SG2044 
Add PCIe device node for SG2044 and configuration for Sophgo SRD3-10.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20250618015851.272188-3-inochiama@gmail.com
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:58 +08:00
Inochi Amaoto
d304f50ff1 FROMLIST: riscv: dts: sophgo: sg2044: add MSI device support for SG2044 
Add MSI device tree node for SG2044.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/20250618015851.272188-2-inochiama@gmail.com
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:58 +08:00
Inochi Amaoto
9c98acf0c3 FROMLIST: PCI: sophgo-dwc: Add Sophgo SG2044 PCIe driver 
Add support for DesignWare-based PCIe controller in SG2044 SoC.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20250504004420.202685-3-inochiama@gmail.com
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:58 +08:00
Inochi Amaoto
540d47caee FROMLIST: dt-bindings: pci: Add Sophgo SG2044 PCIe host 
The pcie controller on the SG2044 is designware based with
custom app registers.

Add binding document for SG2044 PCIe host controller.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250504004420.202685-2-inochiama@gmail.com
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:58 +08:00
Inochi Amaoto
0f6f5e64f0 FROMLIST: riscv: dts: sophgo: sophgo-srd3-10: add HWMON MCU device 
Add MCU devicetree node for Sophgo SRD3-10 board. This is used to
provide SUSP function for the board.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20250608232836.784737-8-inochiama@gmail.com
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:58 +08:00
Inochi Amaoto
f45be2221c FROMLIST: riscv: dts: sophgo: sg2044: Add I2C device 
The I2C controller of SG2044 is a standard Synopsys IP, with one
the ref clock is need.

Add I2C DT node for SG2044 SoC.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20250608232836.784737-5-inochiama@gmail.com
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:58 +08:00
Longbin Li
79aa2f219f FROMLIST: riscv: dts: sophgo: add pwm controller for SG2044 
Add pwm device node for SG2044.

Signed-off-by: Longbin Li <looong.bin@gmail.com>
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/20250608232836.784737-12-inochiama@gmail.com
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:58 +08:00
Longbin Li
19f27ccc45 FROMLIST: riscv: dts: sophgo: add SG2044 SPI NOR controller driver 
Add SPI NOR device node for SG2044.

Signed-off-by: Longbin Li <looong.bin@gmail.com>
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20250608232836.784737-11-inochiama@gmail.com
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:58 +08:00
Inochi Amaoto
47835fedf1 FROMLIST: riscv: dts: sophgo: sg2044: Add pinctrl device 
Add pinctrl DT node and configuration for SG2044.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20250608232836.784737-10-inochiama@gmail.com
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:58 +08:00
Inochi Amaoto
403900aaee FROMLIST: riscv: dts: sophgo: sg2044: Add ethernet control device 
Add ethernet control node for sg2044.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20250608232836.784737-9-inochiama@gmail.com
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:58 +08:00
Inochi Amaoto
2b801226e5 FROMLIST: riscv: dts: sophgo: sophgo-srd3-10: add HWMON MCU device 
Add MCU devicetree node for Sophgo SRD3-10 board. This is used to
provide SUSP function for the board.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20250608232836.784737-8-inochiama@gmail.com
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:58 +08:00
Inochi Amaoto
7e55817467 FROMLIST: riscv: dts: sophgo: sg2044: Add MMC controller device 
Add emmc controller and sd controller DT node for SG2044.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20250608232836.784737-7-inochiama@gmail.com
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:58 +08:00
Inochi Amaoto
249c4e5601 FROMLIST: riscv: dts: sophgo: sg2044: add DMA controller device 
The DMA controller of SG2044 is a standard Synopsys IP, which is
already supported by the kernel.

Add DMA controller DT node for SG2044.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20250608232836.784737-6-inochiama@gmail.com
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:58 +08:00
Inochi Amaoto
7f372ee9be FROMLIST: riscv: dts: sophgo: sg2044: Add I2C device 
The I2C controller of SG2044 is a standard Synopsys IP, with one
the ref clock is need.

Add I2C DT node for SG2044 SoC.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20250608232836.784737-5-inochiama@gmail.com
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:58 +08:00
Inochi Amaoto
13c75910f3 FROMLIST: riscv: dts: sophgo: sg2044: Add GPIO device 
The GPIO controller is a standard Synopsys IP, which is already
supported by the kernel.

Add GPIO DT node for SG2044 SoC.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20250608232836.784737-4-inochiama@gmail.com
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:58 +08:00
Inochi Amaoto
7653e5e23f FROMLIST: riscv: dts: sophgo: sg2044: Add clock controller device 
Add clock controller and pll clock node for sg2044.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20250608232836.784737-3-inochiama@gmail.com
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:58 +08:00
Inochi Amaoto
8cc218b1f4 FROMLIST: riscv: dts: sophgo: sg2044: Add system controller device 
The TOP system controller device is necessary for the SG2044 clock
controller. Add it to the SoC device tree.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/r/20250608232836.784737-2-inochiama@gmail.com
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:58 +08:00
Longbin Li
4396916cfd FROMLIST: pwm: sophgo: add driver for SG2044 
Add PWM controller for SG2044 on base of SG2042.

Signed-off-by: Longbin Li <looong.bin@gmail.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Tested-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/20250528101139.28702-4-looong.bin@gmail.com
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:58 +08:00
Longbin Li
0f3862afd5 FROMLIST: pwm: sophgo: reorganize the code structure 
As the driver logic can be used in both SG2042 and SG2044, it
will be better to reorganize the code structure.

Signed-off-by: Longbin Li <looong.bin@gmail.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Tested-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/20250528101139.28702-3-looong.bin@gmail.com
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:58 +08:00
Longbin Li
1ce780ce7f FROMLIST: dt-bindings: pwm: sophgo: add pwm controller for SG2044 
Add compatible string for PWM controller on SG2044.

Signed-off-by: Longbin Li <looong.bin@gmail.com>
Tested-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250528101139.28702-2-looong.bin@gmail.com
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:57 +08:00
Jessica Liu
8ab3dda380 FROMLIST: riscv: mmap(): use unsigned offset type in riscv_sys_mmap 
The variable type of offset should be consistent with the relevant
interfaces of mmap which described in commit 295f10061a ("syscalls:
mmap(): use unsigned offset type consistently). Otherwise, a user input
with the top bit set would result in a negative page offset rather than a
large one.

Signed-off-by: Jessica Liu <liu.xuemei1@zte.com.cn>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Nutty Liu <liujingqi@lanxincomputing.com>
Link: https://lore.kernel.org/r/20250707193411886Kc-TWknP0PER2_sEg-byb@zte.com.cn
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:57 +08:00
Inochi Amaoto
8f426c4a1a UPSTREAM: irqchip/sg2042-msi: Fix wrong type cast in sg2044_msi_irq_ack() 
The type cast in sg2044_msi_irq_ack() lost the __iomem attribute, which
makes the pointer type incorrect.

Add it back.

Fixes: e96b93a97c ("irqchip/sg2042-msi: Add the Sophgo SG2044 MSI interrupt controller")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/all/20250422003804.214264-1-inochiama@gmail.com
Closes: https://lore.kernel.org/oe-kbuild-all/202504211251.B3aesulq-lkp@intel.com/
(cherry picked from commit 76b66e8c9d)
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:57 +08:00
Inochi Amaoto
1d54b368eb UPSTREAM: irqchip/sg2042-msi: Add the Sophgo SG2044 MSI interrupt controller 
Add support for Sophgo SG2044 MSI interrupt controller.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Chen Wang <wangchen20@iscas.ac.cn> # SG2042
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/all/20250413224922.69719-5-inochiama@gmail.com

(cherry picked from commit e96b93a97c)
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:57 +08:00
Inochi Amaoto
f71ffd7baa UPSTREAM: irqchip/sg2042-msi: Introduce configurable chipinfo for SG2042 
As the controller on SG2044 uses different msi_parent_ops and a difffernt
irq_chip, it is necessary to provide that information to the probe function.

Add a new chipinfo structure to hold that information, implement the
necessary logic and make SG2042 use it.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Chen Wang <wangchen20@iscas.ac.cn> # SG2042
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/all/20250413224922.69719-4-inochiama@gmail.com

(cherry picked from commit bad2094e3b)
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:57 +08:00
Inochi Amaoto
2ef0a13d79 UPSTREAM: irqchip/sg2042-msi: Rename functions and data structures to be SG2042 agnostic 
As the driver logic can be used in both SG2042 and SG2044 SoCs, rename
functions and data structures, which are not SG2042 specific, to SG204x*.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Chen Wang <wangchen20@iscas.ac.cn> # SG2042
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/all/20250413224922.69719-3-inochiama@gmail.com

(cherry picked from commit bced55494c)
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:57 +08:00
Inochi Amaoto
32b5ee9e34 UPSTREAM: dt-bindings: interrupt-controller: Add Sophgo SG2044 MSI controller 
Like SG2042, SG2044 also uses an external MSI controller to provide
MSI interrupt for PCIe controllers. The difference between these
two MSI controllers are:

  1. SG2044 acks the interrupt by writing 0, SG2042 by setting the
     bit related to the interrupt.

  2. SG2044 uses interrupt number modulo 32 as MSI message data, but
     SG2042 uses the bit related to the interrupt.

Add support for the SG2044 MSI controller.

Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Chen Wang <wangchen20@iscas.ac.cn> # SG2042
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/all/20250413224922.69719-2-inochiama@gmail.com

(cherry picked from commit 9fe5a0790a)
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
 2025-07-18 23:50:57 +08:00