target/riscv: Xuantie CPU support

1. Support Xuantie R908/c920v3, more cpu can be list by -cpu help option.
2. Align to git commit 62dbe54c24dbf77051bafe1039c31ddc8f37602d(9.0.0-rc4)

MAINTAINERS

@@ -355,6 +355,7 @@ L: qemu-riscv@nongnu.org
 S: Supported
 F: target/riscv/insn_trans/trans_xthead.c.inc
 F: target/riscv/xthead*.decode
+F: target/riscv/th_*
 F: disas/riscv-xthead*
 
 RISC-V XVentanaCondOps extension

accel/tcg/translate-all.c

@@ -65,6 +65,7 @@
 #include "internal-target.h"
 #include "tcg/perf.h"
 #include "tcg/insn-start-words.h"
+#include "exec/tracestub.h"
 
 TBContext tb_ctx;
 
@@ -593,6 +594,17 @@ void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr)
 }
 
 #ifndef CONFIG_USER_ONLY
+static int
+cpu_unwind_data_from_tb_pcrel(TranslationBlock *tb, uintptr_t host_pc,
+                              uint64_t *data)
+{
+    assert(tb_cflags(tb) & CF_PCREL);
+    const uint8_t *p = tb->tc.ptr + tb->tc.size;
+    memset(data, 0, sizeof(uint64_t) * TARGET_INSN_START_WORDS);
+    data[0] = decode_sleb128(&p);
+    return 0;
+}
+
 /*
  * In deterministic execution mode, instructions doing device I/Os
  * must be at the end of the TB.
@@ -610,8 +622,24 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
         cpu_abort(cpu, "cpu_io_recompile: could not find TB for pc=%p",
                   (void *)retaddr);
     }
+    /*
+     * After dcd092a0636ec36e69e42a3dbbe447d97cb0d113, mmio in tb will
+     * cause tb retranslation, thus we should exit current tb
+     */
+    if (gen_tb_trace()) {
+        uint64_t data[TARGET_INSN_START_WORDS];
+        uint64_t tb_size;
+        cpu_unwind_data_from_tb(tb, retaddr, data);
+        if (!(tb_cflags(tb) & CF_PCREL)) {
+            tb_size = data[0] - tb->pc;
+        } else {
+            tb_size = data[0];
+            cpu_unwind_data_from_tb_pcrel(tb, retaddr, data);
+            tb_size -= data[0];
+        }
+        extern_helper_trace_tb_exit(0x2, tb_size);
+    }
     cpu_restore_state_from_tb(cpu, tb, retaddr);
-
     /*
      * Some guests must re-execute the branch when re-executing a delay
      * slot instruction.  When this is the case, adjust icount and N

configs/devices/cskyv1-softmmu.mak

@@ -0,0 +1,15 @@
+#Default configuration for cskyv1-softmmu
+
+CONFIG_SEMIHOSTING=y
+# Boards:
+#
+CONFIG_SMARTL=y
+CONFIG_CSKY_VIRT=y
+CONFIG_YUNVOICE_V2=y
+CONFIG_TRILOBITE=y
+CONFIG_TRILOBITE_V2=y
+CONFIG_SMART_CARD=y
+CONFIG_HOBBIT1_V2=y
+CONFIG_DEIMOS=y
+CONFIG_SMARTH=y
+CONFIG_DUMMYH=y

configs/devices/cskyv1-softmmu/default.mak

@@ -0,0 +1,15 @@
+#Default configuration for cskyv1-softmmu
+
+CONFIG_SEMIHOSTING=y
+# Boards:
+#
+CONFIG_SMARTL=y
+CONFIG_CSKY_VIRT=y
+CONFIG_YUNVOICE_V2=y
+CONFIG_TRILOBITE=y
+CONFIG_TRILOBITE_V2=y
+CONFIG_SMART_CARD=y
+CONFIG_HOBBIT1_V2=y
+CONFIG_DEIMOS=y
+CONFIG_SMARTH=y
+CONFIG_DUMMYH=y

configs/devices/cskyv1eb-softmmu.mak

@@ -0,0 +1,15 @@
+#Default configuration for cskyv1eb-softmmu
+
+CONFIG_SEMIHOSTING=y
+# Boards:
+#
+CONFIG_SMARTL=y
+CONFIG_CSKY_VIRT=y
+CONFIG_YUNVOICE_V2=y
+CONFIG_TRILOBITE=y
+CONFIG_TRILOBITE_V2=y
+CONFIG_SMART_CARD=y
+CONFIG_HOBBIT1_V2=y
+CONFIG_DEIMOS=y
+CONFIG_SMARTH=y
+CONFIG_DUMMYH=y

configs/devices/cskyv1eb-softmmu/default.mak

@@ -0,0 +1,15 @@
+#Default configuration for cskyv1eb-softmmu
+
+CONFIG_SEMIHOSTING=y
+# Boards:
+#
+CONFIG_SMARTL=y
+CONFIG_CSKY_VIRT=y
+CONFIG_YUNVOICE_V2=y
+CONFIG_TRILOBITE=y
+CONFIG_TRILOBITE_V2=y
+CONFIG_SMART_CARD=y
+CONFIG_HOBBIT1_V2=y
+CONFIG_DEIMOS=y
+CONFIG_SMARTH=y
+CONFIG_DUMMYH=y

configs/devices/cskyv2-softmmu.mak

@@ -0,0 +1,15 @@
+#Default configuration for cskyv2-softmmu
+
+CONFIG_SEMIHOSTING=y
+# Boards:
+#
+CONFIG_SMARTL=y
+CONFIG_CSKY_VIRT=y
+CONFIG_YUNVOICE_V2=y
+CONFIG_TRILOBITE=y
+CONFIG_TRILOBITE_V2=y
+CONFIG_SMART_CARD=y
+CONFIG_HOBBIT1_V2=y
+CONFIG_DEIMOS=y
+CONFIG_SMARTH=y
+CONFIG_DUMMYH=y

configs/devices/cskyv2-softmmu/default.mak

@@ -0,0 +1,15 @@
+#Default configuration for cskyv2-softmmu
+
+CONFIG_SEMIHOSTING=y
+# Boards:
+#
+CONFIG_SMARTL=y
+CONFIG_CSKY_VIRT=y
+CONFIG_YUNVOICE_V2=y
+CONFIG_TRILOBITE=y
+CONFIG_TRILOBITE_V2=y
+CONFIG_SMART_CARD=y
+CONFIG_HOBBIT1_V2=y
+CONFIG_DEIMOS=y
+CONFIG_SMARTH=y
+CONFIG_DUMMYH=y

configs/devices/cskyv2eb-softmmu.mak

@@ -0,0 +1,15 @@
+#Default configuration for cskyv2eb-softmmu
+
+CONFIG_SEMIHOSTING=y
+# Boards:
+#
+CONFIG_SMARTL=y
+CONFIG_CSKY_VIRT=y
+CONFIG_YUNVOICE_V2=y
+CONFIG_TRILOBITE=y
+CONFIG_TRILOBITE_V2=y
+CONFIG_SMART_CARD=y
+CONFIG_HOBBIT1_V2=y
+CONFIG_DEIMOS=y
+CONFIG_SMARTH=y
+CONFIG_DUMMYH=y

configs/devices/cskyv2eb-softmmu/default.mak

@@ -0,0 +1,15 @@
+#Default configuration for cskyv2eb-softmmu
+
+CONFIG_SEMIHOSTING=y
+# Boards:
+#
+CONFIG_SMARTL=y
+CONFIG_CSKY_VIRT=y
+CONFIG_YUNVOICE_V2=y
+CONFIG_TRILOBITE=y
+CONFIG_TRILOBITE_V2=y
+CONFIG_SMART_CARD=y
+CONFIG_HOBBIT1_V2=y
+CONFIG_DEIMOS=y
+CONFIG_SMARTH=y
+CONFIG_DUMMYH=y

configs/devices/riscv32-softmmu/default.mak

@@ -11,3 +11,8 @@ CONFIG_SIFIVE_E=y
 CONFIG_SIFIVE_U=y
 CONFIG_RISCV_VIRT=y
 CONFIG_OPENTITAN=y
+CONFIG_RISCV_CLIC=y
+CONFIG_RISCV_SMARTL=y
+CONFIG_RISCV_DUMMYH=y
+CONFIG_THEAD_ASP_V1=y
+CONFIG_RISCV_XIAOHUI=y

configs/devices/riscv64-softmmu/default.mak

@@ -12,3 +12,7 @@ CONFIG_SIFIVE_U=y
 CONFIG_RISCV_VIRT=y
 CONFIG_MICROCHIP_PFSOC=y
 CONFIG_SHAKTI_C=y
+CONFIG_RISCV_CLIC=y
+CONFIG_RISCV_SMARTH=y
+CONFIG_RISCV_DUMMYH=y
+CONFIG_RISCV_XIAOHUI=y

configs/targets/cskyv1-linux-user.mak

@@ -0,0 +1,8 @@
+TARGET_ARCH=cskyv1
+TARGET_BASE_ARCH=csky
+TARGET_ABI_DIR=csky
+TARGET_HAS_BFLT=y
+TARGET_CSKYV1=y
+TARGET_XML_FILES= gdb-xml/csky-abiv1-linux-user-core.xml gdb-xml/csky-abiv1-softmmu-core.xml
+CONFIG_CSKY_KERNEL_4X=y
+CONFIG_CSKY_TRACE=y

configs/targets/cskyv1-softmmu.mak

@@ -0,0 +1,8 @@
+TARGET_ARCH=cskyv1
+TARGET_BASE_ARCH=csky
+TARGET_ABI_DIR=csky
+TARGET_HAS_BFLT=y
+TARGET_CSKYV1=y
+TARGET_XML_FILES= gdb-xml/csky-abiv1-linux-user-core.xml gdb-xml/csky-abiv1-softmmu-core.xml
+TARGET_NEED_FDT=y
+CONFIG_CSKY_TRACE=y

configs/targets/cskyv1eb-linux-user.mak

@@ -0,0 +1,8 @@
+TARGET_ARCH=cskyv1
+TARGET_BASE_ARCH=csky
+TARGET_ABI_DIR=csky
+TARGET_HAS_BFLT=y
+TARGET_CSKYV1=y
+TARGET_XML_FILES= gdb-xml/csky-abiv1-linux-user-core.xml gdb-xml/csky-abiv1-softmmu-core.xml
+CONFIG_CSKY_KERNEL_4X=y
+CONFIG_CSKY_TRACE=y

configs/targets/cskyv1eb-softmmu.mak

@@ -0,0 +1,8 @@
+TARGET_ARCH=cskyv1
+TARGET_BASE_ARCH=csky
+TARGET_ABI_DIR=csky
+TARGET_HAS_BFLT=y
+TARGET_CSKYV1=y
+TARGET_XML_FILES= gdb-xml/csky-abiv1-linux-user-core.xml gdb-xml/csky-abiv1-softmmu-core.xml
+TARGET_NEED_FDT=y
+CONFIG_CSKY_TRACE=y

configs/targets/cskyv2-linux-user.mak

@@ -0,0 +1,9 @@
+TARGET_ARCH=cskyv2
+TARGET_BASE_ARCH=csky
+TARGET_ABI_DIR=csky
+TARGET_SUPPORTS_MTTCG=y
+TARGET_HAS_BFLT=y
+TARGET_CSKYV2=y
+TARGET_XML_FILES= gdb-xml/csky-abiv2-linux-user-core.xml gdb-xml/csky-abiv2-softmmu-core.xml gdb-xml/csky-fpu3.xml
+CONFIG_CSKY_KERNEL_4X=y
+CONFIG_CSKY_TRACE=y

configs/targets/cskyv2-softmmu.mak

@@ -0,0 +1,9 @@
+TARGET_ARCH=cskyv2
+TARGET_BASE_ARCH=csky
+TARGET_ABI_DIR=csky
+TARGET_SUPPORTS_MTTCG=y
+TARGET_HAS_BFLT=y
+TARGET_CSKYV2=y
+TARGET_XML_FILES= gdb-xml/csky-abiv2-linux-user-core.xml gdb-xml/csky-abiv2-softmmu-core.xml gdb-xml/csky-fpu3.xml
+TARGET_NEED_FDT=y
+CONFIG_CSKY_TRACE=y

configs/targets/cskyv2eb-linux-user.mak

@@ -0,0 +1,10 @@
+TARGET_ARCH=cskyv2
+TARGET_BASE_ARCH=csky
+TARGET_ABI_DIR=csky
+TARGET_SUPPORTS_MTTCG=y
+TARGET_HAS_BFLT=y
+TARGET_CSKYV2=y
+TARGET_XML_FILES= gdb-xml/csky-abiv2-linux-user-core.xml gdb-xml/csky-abiv2-softmmu-core.xml gdb-xml/csky-fpu3.xml
+TARGET_BIG_ENDIAN=y
+CONFIG_CSKY_KERNEL_4X=y
+CONFIG_CSKY_TRACE=y

configs/targets/cskyv2eb-softmmu.mak

@@ -0,0 +1,10 @@
+TARGET_ARCH=cskyv2
+TARGET_BASE_ARCH=csky
+TARGET_ABI_DIR=csky
+TARGET_SUPPORTS_MTTCG=y
+TARGET_HAS_BFLT=y
+TARGET_CSKYV2=y
+TARGET_XML_FILES= gdb-xml/csky-abiv2-linux-user-core.xml gdb-xml/csky-abiv2-softmmu-core.xml gdb-xml/csky-fpu3.xml
+TARGET_NEED_FDT=y
+TARGET_BIG_ENDIAN=y
+CONFIG_CSKY_TRACE=y

configs/targets/riscv32-linux-user.mak

@@ -4,3 +4,4 @@ TARGET_ABI_DIR=riscv
 TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-virtual.xml
 CONFIG_SEMIHOSTING=y
 CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
+CONFIG_CSKY_TRACE=y

configs/targets/riscv32-softmmu.mak

@@ -3,3 +3,4 @@ TARGET_BASE_ARCH=riscv
 TARGET_SUPPORTS_MTTCG=y
 TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-virtual.xml
 TARGET_NEED_FDT=y
+CONFIG_CSKY_TRACE=y

configs/targets/riscv64-linux-user.mak

@@ -4,3 +4,4 @@ TARGET_ABI_DIR=riscv
 TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml
 CONFIG_SEMIHOSTING=y
 CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
+CONFIG_CSKY_TRACE=y

configs/targets/riscv64-softmmu.mak

@@ -3,3 +3,4 @@ TARGET_BASE_ARCH=riscv
 TARGET_SUPPORTS_MTTCG=y
 TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml
 TARGET_NEED_FDT=y
+CONFIG_CSKY_TRACE=y

configure

@@ -252,6 +252,7 @@ python=
 download="enabled"
 skip_meson=no
 use_containers="yes"
+csky_dynsoc="no"
 gdb_bin=$(command -v "gdb-multiarch" || command -v "gdb")
 gdb_arches=""
 
@@ -758,6 +759,8 @@ for opt do
   ;;
   --gdb=*) gdb_bin="$optarg"
   ;;
+  --enable-dynsoc) csky_dynsoc="yes"
+  ;;
   # everything else has the same name in configure and meson
   --*) meson_option_parse "$opt" "$optarg"
   ;;
@@ -1597,6 +1600,10 @@ echo >> $config_host_mak
 
 echo all: >> $config_host_mak
 
+if test "$csky_dynsoc" = "yes" ; then
+  echo "CONFIG_DYNSOC=y" >> $config_host_mak
+fi
+
 echo "SRC_PATH=$source_path" >> $config_host_mak
 echo "TARGET_DIRS=$target_list" >> $config_host_mak
 echo "GDB=$gdb_bin" >> $config_host_mak

csky-trace.c

@@ -0,0 +1,613 @@
+/*
+ * CSKY trace
+ *
+ * Copyright (c) 2024 Alibaba Group. All rights reserved.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/tracestub.h"
+#include "exec/helper-proto.h"
+
+static uint32_t csky_trace_insn_seg;
+static uint32_t csky_trace_data_seg;
+#ifdef TARGET_RISCV
+bool csky_trace_elf_start;
+#endif
+inline bool gen_mem_trace(void)
+{
+    if (tfilter.enable) {
+#ifdef TARGET_RISCV
+        if (!csky_trace_elf_start) {
+            return false;
+        }
+#endif
+
+        if (tfilter.event & TRACE_EVENT_DATA) {
+            return true;
+        }
+    }
+    return false;
+}
+
+inline bool gen_tb_trace(void)
+{
+    if (tfilter.enable) {
+        if (tfilter.event & TRACE_EVENT_INSN) {
+            return true;
+        }
+    }
+    return false;
+}
+
+inline bool gen_x_vf_trace(void)
+{
+    if (tfilter.enable) {
+        if (tfilter.event & TRACE_EVENT_X_VF) {
+            return true;
+        }
+    }
+    return false;
+}
+
+inline bool gen_x_lmul_trace(void)
+{
+    if (tfilter.enable) {
+        if (tfilter.event & TRACE_EVENT_X_LMUL) {
+            return true;
+        }
+    }
+    return false;
+}
+
+static inline uint32_t csky_trace_get_addr_base(target_ulong addr)
+{
+    if (sizeof(target_ulong) == 8) {
+        return (uint64_t)addr >> 32;
+    }
+    return 0;
+}
+
+static inline uint32_t csky_trace_get_addr_offset(target_ulong addr)
+{
+    if (sizeof(target_ulong) == 8) {
+        return extract64(addr, 0, 32);
+    }
+    return addr;
+}
+
+
+static inline void csky_trace_send_base(uint32_t *base, uint8_t type,
+                                        target_ulong addr)
+{
+    int packlen = 0;
+    uint32_t addr_base;
+    packlen = 2 * sizeof(uint8_t) + sizeof(uint32_t);
+    addr_base = csky_trace_get_addr_base(addr);
+    if (addr_base != *base) {
+        *base = addr_base;
+        write_trace_8_8(type, packlen, sizeof(uint8_t), addr_base);
+    }
+    return;
+}
+
+static bool stsp_range_match(target_ulong pc, target_ulong smask)
+{
+    struct trace_range *tr = NULL;
+    int i;
+    if (tfilter.stsp_num == 0) {
+        if (smask == 0) {
+            return true;
+        } else {
+            return false;
+        }
+    }
+    for (i = 0; i < tfilter.stsp_num; i++) {
+        tr = &tfilter.stsp_range[i];
+        if (smask != 0) {
+            if ((tr->start & smask ) == pc) {
+                tr->start = pc;
+                return true;
+            } else if ((tr->end & smask) ==pc) {
+                tr->end = pc;
+                return true;
+            } else {
+                return false;
+            }
+        }
+        if (tfilter.sstsp == STSP_EXIT) {
+            if (tr->start == pc) {
+                tfilter.sstsp = STSP_START;
+                return true;
+            }
+            return false;
+        } else if (tfilter.sstsp == STSP_START) {
+            if (tr->end == pc) {
+                tfilter.sstsp = STSP_EXIT;
+                return false;
+            }
+            return true;
+        } else {
+            return false;
+        }
+    }
+    return false;
+}
+
+static bool addr_range_match(target_ulong pc, target_ulong smask)
+{
+    struct trace_range *tr = NULL;
+    int i;
+    if (tfilter.addr_num == 0) {
+        if (smask == 0) {
+            return true;
+        } else {
+            return false;
+        }
+    }
+    for (i = 0; i < tfilter.addr_num; i++) {
+        tr = &tfilter.addr_range[i];
+        if (smask != 0) {
+            if ((tr->start & smask ) == pc) {
+                tr->start = pc;
+                return true;
+            } else if ((tr->end & smask) == pc) {
+                tr->end = pc;
+                return true;
+            } else {
+                return false;
+            }
+        }
+        if ((tr->start <= pc) && (tr->end > pc)) {
+            return true;
+        }
+    }
+    return false;
+}
+
+static bool data_range_match(target_ulong pc, target_ulong value)
+{
+    if (tfilter.data_num == 0) {
+        return true;
+    }
+#ifdef TARGET_CSKY
+    for (int i = 0; i < tfilter.data_num; i++) {
+        struct trace_data *td = &tfilter.data_range[i];
+        struct trace_range *tr = &td->data_addr;
+        if ((tr->start <= pc) && (tr->end > pc)) {
+            if (td->mode == TRACE_VALUE_SINGLE) {
+                if (td->min == value) {
+                    return true;
+                }
+            } else if (td->mode == TRACE_VALUE_RANGE) {
+                if ((td->min <= value) && (td->max > value)) {
+                    return true;
+                }
+            }
+        }
+    }
+#endif
+    return false;
+}
+
+bool trace_range_test(void *cpu, uint32_t pc, uint32_t smask)
+{
+    bool result = false;
+    result = stsp_range_match(pc, smask);
+    result |= addr_range_match(pc, smask);
+    return result;
+}
+
+static int addr_trace_filter(CPUArchState *env, target_ulong pc)
+{
+    int result = 0;
+#ifdef TARGET_CSKY
+    if (tfilter.enable) {
+        if (tfilter.asid & TRACE_ASID_ENABLE_MASK) {
+            if (ENV_GET_MMU(env)) {
+                if (tfilter.asid != ENV_GET_ASID(env)) {
+                    return result;
+                }
+            }
+        }
+        if (stsp_range_match(pc, 0)) {
+            result |= STSP_RANGE_MATCH;
+            if (addr_range_match(pc, 0)) {
+                result |= ADDR_RANGE_MATCH;
+            }
+        }
+    }
+#elif TARGET_RISCV
+    if (tfilter.enable) {
+        if (stsp_range_match(pc, 0)) {
+            result |= STSP_RANGE_MATCH;
+        }
+        result |= ADDR_RANGE_MATCH;
+    }
+#endif
+    return result;
+}
+
+static int data_trace_filter(CPUArchState *env,
+    target_ulong pc, target_ulong addr, target_ulong value)
+{
+    int result = 0;
+    if (tfilter.enable) {
+#ifdef TARGET_CSKY
+        if (tfilter.asid & TRACE_ASID_ENABLE_MASK) {
+            if (ENV_GET_MMU(env)) {
+                if (tfilter.asid != ENV_GET_ASID(env)) {
+                    return result;
+                }
+            }
+        }
+#endif
+        if (stsp_range_match(pc, 0)) {
+            result |= STSP_RANGE_MATCH;
+            if (addr_range_match(addr, 0)) {
+                result |= ADDR_RANGE_MATCH;
+            }
+            if (data_range_match(addr, value)) {
+                    result |= DATA_RANGE_MATCH;
+            }
+        }
+    }
+    return result;
+}
+//#define CSKY_TRACE_DEBUG
+#ifdef CSKY_TRACE_DEBUG
+static int sync_trace_count;
+#endif
+void helper_csky_trace_icount(CPUArchState *env, target_ulong tb_pc, uint32_t icount)
+{
+    static long long total_csky_trace_icount;
+    static long long last_csky_trace_icount;
+    total_csky_trace_icount += icount;
+    if ((total_csky_trace_icount - last_csky_trace_icount) > INSN_PER_PACKET) {
+#ifdef CSKY_TRACE_DEBUG
+        if (sync_trace_count % 100 == 0) {
+            fprintf(stderr, ".");
+            fflush(stderr);
+        }
+        sync_trace_count++;
+#endif
+        trace_send();
+        last_csky_trace_icount = total_csky_trace_icount;
+    }
+    if (tfilter.enable) {
+        if (tfilter.event & TRACE_EVENT_INSN) {
+            int result = addr_trace_filter(env, tb_pc);
+            if (result & STSP_RANGE_MATCH) {
+                csky_trace_icount += icount;
+            }
+        }
+    }
+}
+
+void helper_trace_tb_start(CPUArchState *env, target_ulong tb_pc)
+{
+    static int8_t lastbase;
+    int8_t base = (tb_pc >> 24) & 0xff;
+    int32_t offset = tb_pc & 0xffffff;
+    int result = addr_trace_filter(env, tb_pc);
+#ifdef TARGET_RISCV
+    if (!csky_trace_elf_start) {
+        if (tb_pc == env->elf_start) {
+            csky_trace_elf_start = true;
+        }
+    }
+    if (!csky_trace_elf_start) {
+        return;
+    }
+#endif
+    if (result & STSP_RANGE_MATCH) {
+        csky_trace_send_base(&csky_trace_insn_seg, INST_SEG, tb_pc);
+        env->last_pc = tb_pc;
+        if (base != lastbase) {
+            write_trace_8(INST_BASE, 2 * sizeof(uint8_t), base);
+            lastbase = base;
+        }
+        write_trace_8(INST_OFFSET, sizeof(uint32_t), offset);
+        if (result & ADDR_RANGE_MATCH) {
+            //write_trace_8(ADDR_CMPR_MATCH, sizeof(uint32_t), offset);
+        }
+    }
+}
+
+void helper_trace_tb_exit(uint32_t subtype, uint32_t offset)
+{
+#ifdef TARGET_RISCV
+    if (!csky_trace_elf_start) {
+        return;
+    }
+#endif
+    write_trace_8_8(INST_EXIT, sizeof(uint32_t), subtype, offset);
+    if (is_gdbserver_start) {
+        trace_send_immediately();
+    }
+}
+
+void extern_helper_trace_tb_exit(uint32_t subtype, uint32_t offset)
+{
+    helper_trace_tb_exit(subtype, offset);
+}
+
+static void helper_trace_ldst(CPUArchState *env, target_ulong pc,
+    target_ulong rz, target_ulong addr, int type)
+{
+    int packlen = 0;
+    int result = data_trace_filter(env, pc, addr, rz);
+
+    packlen = 2 * sizeof(uint8_t) + sizeof(uint32_t);
+    if (result & STSP_RANGE_MATCH) {
+        if (tfilter.proxy) {
+            write_trace_8(DATA_INST_OFFSET, sizeof(uint32_t), pc - env->last_pc);
+        }
+        csky_trace_send_base(&csky_trace_data_seg, DATA_SEG, addr);
+        addr = csky_trace_get_addr_offset(addr);
+        switch (type) {
+        case LD8U: case LD8S:
+            write_trace_8_8(DATA_RADDR, packlen, sizeof(uint8_t), addr);
+            write_trace_8_8(DATA_VALUE, packlen, 0, (uint32_t)rz);
+            raddr_num++;
+            break;
+        case LD16U: case LD16S:
+            write_trace_8_8(DATA_RADDR, packlen, sizeof(uint16_t), addr);
+            write_trace_8_8(DATA_VALUE, packlen, 0, (uint32_t)rz);
+            raddr_num++;
+            break;
+        case LD32U: case LD32S:
+            write_trace_8_8(DATA_RADDR, packlen, sizeof(uint32_t), addr);
+            write_trace_8_8(DATA_VALUE, packlen, 0, (uint32_t)rz);
+            raddr_num++;
+            break;
+        case LD64U: case LD64S:
+            write_trace_8_8(DATA_RADDR, packlen, sizeof(uint64_t), addr);
+            //write_trace_8_seq(DATA_VALUE, sizeof(uint64_t) + 1, (uint8_t *)&rz);
+            write_trace_8_8(DATA_VALUE, packlen, 0, extract64(rz, 0, 32));
+            write_trace_8_8(DATA_VALUE, packlen, 32, extract64(rz, 32, 32));
+            raddr_num++;
+            break;
+        case ST8:
+            write_trace_8_8(DATA_WADDR, packlen, sizeof(uint8_t), addr);
+            write_trace_8_8(DATA_VALUE, packlen, 0, (uint32_t)rz);
+            waddr_num++;
+            break;
+        case ST16:
+            write_trace_8_8(DATA_WADDR, packlen, sizeof(uint16_t), addr);
+            write_trace_8_8(DATA_VALUE, packlen, 0, (uint32_t)rz);
+            waddr_num++;
+            break;
+        case ST32:
+            write_trace_8_8(DATA_WADDR, packlen, sizeof(uint32_t), addr);
+            write_trace_8_8(DATA_VALUE, packlen, 0, (uint32_t)rz);
+            waddr_num++;
+            break;
+        case ST64:
+            write_trace_8_8(DATA_WADDR, packlen, sizeof(uint64_t), addr);
+            //write_trace_8_seq(DATA_VALUE, sizeof(uint64_t) + 1, (uint8_t*)&rz);
+            write_trace_8_8(DATA_VALUE, packlen, 0, extract64(rz, 0, 32));
+            write_trace_8_8(DATA_VALUE, packlen, 32, extract64(rz, 32, 32));
+            waddr_num++;
+            break;
+        default:
+            break;
+        }
+        if (result & ADDR_RANGE_MATCH) {
+        }
+        if (result & DATA_RANGE_MATCH) {
+        }
+    }
+}
+
+void helper_trace_ld8u(CPUArchState *env, target_ulong pc,
+                       target_ulong rz, target_ulong addr)
+{
+    helper_trace_ldst(env, pc, rz, addr, LD8U);
+}
+
+void helper_trace_ld16u(CPUArchState *env, target_ulong pc,
+                        target_ulong rz, target_ulong addr)
+{
+    helper_trace_ldst(env, pc, rz, addr, LD16U);
+}
+
+void helper_trace_ld32u(CPUArchState *env, target_ulong pc,
+                        target_ulong rz, target_ulong addr)
+{
+    helper_trace_ldst(env, pc, rz, addr, LD32U);
+}
+
+void helper_trace_ld64u(CPUArchState *env, target_ulong pc,
+                        target_ulong rz, target_ulong addr)
+{
+    helper_trace_ldst(env, pc, rz, addr, LD64U);
+}
+
+void helper_trace_ld8s(CPUArchState *env, target_ulong pc,
+                       target_ulong rz, target_ulong addr)
+{
+    helper_trace_ldst(env, pc, rz, addr, LD8S);
+}
+
+void helper_trace_ld16s(CPUArchState *env, target_ulong pc,
+                        target_ulong rz, target_ulong addr)
+{
+    helper_trace_ldst(env, pc, rz, addr, LD16S);
+}
+
+void helper_trace_ld32s(CPUArchState *env, target_ulong pc,
+                        target_ulong rz, target_ulong addr)
+{
+    helper_trace_ldst(env, pc, rz, addr, LD32S);
+}
+
+void helper_trace_ld64s(CPUArchState *env, target_ulong pc,
+                        target_ulong rz, target_ulong addr)
+{
+    helper_trace_ldst(env, pc, rz, addr, LD64S);
+}
+
+void helper_trace_st8(CPUArchState *env, target_ulong pc,
+                      target_ulong rz, target_ulong addr)
+{
+    helper_trace_ldst(env, pc, rz, addr, ST8);
+}
+
+void helper_trace_st16(CPUArchState *env, target_ulong pc,
+                       target_ulong rz, target_ulong addr)
+{
+    helper_trace_ldst(env, pc, rz, addr, ST16);
+}
+
+void helper_trace_st32(CPUArchState *env, target_ulong pc,
+                       target_ulong rz, target_ulong addr)
+{
+    helper_trace_ldst(env, pc, rz, addr, ST32);
+}
+
+void helper_trace_st64(CPUArchState *env, target_ulong pc,
+                       target_ulong rz, target_ulong addr)
+{
+    helper_trace_ldst(env, pc, rz, addr, ST64);
+}
+
+void helper_trace_m_addr(CPUArchState *env, target_ulong pc,
+                         target_ulong addr, target_ulong num, uint32_t type)
+{
+    int packlen = 0;
+    int result = addr_trace_filter(env, pc);
+
+    packlen = 2 * sizeof(uint8_t) + sizeof(uint32_t);
+    if (result & STSP_RANGE_MATCH) {
+        csky_trace_send_base(&csky_trace_data_seg, DATA_SEG, addr);
+        addr = csky_trace_get_addr_offset(addr);
+        write_trace_8_8(type, packlen, num * sizeof(uint32_t), addr);
+        if (type == 0x41) {
+            waddr_num++;
+        } else if (type == 0x40) {
+            raddr_num++;
+        }
+        if (result & ADDR_RANGE_MATCH) {
+        }
+    }
+}
+
+void helper_trace_m_value(CPUArchState *env, target_ulong pc,
+                          target_ulong addr, target_ulong value)
+{
+    int packlen = 0;
+    int result = data_trace_filter(env, pc, addr, value);
+
+    packlen = 2 * sizeof(uint8_t) + sizeof(uint32_t);
+    if (result & STSP_RANGE_MATCH) {
+        //write_trace_8_seq(DATA_VALUE, packlen, &value);
+        if (sizeof(target_ulong) == 64) {
+            write_trace_8_8(DATA_VALUE, packlen, 0, extract64(value, 0, 32));
+            write_trace_8_8(DATA_VALUE, packlen, 0, extract64(value, 32, 32));
+        } else {
+            write_trace_8_8(DATA_VALUE, packlen, 0, value);
+        }
+        if (result & ADDR_RANGE_MATCH) {
+        }
+        if (result & DATA_RANGE_MATCH) {
+        }
+    }
+}
+
+void helper_trace_update_tcr(CPUArchState *env)
+{
+    int mode = -1;
+    int enable = 0;
+    uint32_t *addr_index = &tfilter.addr_num;
+    uint32_t *data_index = &tfilter.data_num;
+    uint32_t *stsp_index = &tfilter.stsp_num;
+    int value_index, value_mode, i;
+    CPUState *cpu = env_cpu(env);
+
+    /* TRCEn enable */
+    if ((env->cp13.tcr & 0x01) && (cpu->csky_trace_features & CSKY_TRACE)) {
+
+        tfilter.enable = true;
+        tfilter.event = env->cp13.ter; /* get all trace event */
+        /* first send trace header */
+        write_trace_header(env->cp13.ter);
+
+        if (!(cpu->csky_trace_features & MEM_TRACE)) {
+            tfilter.event &= ~(0x02);
+        }
+        if (!(cpu->csky_trace_features & TB_TRACE)) {
+            tfilter.event &= ~(0x01);
+        }
+        tfilter.asid = env->cp13.asid;
+
+        /* fill all range */
+        for (i = 0; i < MAX_ADDR_CMPR_NUM - 1; i++) {
+            mode = (env->cp13.addr_cmpr_config[i] & ADDR_CMPR_MODE_MASK)
+                    >> ADDR_CMPR_MODE_START;
+            enable = env->cp13.addr_cmpr_config[i] & ADDR_CMPR_ENABLE_MASK;
+            if (enable) {
+                switch (mode) {
+                case INSN_ADDR_RANGE_CMPR:
+                case DATA_ADDR_RANGE_CMPR: /* addr range match */
+                    tfilter.addr_range[*addr_index].start
+                                    = env->cp13.addr_cmpr[i];
+                    tfilter.addr_range[*addr_index].end
+                                    = env->cp13.addr_cmpr[++i];
+                    (*addr_index)++;
+                    break;
+                case ASSOCIATE_VALUE_CMPR: /* associate value match */
+                    value_index = env->cp13.addr_cmpr_config[i]
+                                & ADDR_CMPR_DATA_MASK;
+                    value_mode = env->cp13.data_cmpr_config[value_index]
+                                & DATA_CMPR_MODE_MASK;
+                    if (TRACE_VALUE_SINGLE == value_mode) {
+                        tfilter.data_range[*data_index].mode
+                                = value_mode;
+                        tfilter.data_range[*data_index].min
+                                = env->cp13.data_cmpr[value_index];
+                    } else if (TRACE_VALUE_RANGE == value_mode) {
+                        tfilter.data_range[*data_index].mode
+                                = value_mode;
+                        tfilter.data_range[*data_index].min
+                                = env->cp13.data_cmpr[value_index];
+                        tfilter.data_range[*data_index].max
+                                = env->cp13.data_cmpr[value_index + 1];
+                    } else {
+                        return;
+                    }
+                    tfilter.data_range[*data_index].data_addr.start
+                            =  env->cp13.addr_cmpr[i];
+                    tfilter.data_range[*data_index].data_addr.end
+                            =  env->cp13.addr_cmpr[++i];
+                    (*data_index)++;
+                    break;
+                case STSP_RANGE_CMPR: /* stsp range match */
+                    tfilter.stsp_range[*stsp_index].start
+                            = env->cp13.addr_cmpr[i];
+                    tfilter.stsp_range[*stsp_index].end
+                            = env->cp13.addr_cmpr[++i];
+                    (*stsp_index)++;
+                    break;
+                default:
+                    break;
+                }
+            }
+        }
+    } else {
+        memset(&tfilter, 0, sizeof(tfilter));
+    }
+}
+

cskysim/.gitignore

@@ -0,0 +1 @@
+compile_gen.h

cskysim/Makefile

@@ -0,0 +1,37 @@
+ifeq ($(DEBUG),y)
+	CFLAGS += -g -O0
+endif
+
+ifeq ($(GCOV),y)
+	CFLAGS += -fprofile-arcs -ftest-coverage -g -O0
+	LIBS   += -fprofile-arcs -ftest-coverage -lgcov
+endif
+
+SYS := $(shell $(CC) -dumpmachine)
+
+ifneq (, $(findstring mingw, $(SYS)))
+XML_LIBS=$(shell mingw32-pkg-config --libs libxml-2.0)
+XML_CFLAGS=$(shell mingw32-pkg-config --cflags libxml-2.0)
+else
+XML_CFLAGS=$(shell xml2-config --cflags)
+XML_LIBS=$(shell xml2-config --libs)
+endif
+
+COMPILE_DATE=`date +%Y%m%d`
+
+all: compile_date
+	$(CC) cskysim.c $(XML_CFLAGS) $(XML_LIBS) $(CFLAGS) -o cskysim -g $(LIBS)
+
+compile_date:
+	@echo "#define COMPILE_DATE "$(COMPILE_DATE) > compile_gen.h
+
+.PHONY: win32
+win32: compile_date
+	$(CC) cskysim.c $(XML_CFLAGS) $(XML_LIBS) -o cskysim_w32.exe -g
+
+.PHONY: win64
+win64: compile_date
+	$(CC) cskysim.c $(XML_CFLAGS) $(XML_LIBS) -o cskysim_w64.exe -g
+
+clean:
+	rm cskysim compile_gen.h

cskysim/soccfg/cskyv1/smarth_610_cfg.xml

@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="smarth" arch="csky" cskysimv="2.0">
+    <cpu_info cpu="ck610ef" endian="little" abi="abiv1"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_intc" filename="builtin" addr="0x10010000" type="INTC" extra="" irq="31"></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x10015000" type="UART" extra="" irq="0"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x10011000" type="TIMER" extra="" irq="2"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq="30"></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x01000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: ck610ef Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x1000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/cskyv1/smarth_610m_cfg.xml

@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="smarth" arch="csky" cskysimv="2.0">
+    <cpu_info cpu="ck610ef" endian="little" abi="abiv1"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_intc" filename="builtin" addr="0x10010000" type="INTC" extra="" irq="31"></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x10015000" type="UART" extra="" irq="0"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x10011000" type="TIMER" extra="" irq="2"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq="30"></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x01000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mmu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: ck610ef Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x1000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/cskyv1/trilobite_610e_cfg.xml

@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="trilobite" arch="csky" cskysimv="2.0">
+    <cpu_info cpu="ck610e" endian="little" abi="abiv1"></cpu_info>
+    <dyndev shm="off">
+        <dev name="csky_intc" filename="csky_intc" addr="0x10010000" type="INTC" extra="" irq="0"></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x10015000" type="UART" extra="" irq="16"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x10011000" type="TIMER" extra="" irq="12"></dev>
+        <dev name="csky_mac"  filename="csky_mac" addr="0x10006000" type="MAC" extra="" irq="26"></dev>
+        <dev name="csky_lcdc"  filename="csky_lcdc" addr="0x10004000" type="LCDC" extra="" irq="28"></dev>
+    </dyndev>
+    <memory>
+        <mem name="trilobite_v2.sdram" addr="0x8000000" size ="0x8000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: ck610e Little Endian
+            Memory Sections:
+                trilobite_v2.sdram, Start: 0x08000000, Length: 0x08000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/cskyv1eb/trilobite_610e_cfg.xml

@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="trilobite" arch="csky" cskysimv="2.0">
+    <cpu_info cpu="ck610e" endian="big" abi="abiv1"></cpu_info>
+    <dyndev shm="off">
+        <dev name="csky_intc" filename="csky_intc" addr="0x10010000" type="INTC" extra="" irq="0"></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x10015000" type="UART" extra="" irq="16"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x10011000" type="TIMER" extra="" irq="12"></dev>
+        <dev name="csky_mac"  filename="csky_mac" addr="0x10006000" type="MAC" extra="" irq="26"></dev>
+        <dev name="csky_lcdc"  filename="csky_lcdc" addr="0x10004000" type="LCDC" extra="" irq="28"></dev>
+    </dyndev>
+    <memory>
+        <mem name="trilobite_v2.sdram" addr="0x8000000" size ="0x8000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: ck610e Big Endian
+            Memory Sections:
+                trilobite_v2.sdram, Start: 0x08000000, Length: 0x08000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/cskyv2/rhea_803.xml

@@ -0,0 +1,34 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="rhea" arch="csky" cskysimv="2.0">
+    <cpu_info cpu="ck803efr1" endian="little" abi="abiv2"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_intc" filename="csky_intc" addr="0x40018000" type="INTC" extra="" irq="0"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x40017000" type="TIMER" extra="" irq="15"></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x40016000" type="UART" extra="" irq="14"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq="30"></dev>
+    </dyndev>
+    <memory>
+        <mem name="rhea_onchip_rom" addr="0x0" size ="0x800" attr="MEM_ROM"></mem>
+        <mem name="rhea_nvm_simulator" addr="0x8000" size ="0x8000" attr="MEM_RAM"></mem>
+        <mem name="rhea_external_sram1" addr="0x20000000" size =" 0x800000" attr ="MEM_RAM"></mem>
+        <mem name="rhea_external_sram2" addr="0x20800000" size ="0x800000" attr="MEM_RAM"></mem>
+        <mem name="rhea_onchip_sram" addr="0x28000000" size ="0x10000" attr="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: ck803efr1 Little Endian
+            Memory Sections:
+               rhea_onchip_rom, Start: 0x0, Length: 0x800
+               rhea_nvm_simulator, Start: 0x8000, Length: 0x8000
+               rhea_external_sram1, Start: 0x20000000, Length: 0x800000
+               rhea_external_sram2, Start: 0x20800000, Length: 0x800000
+               rhea_onchip_sram, Start: 0x28000000, Length: 0x10000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/cskyv2/smart_card_802_cfg.xml

@@ -0,0 +1,32 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="smart_card" arch="csky" cskysimv="2.0">
+    <cpu_info cpu="ck802" endian="little" abi="abiv2"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_tcip_v1" filename="builtin" addr="0xe000e100" type="INTC" extra="" irq="31"></dev>
+        <dev name="csky_coret" filename="builtin" addr="0xe000e000" type="TIMER" extra="" irq="0"></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0xf15000" type="UART" extra="" irq="2"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq="30"></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_card.rom" addr="0x0" size ="0x20000" attr ="MEM_RAM"></mem>
+        <mem name="smart_sys_mem2" addr="0x00400000" size ="0x200000" attr ="MEM_RAM"></mem>
+        <mem name="smart_card.eeprom" addr="0x00600000" size ="0x10000" attr ="MEM_RAM"></mem>
+        <mem name="smart_card.flash" addr="0xF0000000" size ="0xff00000" attr ="MEM_ROM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: ck802 Little Endian
+            Memory Sections:
+                smart_card.rom, Start: 0x0, Length: 0x20000
+                smart_sys_mem2, Start: 0x00400000, Length: 0x200000
+                smart_card.eeprom, Start: 0x00600000, Length: 0x10000
+                smart_card.flash, Start: 0xF0000000, Length: 0xff00000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/cskyv2/smarth_807_cfg.xml

@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="smarth" arch="csky" cskysimv="2.0">
+    <cpu_info cpu="ck807f" endian="little" abi="abiv2"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_intc" filename="builtin" addr="0x10010000" type="INTC" extra="" irq="31"></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x10015000" type="UART" extra="" irq="0"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x10011000" type="TIMER" extra="" irq="2"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq="30"></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x01000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mmu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: ck807fv Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x1000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/cskyv2/smarth_810_cfg.xml

@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="smarth" arch="csky" cskysimv="2.0">
+    <cpu_info cpu="ck810fv" endian="little" abi="abiv2"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_intc" filename="builtin" addr="0x10010000" type="INTC" extra="" irq="31"></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x10015000" type="UART" extra="" irq="0"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x10011000" type="TIMER" extra="" irq="2"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq="30"></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x01000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mmu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: ck810fv Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x1000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/cskyv2/smarth_860_cfg.xml

@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="smarth" arch="csky" cskysimv="2.0">
+    <cpu_info cpu="ck860fv" endian="little" abi="abiv2"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_intc" filename="builtin" addr="0x10010000" type="INTC" extra="" irq="31"></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x10015000" type="UART" extra="" irq="0"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x10011000" type="TIMER" extra="" irq="2"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq="30"></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x01000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mmu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: ck860fv Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x1000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/cskyv2/smartl_801_cfg.xml

@@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="smartl" arch="csky" cskysimv="2.0">
+    <cpu_info cpu="ck801" endian="little" abi="abiv2"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_tcip_v1" filename="builtin" addr="0xe000e100" type="INTC" extra="" irq="31"></dev>
+        <dev name="csky_coret" filename="builtin" addr="0xe000e000" type="TIMER" extra="" irq="1"></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x40015000" type="UART" extra="" irq="0"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x40011000" type="TIMER" extra="" irq="2"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq="30"></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_data_mem" addr="0x20000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_outchip_mem" addr="0x50000000" size ="0x00800000" attr ="MEM_RAM"></mem>
+        <mem name="smart_sys_mem" addr="0x60000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="on"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: ck801 Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x1000000
+                smart_data_mem, Start: 0x20000000, Length: 0x40000
+                smart_outchip_mem, Start: 0x50000000, Length: 0x800000
+                smart_sys_mem, Start: 0x60000000, Length: 0x1000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/cskyv2/smartl_802_cfg.xml

@@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="smartl" arch="csky" cskysimv="2.0">
+    <cpu_info cpu="ck802" endian="little" abi="abiv2"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_tcip_v1" filename="builtin" addr="0xe000e100" type="INTC" extra="" irq="31"></dev>
+        <dev name="csky_coret" filename="builtin" addr="0xe000e000" type="TIMER" extra="" irq="1"></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x40015000" type="UART" extra="" irq="0"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x40011000" type="TIMER" extra="" irq="2"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq="30"></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_data_mem" addr="0x20000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_outchip_mem" addr="0x50000000" size ="0x00800000" attr ="MEM_RAM"></mem>
+        <mem name="smart_sys_mem" addr="0x60000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="on"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: ck802 Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x1000000
+                smart_data_mem, Start: 0x20000000, Length: 0x40000
+                smart_outchip_mem, Start: 0x50000000, Length: 0x800000
+                smart_sys_mem, Start: 0x60000000, Length: 0x1000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/cskyv2/smartl_803_cfg.xml

@@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="smartl" arch="csky" cskysimv="2.0">
+    <cpu_info cpu="ck803efr3" endian="little" abi="abiv2"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_tcip_v1" filename="builtin" addr="0xe000e100" type="INTC" extra="" irq="31"></dev>
+        <dev name="csky_coret" filename="builtin" addr="0xe000e000" type="TIMER" extra="" irq="1"></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x40015000" type="UART" extra="" irq="0"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x40011000" type="TIMER" extra="" irq="2"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq="30"></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_data_mem" addr="0x20000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_outchip_mem" addr="0x50000000" size ="0x00800000" attr ="MEM_RAM"></mem>
+        <mem name="smart_sys_mem" addr="0x60000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="on"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: ck803efr3 Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x1000000
+                smart_data_mem, Start: 0x20000000, Length: 0x40000
+                smart_outchip_mem, Start: 0x50000000, Length: 0x800000
+                smart_sys_mem, Start: 0x60000000, Length: 0x1000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/cskyv2/smartl_804_cfg.xml

@@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="smartl" arch="csky" cskysimv="2.0">
+    <cpu_info cpu="ck804ef" endian="little" abi="abiv2"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_tcip_v1" filename="builtin" addr="0xe000e100" type="INTC" extra="" irq="31"></dev>
+        <dev name="csky_coret" filename="builtin" addr="0xe000e000" type="TIMER" extra="" irq="1"></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x40015000" type="UART" extra="" irq="0"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x40011000" type="TIMER" extra="" irq="2"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq="30"></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_data_mem" addr="0x20000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_outchip_mem" addr="0x50000000" size ="0x00800000" attr ="MEM_RAM"></mem>
+        <mem name="smart_sys_mem" addr="0x60000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="on"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: ck804ef Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x1000000
+                smart_data_mem, Start: 0x20000000, Length: 0x40000
+                smart_outchip_mem, Start: 0x50000000, Length: 0x800000
+                smart_sys_mem, Start: 0x60000000, Length: 0x1000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/cskyv2/smartl_805_cfg.xml

@@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="smartl" arch="csky" cskysimv="2.0">
+    <cpu_info cpu="ck805ef" endian="little" abi="abiv2"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_tcip_v1" filename="builtin" addr="0xe000e100" type="INTC" extra="" irq="31"></dev>
+        <dev name="csky_coret" filename="builtin" addr="0xe000e000" type="TIMER" extra="" irq="1"></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x40015000" type="UART" extra="" irq="0"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x40011000" type="TIMER" extra="" irq="2"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq="30"></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_data_mem" addr="0x20000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_outchip_mem" addr="0x50000000" size ="0x00800000" attr ="MEM_RAM"></mem>
+        <mem name="smart_sys_mem" addr="0x60000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="on"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: ck805ef Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x1000000
+                smart_data_mem, Start: 0x20000000, Length: 0x40000
+                smart_outchip_mem, Start: 0x50000000, Length: 0x800000
+                smart_sys_mem, Start: 0x60000000, Length: 0x1000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/cskyv2eb/rhea_803.xml

@@ -0,0 +1,34 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="rhea" arch="csky" cskysimv="2.0">
+    <cpu_info cpu="ck803efr1" endian="big" abi="abiv2"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_intc" filename="csky_intc" addr="0x40018000" type="INTC" extra="" irq="0"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x40017000" type="TIMER" extra="" irq="15"></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x40016000" type="UART" extra="" irq="14"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq="30"></dev>
+    </dyndev>
+    <memory>
+        <mem name="rhea_onchip_rom" addr="0x0" size ="0x800" attr="MEM_ROM"></mem>
+        <mem name="rhea_nvm_simulator" addr="0x8000" size ="0x8000" attr="MEM_RAM"></mem>
+        <mem name="rhea_external_sram1" addr="0x20000000" size =" 0x800000" attr ="MEM_RAM"></mem>
+        <mem name="rhea_external_sram2" addr="0x20800000" size ="0x800000" attr="MEM_RAM"></mem>
+        <mem name="rhea_onchip_sram" addr="0x28000000" size ="0x10000" attr="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: ck803efr1 Big Endian
+            Memory Sections:
+               rhea_onchip_rom, Start: 0x0, Length: 0x800
+               rhea_nvm_simulator, Start: 0x8000, Length: 0x8000
+               rhea_external_sram1, Start: 0x20000000, Length: 0x800000
+               rhea_external_sram2, Start: 0x20800000, Length: 0x800000
+               rhea_onchip_sram, Start: 0x28000000, Length: 0x10000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/cskyv2eb/smart_card_802_cfg.xml

@@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="smart_card" arch="csky" cskysimv="2.0">
+    <cpu_info cpu="ck802" endian="big" abi="abiv2"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_tcip_v1" filename="builtin" addr="0xe000e100" type="INTC" extra="" irq="31"></dev>
+        <dev name="csky_coret" filename="builtin" addr="0xe000e000" type="TIMER" extra="" irq="0"></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0xf15000" type="UART" extra="" irq="2"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq="30"></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_card.rom" addr="0x0" size ="0x20000" attr ="MEM_RAM"></mem>
+        <mem name="smart_sys_mem2" addr="0x00400000" size ="0x200000" attr ="MEM_RAM"></mem>
+        <mem name="smart_card.eeprom" addr="0x00600000" size ="0x10000" attr ="MEM_RAM"></mem>
+        <mem name="smart_card.flash" addr="0xF0000000" size ="0xff00000" attr ="MEM_ROM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: ck802 Big Endian
+            Memory Sections:
+                smart_card.rom, Start: 0x0, Length: 0x20000
+                smart_sys_mem2, Start: 0x00400000, Length: 0x200000
+                smart_card.eeprom, Start: 0x00600000, Length: 0x10000
+                smart_card.flash, Start: 0xF0000000, Length: 0xff00000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/cskyv2eb/smartl_803_cfg.xml

@@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="smartl" arch="csky" cskysimv="2.0">
+    <cpu_info cpu="ck803" endian="big" abi="abiv2"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_tcip_v1" filename="builtin" addr="0xe000e100" type="INTC" extra="" irq="31"></dev>
+        <dev name="csky_coret" filename="builtin" addr="0xe000e000" type="TIMER" extra="" irq="1"></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x40015000" type="UART" extra="" irq="0"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq="30"></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_data_mem" addr="0x20000000" size ="0x00040000" attr ="MEM_RAM"></mem>
+        <mem name="smart_outchip_mem" addr="0x50000000" size ="0x00800000" attr ="MEM_RAM"></mem>
+        <mem name="smart_sys_mem" addr="0x60000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: ck803 Big Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x1000000
+                smart_data_mem, Start: 0x20000000, Length: 0x10000
+                smart_outchip_mem, Start: 0x50000000, Length: 0x800000
+                smart_sys_mem, Start: 0x60000000, Length: 0x1000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv32/sifive_e.xml

@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="sifive_e" arch="riscv32" cskysimv="2.0">
+    <cpu_info cpu="any" endian="little" abi="riscv32"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_clic" filename="builtin" addr="0xe000e100" type="INTC" extra="" irq="63"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10036000" type="EXIT" extra="" irq="62"></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_data_mem" addr="0x20000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_outchip_mem" addr="0x40000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_sys_mem" addr="0x80000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: sifive-e31 Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x1000000
+                smart_data_mem, Start: 0x20000000, Length: 0x1000000
+                smart_outchip_mem, Start: 0x40000000, Length: 0x1000000
+                smart_sys_mem, Start: 0x80000000, Length: 0x1000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv32/sifive_ex.xml

@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="sifive_ex" arch="riscv32" cskysimv="2.0">
+    <cpu_info cpu="any" endian="little" abi="riscv32"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_clic" filename="builtin" addr="0xe000e100" type="INTC" extra="" irq="63"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10036000" type="EXIT" extra="" irq="62"></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_data_mem" addr="0x20000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_outchip_mem" addr="0x40000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_sys_mem" addr="0x80000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: sifive-e31 Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x1000000
+                smart_data_mem, Start: 0x20000000, Length: 0x1000000
+                smart_outchip_mem, Start: 0x40000000, Length: 0x1000000
+                smart_sys_mem, Start: 0x80000000, Length: 0x1000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv32/smartl_e902_cfg.xml

@@ -0,0 +1,35 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="smartl" arch="riscv32" cskysimv="2.0">
+    <cpu_info cpu="e902m" endian="little" abi="riscv32"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_clic" filename="builtin" addr="0xe0800000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_clint" filename="builtin" addr="0xe0000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x40015000" type="UART" extra="" irq="16"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x40011000" type="TIMER" extra="" irq="18"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq=""></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_data_mem" addr="0x20000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_outchip_mem" addr="0x50000000" size ="0x00800000" attr ="MEM_RAM"></mem>
+        <mem name="smart_sys_mem" addr="0x60000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_systemmap" addr="0xEFFFF000" size ="0x00000040" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: e902m Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x1000000
+                smart_data_mem, Start: 0x20000000, Length: 0x40000
+                smart_outchip_mem, Start: 0x50000000, Length: 0x800000
+                smart_sys_mem, Start: 0x60000000, Length: 0x1000000
+                smart_sysmemmap, Start: 0xEFFFF000, Length: 0x0000040
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv32/smartl_e906_cfg.xml

@@ -0,0 +1,35 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="smartl" arch="riscv32" cskysimv="2.0">
+    <cpu_info cpu="e906fdp" endian="little" abi="riscv32"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_clic" filename="builtin" addr="0xe0800000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_clint" filename="builtin" addr="0xe0000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x40015000" type="UART" extra="" irq="16"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x40011000" type="TIMER" extra="" irq="18"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq=""></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_data_mem" addr="0x20000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_outchip_mem" addr="0x50000000" size ="0x00800000" attr ="MEM_RAM"></mem>
+        <mem name="smart_sys_mem" addr="0x60000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_systemmap" addr="0xEFFFF000" size ="0x00000040" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: e906fdp Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x1000000
+                smart_data_mem, Start: 0x20000000, Length: 0x40000
+                smart_outchip_mem, Start: 0x50000000, Length: 0x800000
+                smart_sys_mem, Start: 0x60000000, Length: 0x1000000
+                smart_sysmemmap, Start: 0xEFFFF000, Length: 0x0000040
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv32/smartl_e907_cfg.xml

@@ -0,0 +1,35 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="smartl" arch="riscv32" cskysimv="2.0">
+    <cpu_info cpu="e907fdp" endian="little" abi="riscv32"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_clic" filename="builtin" addr="0xe0800000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_clint" filename="builtin" addr="0xe0000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x40015000" type="UART" extra="" irq="16"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x40011000" type="TIMER" extra="" irq="18"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq=""></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_data_mem" addr="0x20000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_outchip_mem" addr="0x50000000" size ="0x00800000" attr ="MEM_RAM"></mem>
+        <mem name="smart_sys_mem" addr="0x60000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_systemmap" addr="0xEFFFF000" size ="0x00000040" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: e907fdp Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x1000000
+                smart_data_mem, Start: 0x20000000, Length: 0x40000
+                smart_outchip_mem, Start: 0x50000000, Length: 0x800000
+                smart_sys_mem, Start: 0x60000000, Length: 0x1000000
+                smart_sysmemmap, Start: 0xEFFFF000, Length: 0x0000040
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv32/xiaohui_c907_cfg.xml

@@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="xiaohui" arch="riscv32" cskysimv="2.0">
+    <cpu_info cpu="c907fdvm-rv32" endian="little" abi="riscv32"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_plic" filename="builtin" addr="0x8000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_clint" filename="builtin" addr="0xc000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x1900d000" type="UART" extra="" irq="20"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x19001000" type="TIMER" extra="" irq="25"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x4c000000" type="EXIT" extra="" irq=""></dev>
+    </dyndev>
+    <memory>
+        <mem name="xiaohui_sram" addr="0x0" size ="0x00100000" attr ="MEM_RAM"></mem>
+        <mem name="xiaohui_dram" addr="0x50000000" size ="0x40000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: c907fdvm-rv32 Little Endian
+            Memory Sections:
+                xiaohui_sram, Start: 0x0, Length: 0x100000
+                xiaohui_dram, Start: 0x50000000, Length: 0x40000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv64/sifive_e.xml

@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="sifive_e" arch="riscv64" cskysimv="2.0">
+    <cpu_info cpu="any" endian="little" abi="riscv64"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_clic" filename="builtin" addr="0xe000e100" type="INTC" extra="" irq="63"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10036000" type="EXIT" extra="" irq="62"></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_data_mem" addr="0x20000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_outchip_mem" addr="0x40000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_sys_mem" addr="0x80000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: sifive-e51 Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x1000000
+                smart_data_mem, Start: 0x20000000, Length: 0x1000000
+                smart_outchip_mem, Start: 0x40000000, Length: 0x1000000
+                smart_sys_mem, Start: 0x80000000, Length: 0x1000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv64/sifive_ex.xml

@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="sifive_ex" arch="riscv64" cskysimv="2.0">
+    <cpu_info cpu="any" endian="little" abi="riscv64"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_clic" filename="builtin" addr="0xe000e100" type="INTC" extra="" irq="63"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10036000" type="EXIT" extra="" irq="62"></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_data_mem" addr="0x20000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_outchip_mem" addr="0x40000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_sys_mem" addr="0x80000000" size ="0x01000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: sifive-e51 Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x1000000
+                smart_data_mem, Start: 0x20000000, Length: 0x1000000
+                smart_outchip_mem, Start: 0x40000000, Length: 0x1000000
+                smart_sys_mem, Start: 0x80000000, Length: 0x1000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv64/smarth_c906_cfg.xml

@@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="smarth" arch="riscv64" cskysimv="2.0">
+    <cpu_info cpu="c906fdv" endian="little" abi="riscv64"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_plic" filename="builtin" addr="0x4000000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_clint" filename="builtin" addr="0x4004000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x10015000" type="UART" extra="" irq="32"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x10011000" type="TIMER" extra="" irq="34"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq=""></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x02000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_sys_mem" addr="0x1F000000" size ="0x02000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: c906fdv Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x2000000
+                smart_outchip_mem, Start: 0x1f000000, Length: 0x2000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv64/smarth_c907_cfg.xml

@@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="smarth" arch="riscv64" cskysimv="2.0">
+    <cpu_info cpu="c907fdvm" endian="little" abi="riscv64"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_plic" filename="builtin" addr="0x4000000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_clint" filename="builtin" addr="0x4004000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x10015000" type="UART" extra="" irq="32"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x10011000" type="TIMER" extra="" irq="34"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq=""></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x02000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_sys_mem" addr="0x1F000000" size ="0x02000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: c907fdvm Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x2000000
+                smart_outchip_mem, Start: 0x1f000000, Length: 0x2000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv64/smarth_c908_cfg.xml

@@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="smarth" arch="riscv64" cskysimv="2.0">
+    <cpu_info cpu="c908v" endian="little" abi="riscv64"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_plic" filename="builtin" addr="0x4000000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_clint" filename="builtin" addr="0x4004000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x10015000" type="UART" extra="" irq="32"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x10011000" type="TIMER" extra="" irq="34"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq=""></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x02000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_sys_mem" addr="0x1F000000" size ="0x02000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: c908v Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x2000000
+                smart_outchip_mem, Start: 0x1f000000, Length: 0x2000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv64/smarth_c910_cfg.xml

@@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="smarth" arch="riscv64" cskysimv="2.0">
+    <cpu_info cpu="c910v" endian="little" abi="riscv64"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_plic" filename="builtin" addr="0x4000000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_clint" filename="builtin" addr="0x4004000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x10015000" type="UART" extra="" irq="32"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x10011000" type="TIMER" extra="" irq="34"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq=""></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x02000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_sys_mem" addr="0x1F000000" size ="0x02000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: c910 Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x2000000
+                smart_outchip_mem, Start: 0x1f000000, Length: 0x2000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv64/smarth_c910v2_cfg.xml

@@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="smarth" arch="riscv64" cskysimv="2.0">
+    <cpu_info cpu="c910v2" endian="little" abi="riscv64"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_plic" filename="builtin" addr="0x4000000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_clint" filename="builtin" addr="0x4004000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x10015000" type="UART" extra="" irq="32"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x10011000" type="TIMER" extra="" irq="34"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq=""></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x02000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_sys_mem" addr="0x1F000000" size ="0x02000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: c910v2 Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x02000000
+                smart_outchip_mem, Start: 0x1f000000, Length: 0x02000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv64/smarth_c920_cfg.xml

@@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="smarth" arch="riscv64" cskysimv="2.0">
+    <cpu_info cpu="c920" endian="little" abi="riscv64"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_plic" filename="builtin" addr="0x4000000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_clint" filename="builtin" addr="0x4004000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x10015000" type="UART" extra="" irq="32"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x10011000" type="TIMER" extra="" irq="34"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq=""></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x02000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_sys_mem" addr="0x1F000000" size ="0x02000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: c920 Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x2000000
+                smart_outchip_mem, Start: 0x1f000000, Length: 0x2000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv64/smarth_c920v2_cfg.xml

@@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="smarth" arch="riscv64" cskysimv="2.0">
+    <cpu_info cpu="c920v2" endian="little" abi="riscv64"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_plic" filename="builtin" addr="0x4000000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_clint" filename="builtin" addr="0x4004000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x10015000" type="UART" extra="" irq="32"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x10011000" type="TIMER" extra="" irq="34"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq=""></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x02000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_sys_mem" addr="0x1F000000" size ="0x02000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: c920v2 Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x2000000
+                smart_outchip_mem, Start: 0x1f000000, Length: 0x2000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv64/smarth_r910_cfg.xml

@@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="smarth" arch="riscv64" cskysimv="2.0">
+    <cpu_info cpu="r910" endian="little" abi="riscv64"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_plic" filename="builtin" addr="0x4000000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_clint" filename="builtin" addr="0x4004000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x10015000" type="UART" extra="" irq="32"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x10011000" type="TIMER" extra="" irq="34"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq=""></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x02000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_sys_mem" addr="0x1F000000" size ="0x02000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: r910 Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x2000000
+                smart_outchip_mem, Start: 0x1f000000, Length: 0x2000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv64/smarth_r920_cfg.xml

@@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="smarth" arch="riscv64" cskysimv="2.0">
+    <cpu_info cpu="r920" endian="little" abi="riscv64"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_plic" filename="builtin" addr="0x4000000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_clint" filename="builtin" addr="0x4004000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x10015000" type="UART" extra="" irq="32"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x10011000" type="TIMER" extra="" irq="34"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x10002000" type="EXIT" extra="" irq=""></dev>
+    </dyndev>
+    <memory>
+        <mem name="smart_inst_mem" addr="0x0" size ="0x02000000" attr ="MEM_RAM"></mem>
+        <mem name="smart_sys_mem" addr="0x1F000000" size ="0x02000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: r920 Little Endian
+            Memory Sections:
+                smart_inst_mem, Start: 0x0, Length: 0x2000000
+                smart_outchip_mem, Start: 0x1f000000, Length: 0x2000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv64/xiaohui_c906_cfg.xml

@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="xiaohui" arch="riscv64" cskysimv="2.0">
+    <cpu_info cpu="c906fdv" endian="little" abi="riscv64"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_clic"  filename="builtin" addr="0xc010000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_plic" filename="builtin" addr="0x8000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_clint" filename="builtin" addr="0xc000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x1900d000" type="UART" extra="" irq="20"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x19001000" type="TIMER" extra="" irq="25"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x4c000000" type="EXIT" extra="" irq=""></dev>
+    </dyndev>
+    <memory>
+        <mem name="xiaohui_sram" addr="0x0" size ="0x00100000" attr ="MEM_RAM"></mem>
+        <mem name="xiaohui_dram" addr="0x50000000" size ="0x40000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: c906fdv Little Endian
+            Memory Sections:
+                xiaohui_sram, Start: 0x0, Length: 0x100000
+                xiaohui_dram, Start: 0x50000000, Length: 0x40000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv64/xiaohui_c907_cfg.xml

@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="xiaohui" arch="riscv64" cskysimv="2.0">
+    <cpu_info cpu="c907fdvm" endian="little" abi="riscv64"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_clic"  filename="builtin" addr="0xc010000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_plic" filename="builtin" addr="0x8000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_clint" filename="builtin" addr="0xc000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x1900d000" type="UART" extra="" irq="20"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x19001000" type="TIMER" extra="" irq="25"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x4c000000" type="EXIT" extra="" irq=""></dev>
+    </dyndev>
+    <memory>
+        <mem name="xiaohui_sram" addr="0x0" size ="0x00100000" attr ="MEM_RAM"></mem>
+        <mem name="xiaohui_dram" addr="0x50000000" size ="0x40000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: c907fdvm Little Endian
+            Memory Sections:
+                xiaohui_sram, Start: 0x0, Length: 0x100000
+                xiaohui_dram, Start: 0x50000000, Length: 0x40000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv64/xiaohui_c908_cfg.xml

@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="xiaohui" arch="riscv64" cskysimv="2.0">
+    <cpu_info cpu="c908v" endian="little" abi="riscv64"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_clic"  filename="builtin" addr="0xc010000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_plic" filename="builtin" addr="0x8000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_clint" filename="builtin" addr="0xc000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x1900d000" type="UART" extra="" irq="20"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x19001000" type="TIMER" extra="" irq="25"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x4c000000" type="EXIT" extra="" irq=""></dev>
+    </dyndev>
+    <memory>
+        <mem name="xiaohui_sram" addr="0x0" size ="0x00100000" attr ="MEM_RAM"></mem>
+        <mem name="xiaohui_dram" addr="0x50000000" size ="0x40000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: c908v Little Endian
+            Memory Sections:
+                xiaohui_sram, Start: 0x0, Length: 0x100000
+                xiaohui_dram, Start: 0x50000000, Length: 0x40000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv64/xiaohui_c910_cfg.xml

@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="xiaohui" arch="riscv64" cskysimv="2.0">
+    <cpu_info cpu="c910" endian="little" abi="riscv64"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_clic"  filename="builtin" addr="0xc010000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_plic" filename="builtin" addr="0x8000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_clint" filename="builtin" addr="0xc000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x1900d000" type="UART" extra="" irq="20"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x19001000" type="TIMER" extra="" irq="25"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x4c000000" type="EXIT" extra="" irq=""></dev>
+    </dyndev>
+    <memory>
+        <mem name="xiaohui_sram" addr="0x0" size ="0x00100000" attr ="MEM_RAM"></mem>
+        <mem name="xiaohui_dram" addr="0x50000000" size ="0x40000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: c910 Little Endian
+            Memory Sections:
+                xiaohui_sram, Start: 0x0, Length: 0x100000
+                xiaohui_dram, Start: 0x50000000, Length: 0x40000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv64/xiaohui_c910v2_cfg.xml

@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="xiaohui" arch="riscv64" cskysimv="2.0">
+    <cpu_info cpu="c910v2" endian="little" abi="riscv64"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_clic"  filename="builtin" addr="0xc010000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_plic" filename="builtin" addr="0x8000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_clint" filename="builtin" addr="0xc000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x1900d000" type="UART" extra="" irq="20"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x19001000" type="TIMER" extra="" irq="25"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x4c000000" type="EXIT" extra="" irq=""></dev>
+    </dyndev>
+    <memory>
+        <mem name="xiaohui_sram" addr="0x0" size ="0x00100000" attr ="MEM_RAM"></mem>
+        <mem name="xiaohui_dram" addr="0x50000000" size ="0x40000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: c910v2 Little Endian
+            Memory Sections:
+                xiaohui_sram, Start: 0x0, Length: 0x100000
+                xiaohui_dram, Start: 0x50000000, Length: 0x40000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv64/xiaohui_c910v3_cfg.xml

@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="xiaohui" arch="riscv64" cskysimv="2.0">
+    <cpu_info cpu="c910v3" endian="little" abi="riscv64"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_clic"  filename="builtin" addr="0xc010000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_plic" filename="builtin" addr="0x8000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_clint" filename="builtin" addr="0xc000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x1900d000" type="UART" extra="" irq="20"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x19001000" type="TIMER" extra="" irq="25"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x4c000000" type="EXIT" extra="" irq=""></dev>
+    </dyndev>
+    <memory>
+        <mem name="xiaohui_sram" addr="0x0" size ="0x00100000" attr ="MEM_RAM"></mem>
+        <mem name="xiaohui_dram" addr="0x50000000" size ="0x40000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: c910v3 Little Endian
+            Memory Sections:
+                xiaohui_sram, Start: 0x0, Length: 0x100000
+                xiaohui_dram, Start: 0x50000000, Length: 0x40000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv64/xiaohui_c920_cfg.xml

@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="xiaohui" arch="riscv64" cskysimv="2.0">
+    <cpu_info cpu="c920" endian="little" abi="riscv64"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_clic"  filename="builtin" addr="0xc010000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_plic" filename="builtin" addr="0x8000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_clint" filename="builtin" addr="0xc000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x1900d000" type="UART" extra="" irq="20"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x19001000" type="TIMER" extra="" irq="25"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x4c000000" type="EXIT" extra="" irq=""></dev>
+    </dyndev>
+    <memory>
+        <mem name="xiaohui_sram" addr="0x0" size ="0x00100000" attr ="MEM_RAM"></mem>
+        <mem name="xiaohui_dram" addr="0x50000000" size ="0x40000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: c920 Little Endian
+            Memory Sections:
+                xiaohui_sram, Start: 0x0, Length: 0x100000
+                xiaohui_dram, Start: 0x50000000, Length: 0x40000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv64/xiaohui_c920v2_cfg.xml

@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="xiaohui" arch="riscv64" cskysimv="2.0">
+    <cpu_info cpu="c920v2" endian="little" abi="riscv64"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_clic"  filename="builtin" addr="0xc010000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_plic" filename="builtin" addr="0x8000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_clint" filename="builtin" addr="0xc000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x1900d000" type="UART" extra="" irq="20"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x19001000" type="TIMER" extra="" irq="25"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x4c000000" type="EXIT" extra="" irq=""></dev>
+    </dyndev>
+    <memory>
+        <mem name="xiaohui_sram" addr="0x0" size ="0x00100000" attr ="MEM_RAM"></mem>
+        <mem name="xiaohui_dram" addr="0x50000000" size ="0x40000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: c920v2 Little Endian
+            Memory Sections:
+                xiaohui_sram, Start: 0x0, Length: 0x100000
+                xiaohui_dram, Start: 0x50000000, Length: 0x40000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv64/xiaohui_c920v3_cfg.xml

@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="xiaohui" arch="riscv64" cskysimv="2.0">
+    <cpu_info cpu="c920v3" endian="little" abi="riscv64"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_clic"  filename="builtin" addr="0xc010000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_plic" filename="builtin" addr="0x8000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_clint" filename="builtin" addr="0xc000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x1900d000" type="UART" extra="" irq="20"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x19001000" type="TIMER" extra="" irq="25"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x4c000000" type="EXIT" extra="" irq=""></dev>
+    </dyndev>
+    <memory>
+        <mem name="xiaohui_sram" addr="0x0" size ="0x00100000" attr ="MEM_RAM"></mem>
+        <mem name="xiaohui_dram" addr="0x50000000" size ="0x40000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: c920v3 Little Endian
+            Memory Sections:
+                xiaohui_sram, Start: 0x0, Length: 0x100000
+                xiaohui_dram, Start: 0x50000000, Length: 0x40000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv64/xiaohui_r908_cfg.xml

@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="xiaohui" arch="riscv64" cskysimv="2.0">
+    <cpu_info cpu="r908fdv" endian="little" abi="riscv64"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_clic"  filename="builtin" addr="0xc010000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_plic" filename="builtin" addr="0x8000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_clint" filename="builtin" addr="0xc000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x1900d000" type="UART" extra="" irq="20"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x19001000" type="TIMER" extra="" irq="25"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x4c000000" type="EXIT" extra="" irq=""></dev>
+    </dyndev>
+    <memory>
+        <mem name="xiaohui_sram" addr="0x0" size ="0x00100000" attr ="MEM_RAM"></mem>
+        <mem name="xiaohui_dram" addr="0x50000000" size ="0x40000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: r908fdv Little Endian
+            Memory Sections:
+                xiaohui_sram, Start: 0x0, Length: 0x100000
+                xiaohui_dram, Start: 0x50000000, Length: 0x40000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv64/xiaohui_r910_cfg.xml

@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="xiaohui" arch="riscv64" cskysimv="2.0">
+    <cpu_info cpu="r910" endian="little" abi="riscv64"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_clic"  filename="builtin" addr="0xc010000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_plic" filename="builtin" addr="0x8000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_clint" filename="builtin" addr="0xc000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x1900d000" type="UART" extra="" irq="20"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x19001000" type="TIMER" extra="" irq="25"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x4c000000" type="EXIT" extra="" irq=""></dev>
+    </dyndev>
+    <memory>
+        <mem name="xiaohui_sram" addr="0x0" size ="0x00100000" attr ="MEM_RAM"></mem>
+        <mem name="xiaohui_dram" addr="0x50000000" size ="0x40000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: r910 Little Endian
+            Memory Sections:
+                xiaohui_sram, Start: 0x0, Length: 0x100000
+                xiaohui_dram, Start: 0x50000000, Length: 0x40000000
+        </AutoDescription>
+    </Description>
+</Board>

cskysim/soccfg/riscv64/xiaohui_r920_cfg.xml

@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Board name="xiaohui" arch="riscv64" cskysimv="2.0">
+    <cpu_info cpu="r920" endian="little" abi="riscv64"></cpu_info>
+    <dyndev shm="on">
+        <dev name="csky_clic"  filename="builtin" addr="0xc010000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_plic" filename="builtin" addr="0x8000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_clint" filename="builtin" addr="0xc000000" type="INTC" extra="" irq=""></dev>
+        <dev name="csky_uart" filename="csky_uart" addr="0x1900d000" type="UART" extra="" irq="20"></dev>
+        <dev name="csky_timer" filename="csky_timer" addr="0x19001000" type="TIMER" extra="" irq="25"></dev>
+        <dev name="csky_exit"  filename="csky_exit" addr="0x4c000000" type="EXIT" extra="" irq=""></dev>
+    </dyndev>
+    <memory>
+        <mem name="xiaohui_sram" addr="0x0" size ="0x00100000" attr ="MEM_RAM"></mem>
+        <mem name="xiaohui_dram" addr="0x50000000" size ="0x40000000" attr ="MEM_RAM"></mem>
+    </memory>
+    <cpu_prop>
+        <cpu name="pctrace"                 value="off"> on/off </cpu>
+        <cpu name="elrw"                    value="off"> on/off </cpu>
+        <cpu name="mem_prot"                value="mpu"> no/mmu/mpu </cpu>
+        <cpu name="unaligned_access"        value="off"> on/off </cpu>
+    </cpu_prop>
+    <Description> This file is used for dynamic configuration
+        <AutoDescription>
+            CPU Type: r920 Little Endian
+            Memory Sections:
+                xiaohui_sram, Start: 0x0, Length: 0x100000
+                xiaohui_dram, Start: 0x50000000, Length: 0x40000000
+        </AutoDescription>
+    </Description>
+</Board>

disas/meson.build

@@ -14,6 +14,7 @@ common_ss.add(when: 'CONFIG_RISCV_DIS', if_true: files(
 common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c'))
 common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('sparc.c'))
 common_ss.add(when: 'CONFIG_XTENSA_DIS', if_true: files('xtensa.c'))
+common_ss.add(when: 'CONFIG_CSKY_DIS', if_true: files('csky.c'))
 common_ss.add(when: capstone, if_true: [files('capstone.c'), capstone])
 common_ss.add(files('disas.c'))
 

disas/riscv.c

@@ -906,6 +906,74 @@ typedef enum {
     rv_op_amocas_w = 875,
     rv_op_amocas_d = 876,
     rv_op_amocas_q = 877,
+    rv_mop_r_0     = 878,
+    rv_mop_r_1     = 879,
+    rv_mop_r_2     = 880,
+    rv_mop_r_3     = 881,
+    rv_mop_r_4     = 882,
+    rv_mop_r_5     = 883,
+    rv_mop_r_6     = 884,
+    rv_mop_r_7     = 885,
+    rv_mop_r_8     = 886,
+    rv_mop_r_9     = 887,
+    rv_mop_r_10    = 888,
+    rv_mop_r_11    = 889,
+    rv_mop_r_12    = 890,
+    rv_mop_r_13    = 891,
+    rv_mop_r_14    = 892,
+    rv_mop_r_15    = 893,
+    rv_mop_r_16    = 894,
+    rv_mop_r_17    = 895,
+    rv_mop_r_18    = 896,
+    rv_mop_r_19    = 897,
+    rv_mop_r_20    = 898,
+    rv_mop_r_21    = 899,
+    rv_mop_r_22    = 900,
+    rv_mop_r_23    = 901,
+    rv_mop_r_24    = 902,
+    rv_mop_r_25    = 903,
+    rv_mop_r_26    = 904,
+    rv_mop_r_27    = 905,
+    rv_mop_r_28    = 906,
+    rv_mop_r_29    = 907,
+    rv_mop_r_30    = 908,
+    rv_mop_r_31    = 909,
+    rv_mop_rr_0    = 910,
+    rv_mop_rr_1    = 911,
+    rv_mop_rr_2    = 912,
+    rv_mop_rr_3    = 913,
+    rv_mop_rr_4    = 914,
+    rv_mop_rr_5    = 915,
+    rv_mop_rr_6    = 916,
+    rv_mop_rr_7    = 917,
+    rv_c_mop_1     = 918,
+    rv_c_mop_3     = 919,
+    rv_c_mop_5     = 920,
+    rv_c_mop_7     = 921,
+    rv_c_mop_9     = 922,
+    rv_c_mop_11    = 923,
+    rv_c_mop_13    = 924,
+    rv_c_mop_15    = 925,
+    rv_op_amoswap_b = 926,
+    rv_op_amoadd_b  = 927,
+    rv_op_amoxor_b  = 928,
+    rv_op_amoor_b   = 929,
+    rv_op_amoand_b  = 930,
+    rv_op_amomin_b  = 931,
+    rv_op_amomax_b  = 932,
+    rv_op_amominu_b = 933,
+    rv_op_amomaxu_b = 934,
+    rv_op_amoswap_h = 935,
+    rv_op_amoadd_h  = 936,
+    rv_op_amoxor_h  = 937,
+    rv_op_amoor_h   = 938,
+    rv_op_amoand_h  = 939,
+    rv_op_amomin_h  = 940,
+    rv_op_amomax_h  = 941,
+    rv_op_amominu_h = 942,
+    rv_op_amomaxu_h = 943,
+    rv_op_amocas_b  = 944,
+    rv_op_amocas_h  = 945,
 } rv_op;
 
 /* register names */
@@ -2096,6 +2164,74 @@ const rv_opcode_data rvi_opcode_data[] = {
     { "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
     { "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
     { "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+    { "mop.r.0", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.1", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.2", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.3", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.4", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.5", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.6", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.7", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.8", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.9", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.10", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.11", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.12", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.13", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.14", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.15", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.16", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.17", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.18", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.19", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.20", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.21", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.22", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.23", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.24", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.25", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.26", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.27", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.28", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.29", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.30", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.r.31", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0 },
+    { "mop.rr.0", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "mop.rr.1", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "mop.rr.2", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "mop.rr.3", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "mop.rr.4", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "mop.rr.5", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "mop.rr.6", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "mop.rr.7", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
+    { "c.mop.1",  rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
+    { "c.mop.3",  rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
+    { "c.mop.5",  rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
+    { "c.mop.7",  rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
+    { "c.mop.9",  rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
+    { "c.mop.11", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
+    { "c.mop.13", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
+    { "c.mop.15", rv_codec_ci_none, rv_fmt_none, NULL, 0, 0, 0 },
+    { "amoswap.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+    { "amoadd.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+    { "amoxor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+    { "amoor.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+    { "amoand.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+    { "amomin.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+    { "amomax.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+    { "amominu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+    { "amomaxu.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+    { "amoswap.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+    { "amoadd.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+    { "amoxor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+    { "amoor.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+    { "amoand.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+    { "amomin.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+    { "amomax.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+    { "amominu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+    { "amomaxu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+    { "amocas.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+    { "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
 };
 
 /* CSR names */
@@ -2389,6 +2525,13 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
             break;
         case 2: op = rv_op_c_li; break;
         case 3:
+            if (dec->cfg->ext_zcmop) {
+                if ((((inst >> 2) & 0b111111) == 0b100000) &&
+                    (((inst >> 11) & 0b11) == 0b0)) {
+                    op = rv_c_mop_1 + ((inst >> 8) & 0b111);
+                    break;
+                }
+            }
             switch ((inst >> 7) & 0b11111) {
             case 2: op = rv_op_c_addi16sp; break;
             default: op = rv_op_c_lui; break;
@@ -2820,9 +2963,13 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
         case 11:
             switch (((inst >> 24) & 0b11111000) |
                     ((inst >> 12) & 0b00000111)) {
+            case 0: op = rv_op_amoadd_b; break;
+            case 1: op = rv_op_amoadd_h; break;
             case 2: op = rv_op_amoadd_w; break;
             case 3: op = rv_op_amoadd_d; break;
             case 4: op = rv_op_amoadd_q; break;
+            case 8: op = rv_op_amoswap_b; break;
+            case 9: op = rv_op_amoswap_h; break;
             case 10: op = rv_op_amoswap_w; break;
             case 11: op = rv_op_amoswap_d; break;
             case 12: op = rv_op_amoswap_q; break;
@@ -2844,27 +2991,43 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
             case 26: op = rv_op_sc_w; break;
             case 27: op = rv_op_sc_d; break;
             case 28: op = rv_op_sc_q; break;
+            case 32: op = rv_op_amoxor_b; break;
+            case 33: op = rv_op_amoxor_h; break;
             case 34: op = rv_op_amoxor_w; break;
             case 35: op = rv_op_amoxor_d; break;
             case 36: op = rv_op_amoxor_q; break;
+            case 40: op = rv_op_amocas_b; break;
+            case 41: op = rv_op_amocas_h; break;
             case 42: op = rv_op_amocas_w; break;
             case 43: op = rv_op_amocas_d; break;
             case 44: op = rv_op_amocas_q; break;
+            case 64: op = rv_op_amoor_b; break;
+            case 65: op = rv_op_amoor_h; break;
             case 66: op = rv_op_amoor_w; break;
             case 67: op = rv_op_amoor_d; break;
             case 68: op = rv_op_amoor_q; break;
+            case 96: op = rv_op_amoand_b; break;
+            case 97: op = rv_op_amoand_h; break;
             case 98: op = rv_op_amoand_w; break;
             case 99: op = rv_op_amoand_d; break;
             case 100: op = rv_op_amoand_q; break;
+            case 128: op = rv_op_amomin_b; break;
+            case 129: op = rv_op_amomin_h; break;
             case 130: op = rv_op_amomin_w; break;
             case 131: op = rv_op_amomin_d; break;
             case 132: op = rv_op_amomin_q; break;
+            case 160: op = rv_op_amomax_b; break;
+            case 161: op = rv_op_amomax_h; break;
             case 162: op = rv_op_amomax_w; break;
             case 163: op = rv_op_amomax_d; break;
             case 164: op = rv_op_amomax_q; break;
+            case 192: op = rv_op_amominu_b; break;
+            case 193: op = rv_op_amominu_h; break;
             case 194: op = rv_op_amominu_w; break;
             case 195: op = rv_op_amominu_d; break;
             case 196: op = rv_op_amominu_q; break;
+            case 224: op = rv_op_amomaxu_b; break;
+            case 225: op = rv_op_amomaxu_h; break;
             case 226: op = rv_op_amomaxu_w; break;
             case 227: op = rv_op_amomaxu_d; break;
             case 228: op = rv_op_amomaxu_q; break;
@@ -3792,6 +3955,24 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
             case 1: op = rv_op_csrrw; break;
             case 2: op = rv_op_csrrs; break;
             case 3: op = rv_op_csrrc; break;
+            case 4:
+                if (dec->cfg->ext_zimop) {
+                    int imm_mop5, imm_mop3;
+                    if ((extract32(inst, 22, 10) & 0b1011001111)
+                        == 0b1000000111) {
+                        imm_mop5 = deposit32(deposit32(extract32(inst, 20, 2),
+                                                       2, 2,
+                                                       extract32(inst, 26, 2)),
+                                             4, 1, extract32(inst, 30, 1));
+                        op = rv_mop_r_0 + imm_mop5;
+                    } else if ((extract32(inst, 25, 7) & 0b1011001)
+                               == 0b1000001) {
+                        imm_mop3 = deposit32(extract32(inst, 26, 2),
+                                             2, 1, extract32(inst, 30, 1));
+                        op = rv_mop_rr_0 + imm_mop3;
+                    }
+                }
+                break;
             case 5: op = rv_op_csrrwi; break;
             case 6: op = rv_op_csrrsi; break;
             case 7: op = rv_op_csrrci; break;

docs/conf.py

@@ -121,7 +121,7 @@ language = 'en'
 # List of patterns, relative to source directory, that match files and
 # directories to ignore when looking for source files.
 # This patterns also effect to html_static_path and html_extra_path
-exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store']
+exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store', 'csky']
 
 # The name of the Pygments (syntax highlighting) style to use.
 pygments_style = 'sphinx'

docs/csky/Makefile

@@ -0,0 +1,19 @@
+# Minimal makefile for Sphinx documentation
+#
+
+# You can set these variables from the command line.
+SPHINXOPTS    =
+SPHINXBUILD   = sphinx-build
+SOURCEDIR     = .
+BUILDDIR      = _build
+
+# Put it first so that "make" without argument is like "make help".
+help:
+	@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+
+.PHONY: help Makefile
+
+# Catch-all target: route all unknown targets to Sphinx using the new
+# "make mode" option.  $(O) is meant as a shortcut for $(SPHINXOPTS).
+%: Makefile
+	@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)

docs/csky/build.rst

@@ -0,0 +1,41 @@
+==========================
+编译
+==========================
+
+------------
+推荐环境
+------------
+
+推荐使用以下操作系统版本：
+
+* ubuntu 20.04 64位
+* windows 10 64位
+
+---------------------
+获取可执行程序
+---------------------
+
+玄铁 QEMU 可执行程序有以下几种获取方式：
+
+1. CDS安装后，以windows默认安装为例，可以在D:\\C-Sky\\CDS\\qemu下找到。
+2. CDK安装后，以windows默认安装为例，可以在D:\\C-Sky\\CDK\\qemu下找到。
+3. 从https://www.xrvm.cn/芯片开放社区获取。
+
+---------------------
+获取源代码
+---------------------
+
+源代码在玄铁github站点维护：
+https://github.com/XUANTIE-RV/qemu
+
+---------------------
+编译方法
+---------------------
+
+.. code-block:: none
+
+    git clone git@github.com:XUANTIE-RV/qemu.git
+    mkdir build
+    cd build
+    ../configure --target-list="riscv64-softmmu riscv32-softmmu riscv64-linux-user riscv32-linux-user cskyv2-softmmu cskyv1-softmmu cskyv1-linux-user cskyv2-linux-user"
+    make -j8

docs/csky/conf.py

@@ -0,0 +1,156 @@
+
+# -*- coding: utf-8 -*-
+#
+# Configuration file for the Sphinx documentation builder.
+#
+
+# -- Project information
+
+import sys
+reload(sys)
+
+project = u'玄铁QEMU用户手册'
+author = u''
+version = u''
+release = u'V5.0'
+copyright = 'copyright'
+
+# -- General configuration
+
+extensions = [
+]
+templates_path = ['_templates']
+source_suffix = '.rst'
+master_doc = 'index'
+language = u'zh_CN'
+exclude_patterns = []
+pygments_style = 'sphinx'
+numfig = True
+
+# -- Options for HTML output
+
+html_theme = 'alabaster'
+html_static_path = ['_static']
+
+# -- Options for HTMLHelp output
+
+htmlhelp_basename = u'玄铁QEMU用户手册doc'
+
+# -- Options for LaTeX output
+
+
+latex_engine = 'xelatex'
+
+latex_elements = {
+
+    'preamble': r'''
+\usepackage[UTF8, heading = true]{ctex}
+\usepackage{ctex}
+\setlength{\parindent}{2em}
+\usepackage{enumitem}
+\setlist[itemize,1]{leftmargin=1.2cm}
+\setlist[itemize,2]{leftmargin=1.8cm}
+\setlist[enumerate,1]{leftmargin=1.2cm}
+\setlist[enumerate,2]{leftmargin=1.8cm}
+\hypersetup{bookmarksnumbered = true}
+\setcounter{secnumdepth}{3}
+\usepackage{graphicx}
+\usepackage{setspace}
+\usepackage{subfigure}
+\usepackage{float}
+\usepackage{multirow}
+\usepackage{fancyhdr}
+\makeatletter
+    \fancypagestyle{normal}{
+        \fancyfoot[C]{\thepage}
+        \fancyfoot[L]{\fontsize{7}{7} \selectfont \ www.xrvm.cn}
+        \fancyfoot[R]{\fontsize{7}{7} \selectfont  \textcopyright\ 【杭州中天微系统有限公司】版权所有}
+        \fancyhead[R]{\includegraphics[scale=0.45] {xuantielogo.png}}
+        \fancyhead[L]{\py@HeaderFamily \nouppercase{\leftmark}}
+     }
+\makeatother
+    ''',
+    'classoptions': ',oneside',
+    'maketitle': ur'''
+\maketitle
+
+
+\begin{spacing}{1.1}
+
+\noindent \small \textbf{Copyright © 2023 Hangzhou C-SKY MicroSystems Co., Ltd. All rights reserved.}
+
+\noindent This document is the property of Hangzhou C-SKY MicroSystems Co., Ltd. and its affiliates ("C-SKY"). This document may only be distributed to: (i) a C-SKY party having a legitimate business need for the information contained herein, or (ii) a non-C-SKY party having a legitimate business need for the information contained herein. No license, expressed or implied, under any patent, copyright or trade secret right is granted or implied by the conveyance of this document. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual, or otherwise without the prior written permission of Hangzhou C-SKY MicroSystems Co., Ltd.
+
+\noindent \small \textbf{Trademarks and Permissions}
+
+\noindent The C-SKY Logo and all other trademarks indicated as such herein (including XuanTie) are trademarks of Hangzhou C-SKY MicroSystems Co., Ltd. All other products or service names are the property of their respective owners.
+
+\noindent \small \textbf{Notice}
+
+\noindent The purchased products, services and features are stipulated by the contract made between C-SKY and the customer. All or part of the products, services and features described in this document may not be within the purchase scope or the usage scope. Unless otherwise specified in the contract, all statements, information, and recommendations in this document are provided "AS IS" without warranties, guarantees or representations of any kind, either express or implied.
+
+\noindent The information in this document is subject to change without notice. Every effort has been made in the preparation of this document to ensure accuracy of the contents, but all statements, information, and recommendations in this document do not constitute a warranty of any kind, express or implied.
+
+\noindent \small \textbf{杭州中天微系统有限公司 Hangzhou C-SKY MicroSystems Co., LTD}
+
+\noindent Address: Room 201, 2/F, Building 5, No.699 Wangshang Road , Hangzhou, Zhejiang, China
+
+\noindent Website: www.xrvm.cn
+
+\noindent \small \textbf{Copyright © 2023杭州中天微系统有限公司，保留所有权利.}
+
+\noindent 本文档的所有权及知识产权归属于杭州中天微系统有限公司及其关联公司(下称“中天微”)。本文档仅能分派给：(i)拥有合法雇佣关系，并需要本文档的信息的中天微员工，或(ii)非中天微组织但拥有合法合作关系，并且其需要本文档的信息的合作方。对于本文档，未经杭州中天微系统有限公司明示同意，则不能使用该文档。在未经中天微的书面许可的情形下，不得复制本文档的任何部分，传播、转录、储存在检索系统中或翻译成任何语言或计算机语言。
+
+\noindent \small \textbf{商标申明}
+
+\noindent 中天微的LOGO和其它所有商标（如XuanTie玄铁）归杭州中天微系统有限公司及其关联公司所有，未经杭州中天微系统有限公司的书面同意，任何法律实体不得使用中天微的商标或者商业标识。
+
+\noindent \small \textbf{注意}
+
+\noindent 您购买的产品、服务或特性等应受中天微商业合同和条款的约束，本文档中描述的全部或部分产品、服务或特性可能不在您的购买或使用范围之内。除非合同另有约定，中天微对本文档内容不做任何明示或默示的声明或保证。
+
+\noindent 由于产品版本升级或其他原因，本文档内容会不定期进行更新。除非另有约定，本文档仅作为使用指导，本文档中的所有陈述、信息和建议不构成任何明示或暗示的担保。杭州中天微系统有限公司不对任何第三方使用本文档产生的损失承担任何法律责任。
+
+\noindent \small \textbf{杭州中天微系统有限公司 Hangzhou C-SKY MicroSystems Co., LTD}
+
+\noindent 地址：中国浙江省杭州市网商路699号5号楼2楼201室
+
+\noindent 网址：www.xrvm.cn
+
+\end{spacing}
+
+\newpage
+
+\textbf{\huge 版本历史}\\
+
+\begin{center}
+
+\begin{tabular}{p{40pt}<{}p{300pt}<{}p{100pt}<{}}
+\hline
+
+\textbf{版本}       & \textbf{描述}               & \textbf{日期}                 \\ \hline
+01                  & 第一次正式发布。              & 2021.07.31                  \\ \hline
+
+
+\end{tabular}
+
+\end{center}
+
+	''',
+
+}
+
+latex_additional_files = ["_static/xuantielogo.png"]
+
+latex_documents = [
+    (master_doc, u'玄铁QEMU用户手册{}.tex'.format(release), u'玄铁QEMU用户手册',
+     u'', 'manual'),
+]
+
+# -- Options for Texinfo output
+
+texinfo_documents = [
+    (master_doc, '玄铁QEMU用户手册', u'玄铁QEMU用户手册 Documentation',
+     author, '玄铁QEMU用户手册', 'One line description of project.',
+     'Miscellaneous'),
+]

docs/csky/cskysim.rst

@@ -0,0 +1,31 @@
+==========================
+cskysim
+==========================
+
+cskysim 是为了简化 玄铁 QEMU 系统模式使用，提供的一个 QEMU 启动程序。
+cskysim 用 xml 文件整合了常用的 QEMU 参数，为用户提供了 玄铁 虚拟环境的典型参数。
+另外，cskysim 跟 QMEU 配合，还提供了动态加载外设等功能。
+
+------------------
+Linux 平台下的使用
+------------------
+
+Linux的安装目录下，soccfg 中，可以找到默认的 xml 文件，这些文件提供了通用的 cskysim 配置。
+
+以运行 E906 Smartl SDK(从 https://www.xrvm.cn/ 下载) 为例，可以用 -soc 参数指定 xml 配置文件，用 -kernel 指定 elf 文件。如果需要调整 QEMU 参数，可以修改 xml 文件，或者直接在命令行后直接加更多的 QEMU 参数。
+
+.. code-block:: none
+
+    cskysim -soc soccfg/riscv32/smartl_906_cfg.xml -kernel path/of/yours.elf -nographic
+
+--------------------
+Windows 平台下的使用
+--------------------
+
+以运行 E906 Smartl SDK 为例，-soc 参数指定 xml 配置文件，其他参数用法与 QEMU 相同。
+
+.. code-block:: none
+
+    cskysim.exe -soc soccfg/riscv32/smartl_906_cfg.xml -kernel path/of/yours.elf -nographic
+
+cskysim 中 xml 文件，可以来自 QEMU 二进制包中的 soccfg，也可以使用 CDS/CDK 等集成开发环境自定义配置，具体参见 CDS 或 CDK 的用户手册。

docs/csky/index.rst

@@ -0,0 +1,19 @@
+.. csi-dsp documentation master file, created by
+   sphinx-quickstart on Sun Apr 29 05:24:45 2018.
+   You can adapt this file completely to your liking, but it should at least
+   contain the root `toctree` directive.
+
+XuanTie QEMU User Guide
+===================================
+
+.. toctree::
+   :maxdepth: 2
+   :caption: Contents:
+
+   introduction
+   build
+   quick_start
+   options
+   cskysim
+   user_space_emulator
+   linux

docs/csky/introduction.rst

@@ -0,0 +1,142 @@
+==========================
+玄铁 QEMU
+==========================
+
+------------
+简介
+------------
+
+玄铁 QEMU 是一个以开源项目 QEMU 为基础，支持 玄铁 处理器的软件模拟器，提供了带基本外设的 玄铁 开发板模板。
+
+此外 玄铁 QEMU 还添加了启动程序 cskysim，动态加载外设，profiling 等功能。
+
+玄铁 QEMU 的特点：
+
+1.	支持 Linux 和 windows 操作系统。
+2.	支持 RISC-V 和 C-SKY 两种体系结构。
+3.	可以模拟多种外设，比如网卡，声卡，USB，磁盘等。
+4.	不经过 bootloader 就能引导 C-SKY Linux 内核。
+5.	多种输出方式，不依赖于 host 系统，可以是 SSH，模拟串口等。
+6.	执行不需要管理员权限。
+7.	动态编译技术提供的高速模拟。
+8.	可模拟多核心 CPU，甚至多 CPU。
+
+
+---------------
+支持的 CPU 型号
+---------------
+
+玄铁 QEMU 同步支持所有现存的 玄铁 CPU，支持 C-SKY 和 RISC-V 两种 ARCH，包括但不限于以下 CPU 型号。
+
+**C-SKY ARCH CPU 列表:**
+
+  .. table:: CPU 型号
+
+    +----------+------------+
+    | CPU 型号 | 可选特性   |
+    +==========+============+
+    | e801     |            |
+    +----------+------------+
+    | e802     | t          |
+    +----------+------------+
+    | e803     | t          |
+    +----------+------------+
+    | e804     | d, f, t    |
+    +----------+------------+
+    | s802     | t          |
+    +----------+------------+
+    | s803     | t          |
+    +----------+------------+
+    | i805     | f          |
+    +----------+------------+
+    | c807     | f, v       |
+    +----------+------------+
+    | c810     | t, v       |
+    +----------+------------+
+    | c860     | v          |
+    +----------+------------+
+    | r807     | f          |
+    +----------+------------+
+
+
+此外还支持一些旧的型号和命名方式：
+
+
+  .. table:: CPU 型号
+
+    +----------+----------+------------+
+    | ABI      | CPU 型号 | 可选特性   |
+    +==========+==========+============+
+    | ABIv1    | CK510    | e          |
+    +          +----------+------------+
+    |          | CK610    | e, f       |
+    +----------+----------+------------+
+    | ABIv2    | CK801    | t          |
+    +          +----------+------------+
+    |          | CK802    | j, t       |
+    +          +----------+------------+
+    |          | CK803    | e, f, t    |
+    +          +----------+------------+
+    |          | CK804    | e, f       |
+    +          +----------+------------+
+    |          | CK805    | f          |
+    +          +----------+------------+
+    |          | CK807    | e, f       |
+    +          +----------+------------+
+    |          | CK810    | e, f, t    |
+    +          +----------+------------+
+    |          | CK860    | f, v       |
+    +----------+----------+------------+
+
+**RISC-V ARCH CPU 列表:**
+
+  .. table:: CPU 型号
+
+    +----------+------------+
+    | CPU 型号 | 可选特性   |
+    +==========+============+
+    | e902     | m, t       |
+    +----------+------------+
+    | e906     | f, d, p    |
+    +----------+------------+
+    | e907     | f, d, p    |
+    +----------+------------+
+    | c906     | f, d, v    |
+    +----------+------------+
+    | c907     | f, d, v, m |
+    +----------+------------+
+    | c908     | v          |
+    +----------+------------+
+    | c910     | v          |
+    +----------+------------+
+    | c920     | 无         |
+    +----------+------------+
+    | c910v2   | 无         |
+    +----------+------------+
+    | c920v2   | 无         |
+    +----------+------------+
+    | c910v3   | cp         |
+    +----------+------------+
+    | c920v3   | cp         |
+    +----------+------------+
+    | r908     | fd, v, cp  |
+    +----------+------------+
+    | r910     | 无         |
+    +----------+------------+
+    | r920     | 无         |
+    +----------+------------+
+
+------------
+框架结构
+------------
+
+玄铁 QEMU 主要基于 QEMU 的 system emulator，模拟基于 玄铁 CPU 的 SOC 和开发板，包括 CPU 和外围设备，如 TIMER、UART 等。运行在真实开发板上的程序或者操作系统可以不经过修改，在 玄铁 QEMU 上直接运行。
+
+玄铁 QEMU 结构框架如下：
+
+  .. figure:: /figure/introduce.png
+    :align: center
+    :scale: 100%
+    :name: introduce
+
+    框架

docs/csky/linux.rst

@@ -0,0 +1,108 @@
+==========================
+Linux 运行与调试
+==========================
+
+-------------
+运行 Linux
+-------------
+
+运行RISC-V Linux操作系统( Image 从 https://github.com/XUANTIE-RV/zero_stage_boot/releases 下载，Rootfs 从 https://github.com/c-sky/buildroot/releases 下载)
+
+.. code-block:: none
+
+  qemu-system-riscv64 -M virt -cpu c908v -bios fw_dynamic.bin -kernel Image -append "rootwait root=/dev/vda ro" -drive file=rootfs.ext2,format=raw,id=hd0 -device virtio-blk-device,drive=hd0 -nographic -smp 1
+
+-------------------
+9pfs共享目录
+-------------------
+
+在主机中创建共享的目录
+
+.. code-block:: none
+
+  mkdir -p /home/csky/shared
+
+启动QEMU，增加命令行参数
+
+.. code-block:: none
+
+  -fsdev local,security_model=mapped-xattr,id=fsdev0,path=/home/csky/shared -device virtio-9p-pci,id=fs0,fsdev=fsdev0,mount_tag=hostshare
+
+内核启动后，创建目录，并和主机的目录建立共享关系
+
+.. code-block:: none
+
+  mkdir -p /root/host_shared
+  mount -t 9p -o trans=virtio,version=9p2000.L hostshare /root/host_shared/
+
+这样就可以通过/root/host_shared/访问主机上的/home/csky/shared
+
+-----------------
+tftp服务器
+-----------------
+
+还可以通过用户模式网络中搭建tftp服务器的方式，传入测试文件。
+
+启动QEMU，增加命令行参数
+
+.. code-block:: none
+
+  -device virtio-net-device,netdev=net0 -netdev user,id=net0,tftp=/mnt/ssd/hello
+
+主机目录 /mnt/ssd/hello 作为 ftp 服务器根目录。Guest 可通过如下命令，下载 /mnt/ssd/hello 中的 hello.elf
+
+.. code-block:: none
+
+  tftp -g -r hello.elf 10.0.2.2
+
+-----------------------------
+gdbserver 调试应用程序
+-----------------------------
+
+gdbserver 通过 9pfs 或 ftp 服务器方式传入 Guest Linux 中。gdbserver 通过一个网络端口对外提供服务。
+
+启动QEMU，增加命令行参数
+
+.. code-block:: none
+
+  -netdev user,hostfwd=tcp:192.168.0.60:50222-10.0.2.15:1001,id=net0
+
+命令中 “-device virtio-net-device,netdev=net0“，创建一个 virtio 的虚拟网卡。这个网卡的后端由 "-netdev user,hostfwd=tcp:192.168.0.60:50222-10.0.2.15:1001,id=net0" 描述，user 表明使用 usermode 网络。hostfwd 描述了转发 host 端口到 guest 端口的转发规则。tcp 表明对 tcp 协议转发，192.168.0.60 是 host 机 ip 地址，50222 是 host 的端口，10.0.2.15 是 guest 机 ip 地址，1001 是 guest 用于 ssh 通信的端口。
+
+qemu启动 linux 系统后，需要设置网卡 ip
+
+.. code-block:: none
+
+  ifconfig eth0 10.0.2.15
+
+增加默认路由
+
+.. code-block:: none
+
+  route add default gw 10.0.2.2
+
+调试所需工具和网络环境都已配置完成，下面开始调试应用程序。
+
+在Guest Linux中运行被调试程序，
+
+.. code-block:: none
+
+  gdbserver 10.0.2.15:1001 /root/host_shared/jdk/bin/java。
+
+这时命令行端口中输出
+
+.. code-block:: none
+
+  Process ./jdk2/bin/java created; pid = 110
+  Listening on port 1001
+  Remote debugging from host 192.168.0.60, port 45920
+
+等待gdb 连接。
+
+在Host 中使用 gdb连接程序
+
+.. code-block:: none
+
+  tar remote 192.168.0.60:50222
+
+这样就可以连接上了。

docs/csky/options.rst

@@ -0,0 +1,45 @@
+==========================
+选项
+==========================
+
+-------------------
+常用选项
+-------------------
+
+以下是一些常用选项，更多的选项可以参考 《QEMU Emulator User Documentation》。
+
+.. option:: -help
+
+    显示帮助信息。
+
+.. option:: -version
+
+    显示版本信息。
+
+.. option:: -machine
+
+    选择模拟的开发板，可以输入 -machine help 获取一个完整的开发板列表。
+
+.. option:: -cpu
+
+    选择 CPU 类型（例如 -cpu c907），可以输入 -cpu help 获取完整的 CPU 列表。
+
+.. option:: -nographic
+
+    禁止所有的图形输出，模拟的串口将会重定向到命令行。
+
+.. option:: -gdb tcp::port
+
+    设置连接 GDB 的端口，（例如 -gdb tcp::23333, 将23333作为 GDB 的连接端口）。
+
+.. option:: -S
+
+    在启动时冻结 CPU ，（例如与 -gdb 配合，通过 GDB 控制继续执行）。
+
+.. option:: -CPF
+
+    使用网络端口 8810 输出 trace 信息给 CPF 使用。
+
+.. option:: -csky-trace
+
+    控制 CPF trace 的详细选项，可以输入 -csky-trace help 获取一个完整的选项列表。

docs/csky/quick_start.rst

@@ -0,0 +1,57 @@
+==========================
+使用示例
+==========================
+
+-----------------
+简易示例
+-----------------
+
+下面以 CDS/剑池 CDK 中的示例 C-SKY UART 程序，来演示系统模式的使用。
+
+该例子中如果 UART 正常工作，将在终端上输出一系列的字母等信息，否则会出现错误信息，甚至没有任何提示。
+
+编译 UART 示例程序的具体过程可以参考 CDS/剑池 CDK 的用户手册，下面我们用 玄铁 QEMU 运行该示例编译出的 elf 文件。
+
+.. code-block:: none
+
+  qemu-system-riscv32 -machine smartl -kernel  /path/of/Uart.elf -nographic
+
+QEMU会在终端，将UART示例执行过程的打印，显示如下：
+
+  .. figure:: /figure/uart_output.png
+    :align: center
+    :scale: 100%
+    :name: uart_output
+
+    UART 输出
+
+
+-----------------
+使用 GDB 调试
+-----------------
+
+下面仍然以 QEMU 运行 UART 示例程序为例，来说明如何在使用 GDB 来调试 QEMU 上执行的程序。
+
+玄铁 QEMU 使用与上例类似参数，并追加调试的参数，打开端口23333，等待远程 GDB 调试终端链接，具体如下命令：
+
+.. code-block:: none
+
+  qemu-system-riscv32 -machine smartl -kernel /path/of/Uart.elf -nographic -gdb tcp::23333 -S
+
+
+如上，玄铁 QEMU 在等待远程连接到端口23333。从其他命令行窗口中，用 csky-gdb 接需要调试的 elf 文件：
+
+.. code-block:: none
+
+  riscv64-unknown-elf-gdb /path/of/uart_test/Uart.elf
+
+
+在 GDB 的提示后，输入以下命令连接 QEMU：
+
+.. code-block:: none
+
+  (cskygdb) target remote localhost:23333
+
+本例当中 GDB 连接的目标端口是由参数 -gdb tcp::23333 指定为 23333。
+
+接下来便可以与调试硬件开发板一样使用 GDB 进行调试了。例如设断点，单步执行，查看寄存器值等操作。

docs/csky/user_space_emulator.rst

@@ -0,0 +1,93 @@
+==========================
+玄铁 QEMU 用户模式
+==========================
+
+------------
+简介
+------------
+
+玄铁 QEMU 用户模式是提供 玄铁 Linux 应用程序执行环境的一个模式。允许直接执行绝大多数 玄铁 Linux 应用程序。
+
+-------------------
+从源码编译
+-------------------
+
+这节，以从源码编译 ABIV2 的 C-SKY 用户模式为例，描述了如何从源码编译 C-SKY 用户模式。
+
+
+**编译：**
+
+.. code-block:: none
+
+  mkdir build
+  ../configure --target-list=cskyv2-linux-user
+  make
+
+编译RISC-V 用户模式。
+
+**编译：**
+
+.. code-block:: none
+
+  mkdir build
+  ../configure --target-list=riscv64-linux-user
+  make
+
+如果需要安装可执行程序到本机执行目录，则可以 **安装：**
+
+.. code-block:: none
+
+  make install
+
+
+-----------------
+用户模式简易示例
+-----------------
+
+**用户模拟** 是 玄铁 QEMU 模拟 Linux 程序执行环境的模式。
+
+以仅有 ``hello world`` 打印的 main.c 为例。
+
+如果程序正常执行，将在终端上输出 ``hello world``，否则会出现错误信息，甚至没有任何提示。
+
+.. code-block:: none
+
+  qemu-riscv64 -cpu c920v2 /path/of/a.out
+
+对动态编译的程序，还需要指定动态链接器及依赖动态库的路径。
+
+.. code-block:: none
+
+  qemu-riscv64 -cpu c920v2 -L /home/roman/tools/Xuantie-900-gcc-linux-5.10.4-glibc-x86_64-V2.7.0/sysroot -E LD_LIBRARY_PATH=./  /path/of/a.out
+
+-L指定动态链接器的路径，-E LD_LIBRARY_PATH指令程序依赖的动态库路径。
+
+
+-----------------
+使用 GDB 调试
+-----------------
+
+下面仍然以 玄铁 QEMU 运行 ``hello world`` 示例程序为例，来说明如何在使用 GDB 来调试 QEMU 上执行的程序。
+
+QEMU 使用与上例类似参数，并追加调试的参数，打开端口 23333， 等待远程 GDB 调试终端链接，具体如下命令：
+
+.. code-block:: none
+
+  qemu-riscv64 -cpu c920v2 -g 23333 /path/of/a.out
+
+如上，QEMU 在等待远程连接到端口23333。 从其他命令行窗口中，用 riscv-gdb 接需要调试的 elf 文件：
+
+.. code-block:: none
+
+  riscv64-unknown-linux-gnu-gdb /path/of/a.out
+
+
+在 GDB 的提示后，输入以下命令连接 QEMU：
+
+.. code-block:: none
+
+  (cskygdb) target remote localhost:23333
+
+本例当中 GDB 连接的端口是由参数 -g 23333 指定为 23333。
+
+接下来便可以与调试普通 Linux 应用程序一样使用 GDB 进行调试了。例如设断点，单步执行，查看寄存器值等操作。

docs/specs/pci-ids.rst

@@ -94,6 +94,8 @@ PCI devices (other than virtio):
   PCI ACPI ERST device (``-device acpi-erst``)
 1b36:0013
   PCI UFS device (``-device ufs``)
+1b36:0014
+  PCI RISC-V IOMMU device
 
 All these devices are documented in :doc:`index`.
 

docs/system/riscv/virt.rst

@@ -116,6 +116,12 @@ The following machine-specific options are supported:
   having AIA IMSIC (i.e. "aia=aplic-imsic" selected). When not specified,
   the default number of per-HART VS-level AIA IMSIC pages is 0.
 
+- iopmp=[on|off]
+
+  When this option is "on", an IOPMP device is added to machine. It checks dma
+  operations from the generic PCIe host bridge. This option is assumed to be
+  "off".
+
 Running Linux kernel
 --------------------
 

fpu/softfloat-specialize.c.inc

@@ -294,6 +294,44 @@ bool bfloat16_is_quiet_nan(bfloat16 a_, float_status *status)
     }
 }
 
+/*----------------------------------------------------------------------------
+| Returns 1 if the float8e4 value `a' is a quiet
+| NaN; otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+bool float8e4_is_quiet_nan(float8e4 a_, float_status *status)
+{
+    if (no_signaling_nans(status)) {
+        return float8e4_is_any_nan(a_);
+    } else {
+        uint8_t a = a_;
+        if (snan_bit_is_one(status)) {
+            return (((a >> 2) & 0x1F) == 0x1E) && (a & 0x3);
+        } else {
+            return ((a >> 2) & 0x1F) == 0x1F;
+        }
+    }
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the float8e5 value `a' is a quiet
+| NaN; otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+bool float8e5_is_quiet_nan(float8e5 a_, float_status *status)
+{
+    if (no_signaling_nans(status)) {
+        return float8e5_is_any_nan(a_);
+    } else {
+        uint8_t a = a_;
+        if (snan_bit_is_one(status)) {
+            return (((a >> 1) & 0x3F) == 0x3E) && (a & 0x1);
+        } else {
+            return ((a >> 1) & 0x3F) == 0x3F;
+        }
+    }
+}
+
 /*----------------------------------------------------------------------------
 | Returns 1 if the half-precision floating-point value `a' is a signaling
 | NaN; otherwise returns 0.
@@ -332,6 +370,44 @@ bool bfloat16_is_signaling_nan(bfloat16 a_, float_status *status)
     }
 }
 
+/*----------------------------------------------------------------------------
+| Returns 1 if the float8e4 value `a' is a signaling
+| NaN; otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+bool float8e4_is_signaling_nan(float8e4 a_, float_status *status)
+{
+    if (no_signaling_nans(status)) {
+        return 0;
+    } else {
+        uint8_t a = a_;
+        if (snan_bit_is_one(status)) {
+            return ((a >> 2) & 0x1F) == 0x1F;
+        } else {
+            return (((a >> 2) & 0x1F) == 0x1E) && (a & 0x3);
+        }
+    }
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the float8e5 value `a' is a signaling
+| NaN; otherwise returns 0.
+*----------------------------------------------------------------------------*/
+
+bool float8e5_is_signaling_nan(float8e5 a_, float_status *status)
+{
+    if (no_signaling_nans(status)) {
+        return 0;
+    } else {
+        uint8_t a = a_;
+        if (snan_bit_is_one(status)) {
+            return ((a >> 1) & 0x3F) == 0x3F;
+        } else {
+            return (((a >> 1) & 0x3F) == 0x3E) && (a & 0x1);
+        }
+    }
+}
+
 /*----------------------------------------------------------------------------
 | Returns 1 if the single-precision floating-point value `a' is a quiet
 | NaN; otherwise returns 0.

gdb-xml/csky-abiv1-linux-user-core.xml

@@ -0,0 +1,89 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2008 Free Software Foundation, Inc.
+
+     Copying and distribution of this file, with or without modification,
+     are permitted in any medium without royalty provided the copyright
+     notice and this notice are preserved.  -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.csky.abiv1.gpr">
+  <reg name="r0"  bitsize="32" regnum="0"  group="gpr"/>
+  <reg name="r1"  bitsize="32" regnum="1"  group="gpr"/>
+  <reg name="r2"  bitsize="32" regnum="2"  group="gpr"/>
+  <reg name="r3"  bitsize="32" regnum="3"  group="gpr"/>
+  <reg name="r4"  bitsize="32" regnum="4"  group="gpr"/>
+  <reg name="r5"  bitsize="32" regnum="5"  group="gpr"/>
+  <reg name="r6"  bitsize="32" regnum="6"  group="gpr"/>
+  <reg name="r7"  bitsize="32" regnum="7"  group="gpr"/>
+  <reg name="r8"  bitsize="32" regnum="8"  group="gpr"/>
+  <reg name="r9"  bitsize="32" regnum="9"  group="gpr"/>
+  <reg name="r10" bitsize="32" regnum="10" group="gpr"/>
+  <reg name="r11" bitsize="32" regnum="11" group="gpr"/>
+  <reg name="r12" bitsize="32" regnum="12" group="gpr"/>
+  <reg name="r13" bitsize="32" regnum="13" group="gpr"/>
+  <reg name="r14" bitsize="32" regnum="14" group="gpr"/>
+  <reg name="r15" bitsize="32" regnum="15" group="gpr"/>
+  <reg name="hi"  bitsize="32" regnum="20"/>
+  <reg name="lo"  bitsize="32" regnum="21"/>
+  <reg name="pc"  bitsize="32" regnum="72"/>
+  <reg name="cp1gr0"  bitsize="32" regnum="24" group="fpu"/>
+  <reg name="cp1gr1"  bitsize="32" regnum="25" group="fpu"/>
+  <reg name="cp1gr2"  bitsize="32" regnum="26" group="fpu"/>
+  <reg name="cp1gr3"  bitsize="32" regnum="27" group="fpu"/>
+  <reg name="cp1gr4"  bitsize="32" regnum="28" group="fpu"/>
+  <reg name="cp1gr5"  bitsize="32" regnum="29" group="fpu"/>
+  <reg name="cp1gr6"  bitsize="32" regnum="30" group="fpu"/>
+  <reg name="cp1gr7"  bitsize="32" regnum="31" group="fpu"/>
+  <reg name="cp1gr8"  bitsize="32" regnum="32" group="fpu"/>
+  <reg name="cp1gr9"  bitsize="32" regnum="33" group="fpu"/>
+  <reg name="cp1gr10" bitsize="32" regnum="34" group="fpu"/>
+  <reg name="cp1gr11" bitsize="32" regnum="35" group="fpu"/>
+  <reg name="cp1gr12" bitsize="32" regnum="36" group="fpu"/>
+  <reg name="cp1gr13" bitsize="32" regnum="37" group="fpu"/>
+  <reg name="cp1gr14" bitsize="32" regnum="38" group="fpu"/>
+  <reg name="cp1gr15" bitsize="32" regnum="39" group="fpu"/>
+  <reg name="cp1gr16" bitsize="32" regnum="40" group="fpu"/>
+  <reg name="cp1gr17" bitsize="32" regnum="41" group="fpu"/>
+  <reg name="cp1gr18" bitsize="32" regnum="42" group="fpu"/>
+  <reg name="cp1gr19" bitsize="32" regnum="43" group="fpu"/>
+  <reg name="cp1gr20" bitsize="32" regnum="44" group="fpu"/>
+  <reg name="cp1gr21" bitsize="32" regnum="45" group="fpu"/>
+  <reg name="cp1gr22" bitsize="32" regnum="46" group="fpu"/>
+  <reg name="cp1gr23" bitsize="32" regnum="47" group="fpu"/>
+  <reg name="cp1gr24" bitsize="32" regnum="48" group="fpu"/>
+  <reg name="cp1gr25" bitsize="32" regnum="49" group="fpu"/>
+  <reg name="cp1gr26" bitsize="32" regnum="50" group="fpu"/>
+  <reg name="cp1gr27" bitsize="32" regnum="51" group="fpu"/>
+  <reg name="cp1gr28" bitsize="32" regnum="52" group="fpu"/>
+  <reg name="cp1gr29" bitsize="32" regnum="53" group="fpu"/>
+  <reg name="cp1gr30" bitsize="32" regnum="54" group="fpu"/>
+  <reg name="cp1gr31" bitsize="32" regnum="55" group="fpu"/>
+  <reg name="psr"     bitsize="32" regnum="89"  group="cr"/>
+  <reg name="cp1cr0" bitsize="32" regnum="121" group="fcr"/>
+  <reg name="cp1cr1" bitsize="32" regnum="122" group="fcr"/>
+  <reg name="cp1cr2" bitsize="32" regnum="123" group="fcr"/>
+  <reg name="cp1cr3" bitsize="32" regnum="124" group="fcr"/>
+  <reg name="cp1cr4" bitsize="32" regnum="125" group="fcr"/>
+  <reg name="cp1cr5" bitsize="32" regnum="126" group="fcr"/>
+  <reg name="cp1cr6" bitsize="32" regnum="127" group="fcr"/>
+  <reg name="cp15cr0"  bitsize="32" regnum="128" group="mmu"/>
+  <reg name="cp15cr1"  bitsize="32" regnum="129" group="mmu"/>
+  <reg name="cp15cr2"  bitsize="32" regnum="130" group="mmu"/>
+  <reg name="cp15cr3"  bitsize="32" regnum="131" group="mmu"/>
+  <reg name="cp15cr4"  bitsize="32" regnum="132" group="mmu"/>
+  <reg name="cp15cr5"  bitsize="32" regnum="133" group="mmu"/>
+  <reg name="cp15cr6"  bitsize="32" regnum="134" group="mmu"/>
+  <reg name="cp15cr7"  bitsize="32" regnum="135" group="mmu"/>
+  <reg name="cp15cr8"  bitsize="32" regnum="136" group="mmu"/>
+  <reg name="cp15cr9"  bitsize="32" regnum="137" group="mmu"/>
+  <reg name="cp15cr10" bitsize="32" regnum="138" group="mmu"/>
+  <reg name="cp15cr11" bitsize="32" regnum="139" group="mmu"/>
+  <reg name="cp15cr12" bitsize="32" regnum="140" group="mmu"/>
+  <reg name="cp15cr13" bitsize="32" regnum="141" group="mmu"/>
+  <reg name="cp15cr14" bitsize="32" regnum="142" group="mmu"/>
+  <reg name="cp15cr15" bitsize="32" regnum="143" group="mmu"/>
+  <reg name="cp15cr16" bitsize="32" regnum="144" group="mmu"/>
+  <reg name="cp15cr29" bitsize="32" regnum="145" group="mmu"/>
+  <reg name="cp15cr30" bitsize="32" regnum="146" group="mmu"/>
+  <reg name="cp15cr31" bitsize="32" regnum="147" group="mmu"/>
+</feature>

gdb-xml/csky-abiv1-softmmu-core.xml

@@ -0,0 +1,135 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2008 Free Software Foundation, Inc.
+
+     Copying and distribution of this file, with or without modification,
+     are permitted in any medium without royalty provided the copyright
+     notice and this notice are preserved.  -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.csky.abiv1.gpr">
+  <reg name="r0"  bitsize="32" regnum="0"  group="gpr"/>
+  <reg name="r1"  bitsize="32" regnum="1"  group="gpr"/>
+  <reg name="r2"  bitsize="32" regnum="2"  group="gpr"/>
+  <reg name="r3"  bitsize="32" regnum="3"  group="gpr"/>
+  <reg name="r4"  bitsize="32" regnum="4"  group="gpr"/>
+  <reg name="r5"  bitsize="32" regnum="5"  group="gpr"/>
+  <reg name="r6"  bitsize="32" regnum="6"  group="gpr"/>
+  <reg name="r7"  bitsize="32" regnum="7"  group="gpr"/>
+  <reg name="r8"  bitsize="32" regnum="8"  group="gpr"/>
+  <reg name="r9"  bitsize="32" regnum="9"  group="gpr"/>
+  <reg name="r10" bitsize="32" regnum="10" group="gpr"/>
+  <reg name="r11" bitsize="32" regnum="11" group="gpr"/>
+  <reg name="r12" bitsize="32" regnum="12" group="gpr"/>
+  <reg name="r13" bitsize="32" regnum="13" group="gpr"/>
+  <reg name="r14" bitsize="32" regnum="14" group="gpr"/>
+  <reg name="r15" bitsize="32" regnum="15" group="gpr"/>
+  <reg name="hi"  bitsize="32" regnum="20"/>
+  <reg name="lo"  bitsize="32" regnum="21"/>
+  <reg name="pc"  bitsize="32" regnum="72"/>
+  <reg name="cp1gr0"  bitsize="32" regnum="24" group="fpu"/>
+  <reg name="cp1gr1"  bitsize="32" regnum="25" group="fpu"/>
+  <reg name="cp1gr2"  bitsize="32" regnum="26" group="fpu"/>
+  <reg name="cp1gr3"  bitsize="32" regnum="27" group="fpu"/>
+  <reg name="cp1gr4"  bitsize="32" regnum="28" group="fpu"/>
+  <reg name="cp1gr5"  bitsize="32" regnum="29" group="fpu"/>
+  <reg name="cp1gr6"  bitsize="32" regnum="30" group="fpu"/>
+  <reg name="cp1gr7"  bitsize="32" regnum="31" group="fpu"/>
+  <reg name="cp1gr8"  bitsize="32" regnum="32" group="fpu"/>
+  <reg name="cp1gr9"  bitsize="32" regnum="33" group="fpu"/>
+  <reg name="cp1gr10" bitsize="32" regnum="34" group="fpu"/>
+  <reg name="cp1gr11" bitsize="32" regnum="35" group="fpu"/>
+  <reg name="cp1gr12" bitsize="32" regnum="36" group="fpu"/>
+  <reg name="cp1gr13" bitsize="32" regnum="37" group="fpu"/>
+  <reg name="cp1gr14" bitsize="32" regnum="38" group="fpu"/>
+  <reg name="cp1gr15" bitsize="32" regnum="39" group="fpu"/>
+  <reg name="cp1gr16" bitsize="32" regnum="40" group="fpu"/>
+  <reg name="cp1gr17" bitsize="32" regnum="41" group="fpu"/>
+  <reg name="cp1gr18" bitsize="32" regnum="42" group="fpu"/>
+  <reg name="cp1gr19" bitsize="32" regnum="43" group="fpu"/>
+  <reg name="cp1gr20" bitsize="32" regnum="44" group="fpu"/>
+  <reg name="cp1gr21" bitsize="32" regnum="45" group="fpu"/>
+  <reg name="cp1gr22" bitsize="32" regnum="46" group="fpu"/>
+  <reg name="cp1gr23" bitsize="32" regnum="47" group="fpu"/>
+  <reg name="cp1gr24" bitsize="32" regnum="48" group="fpu"/>
+  <reg name="cp1gr25" bitsize="32" regnum="49" group="fpu"/>
+  <reg name="cp1gr26" bitsize="32" regnum="50" group="fpu"/>
+  <reg name="cp1gr27" bitsize="32" regnum="51" group="fpu"/>
+  <reg name="cp1gr28" bitsize="32" regnum="52" group="fpu"/>
+  <reg name="cp1gr29" bitsize="32" regnum="53" group="fpu"/>
+  <reg name="cp1gr30" bitsize="32" regnum="54" group="fpu"/>
+  <reg name="cp1gr31" bitsize="32" regnum="55" group="fpu"/>
+  <reg name="ar0"  bitsize="32" regnum="73" group="gar"/>
+  <reg name="ar1"  bitsize="32" regnum="74" group="gar"/>
+  <reg name="ar2"  bitsize="32" regnum="75" group="gar"/>
+  <reg name="ar3"  bitsize="32" regnum="76" group="gar"/>
+  <reg name="ar4"  bitsize="32" regnum="77" group="gar"/>
+  <reg name="ar5"  bitsize="32" regnum="78" group="gar"/>
+  <reg name="ar6"  bitsize="32" regnum="79" group="gar"/>
+  <reg name="ar7"  bitsize="32" regnum="80" group="gar"/>
+  <reg name="ar8"  bitsize="32" regnum="81" group="gar"/>
+  <reg name="ar9"  bitsize="32" regnum="82" group="gar"/>
+  <reg name="ar10" bitsize="32" regnum="83" group="gar"/>
+  <reg name="ar11" bitsize="32" regnum="84" group="gar"/>
+  <reg name="ar12" bitsize="32" regnum="85" group="gar"/>
+  <reg name="ar13" bitsize="32" regnum="86" group="gar"/>
+  <reg name="ar14" bitsize="32" regnum="87" group="gar"/>
+  <reg name="ar15" bitsize="32" regnum="88" group="gar"/>
+  <reg name="psr"  bitsize="32" regnum="89"  group="cr"/>
+  <reg name="vbr"  bitsize="32" regnum="90"  group="cr"/>
+  <reg name="epsr" bitsize="32" regnum="91"  group="cr"/>
+  <reg name="fpsr" bitsize="32" regnum="92"  group="cr"/>
+  <reg name="epc"  bitsize="32" regnum="93"  group="cr"/>
+  <reg name="fpc"  bitsize="32" regnum="94"  group="cr"/>
+  <reg name="ss0"  bitsize="32" regnum="95"  group="cr"/>
+  <reg name="ss1"  bitsize="32" regnum="96"  group="cr"/>
+  <reg name="ss2"  bitsize="32" regnum="97"  group="cr"/>
+  <reg name="ss3"  bitsize="32" regnum="98"  group="cr"/>
+  <reg name="ss4"  bitsize="32" regnum="99"  group="cr"/>
+  <reg name="gcr"  bitsize="32" regnum="100" group="cr"/>
+  <reg name="gsr"  bitsize="32" regnum="101" group="cr"/>
+  <reg name="cr13" bitsize="32" regnum="102" group="cr"/>
+  <reg name="cr14" bitsize="32" regnum="103" group="cr"/>
+  <reg name="cr15" bitsize="32" regnum="104" group="cr"/>
+  <reg name="cr16" bitsize="32" regnum="105" group="cr"/>
+  <reg name="cr17" bitsize="32" regnum="106" group="cr"/>
+  <reg name="cr18" bitsize="32" regnum="107" group="cr"/>
+  <reg name="cr19" bitsize="32" regnum="108" group="cr"/>
+  <reg name="cr20" bitsize="32" regnum="109" group="cr"/>
+  <reg name="cr21" bitsize="32" regnum="110" group="cr"/>
+  <reg name="cr22" bitsize="32" regnum="111" group="cr"/>
+  <reg name="cr23" bitsize="32" regnum="112" group="cr"/>
+  <reg name="cr24" bitsize="32" regnum="113" group="cr"/>
+  <reg name="cr25" bitsize="32" regnum="114" group="cr"/>
+  <reg name="cr26" bitsize="32" regnum="115" group="cr"/>
+  <reg name="cr27" bitsize="32" regnum="116" group="cr"/>
+  <reg name="cr28" bitsize="32" regnum="117" group="cr"/>
+  <reg name="cr29" bitsize="32" regnum="118" group="cr"/>
+  <reg name="cr30" bitsize="32" regnum="119" group="cr"/>
+  <reg name="cp1cr0" bitsize="32" regnum="121" group="fcr"/>
+  <reg name="cp1cr1" bitsize="32" regnum="122" group="fcr"/>
+  <reg name="cp1cr2" bitsize="32" regnum="123" group="fcr"/>
+  <reg name="cp1cr3" bitsize="32" regnum="124" group="fcr"/>
+  <reg name="cp1cr4" bitsize="32" regnum="125" group="fcr"/>
+  <reg name="cp1cr5" bitsize="32" regnum="126" group="fcr"/>
+  <reg name="cp1cr6" bitsize="32" regnum="127" group="fcr"/>
+  <reg name="cp15cr0"  bitsize="32" regnum="128" group="mmu"/>
+  <reg name="cp15cr1"  bitsize="32" regnum="129" group="mmu"/>
+  <reg name="cp15cr2"  bitsize="32" regnum="130" group="mmu"/>
+  <reg name="cp15cr3"  bitsize="32" regnum="131" group="mmu"/>
+  <reg name="cp15cr4"  bitsize="32" regnum="132" group="mmu"/>
+  <reg name="cp15cr5"  bitsize="32" regnum="133" group="mmu"/>
+  <reg name="cp15cr6"  bitsize="32" regnum="134" group="mmu"/>
+  <reg name="cp15cr7"  bitsize="32" regnum="135" group="mmu"/>
+  <reg name="cp15cr8"  bitsize="32" regnum="136" group="mmu"/>
+  <reg name="cp15cr9"  bitsize="32" regnum="137" group="mmu"/>
+  <reg name="cp15cr10" bitsize="32" regnum="138" group="mmu"/>
+  <reg name="cp15cr11" bitsize="32" regnum="139" group="mmu"/>
+  <reg name="cp15cr12" bitsize="32" regnum="140" group="mmu"/>
+  <reg name="cp15cr13" bitsize="32" regnum="141" group="mmu"/>
+  <reg name="cp15cr14" bitsize="32" regnum="142" group="mmu"/>
+  <reg name="cp15cr15" bitsize="32" regnum="143" group="mmu"/>
+  <reg name="cp15cr16" bitsize="32" regnum="144" group="mmu"/>
+  <reg name="cp15cr29" bitsize="32" regnum="145" group="mmu"/>
+  <reg name="cp15cr30" bitsize="32" regnum="146" group="mmu"/>
+  <reg name="cp15cr31" bitsize="32" regnum="147" group="mmu"/>
+</feature>

gdb-xml/csky-abiv2-linux-user-core.xml

@@ -0,0 +1,92 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2008 Free Software Foundation, Inc.
+
+     Copying and distribution of this file, with or without modification,
+     are permitted in any medium without royalty provided the copyright
+     notice and this notice are preserved.  -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.csky.abiv2.gpr">
+  <reg name="r0"  bitsize="32" regnum="0"  group="gpr"/>
+  <reg name="r1"  bitsize="32" regnum="1"  group="gpr"/>
+  <reg name="r2"  bitsize="32" regnum="2"  group="gpr"/>
+  <reg name="r3"  bitsize="32" regnum="3"  group="gpr"/>
+  <reg name="r4"  bitsize="32" regnum="4"  group="gpr"/>
+  <reg name="r5"  bitsize="32" regnum="5"  group="gpr"/>
+  <reg name="r6"  bitsize="32" regnum="6"  group="gpr"/>
+  <reg name="r7"  bitsize="32" regnum="7"  group="gpr"/>
+  <reg name="r8"  bitsize="32" regnum="8"  group="gpr"/>
+  <reg name="r9"  bitsize="32" regnum="9"  group="gpr"/>
+  <reg name="r10" bitsize="32" regnum="10" group="gpr"/>
+  <reg name="r11" bitsize="32" regnum="11" group="gpr"/>
+  <reg name="r12" bitsize="32" regnum="12" group="gpr"/>
+  <reg name="r13" bitsize="32" regnum="13" group="gpr"/>
+  <reg name="r14" bitsize="32" regnum="14" group="gpr"/>
+  <reg name="r15" bitsize="32" regnum="15" group="gpr"/>
+  <reg name="r16" bitsize="32" regnum="16" group="gpr"/>
+  <reg name="r17" bitsize="32" regnum="17" group="gpr"/>
+  <reg name="r18" bitsize="32" regnum="18" group="gpr"/>
+  <reg name="r19" bitsize="32" regnum="19" group="gpr"/>
+  <reg name="r20" bitsize="32" regnum="20" group="gpr"/>
+  <reg name="r21" bitsize="32" regnum="21" group="gpr"/>
+  <reg name="r22" bitsize="32" regnum="22" group="gpr"/>
+  <reg name="r23" bitsize="32" regnum="23" group="gpr"/>
+  <reg name="r24" bitsize="32" regnum="24" group="gpr"/>
+  <reg name="r25" bitsize="32" regnum="25" group="gpr"/>
+  <reg name="r26" bitsize="32" regnum="26" group="gpr"/>
+  <reg name="r27" bitsize="32" regnum="27" group="gpr"/>
+  <reg name="r28" bitsize="32" regnum="28" group="gpr"/>
+  <reg name="r29" bitsize="32" regnum="29" group="gpr"/>
+  <reg name="r30" bitsize="32" regnum="30" group="gpr"/>
+  <reg name="r31" bitsize="32" regnum="31" group="gpr"/>
+  <reg name="hi"  bitsize="32" regnum="36"/>
+  <reg name="lo"  bitsize="32" regnum="37"/>
+  <reg name="pc"  bitsize="32" regnum="72"/>
+  <reg name="fr0"  bitsize="64" regnum="40" group="fpu"/>
+  <reg name="fr1"  bitsize="64" regnum="41" group="fpu"/>
+  <reg name="fr2"  bitsize="64" regnum="42" group="fpu"/>
+  <reg name="fr3"  bitsize="64" regnum="43" group="fpu"/>
+  <reg name="fr4"  bitsize="64" regnum="44" group="fpu"/>
+  <reg name="fr5"  bitsize="64" regnum="45" group="fpu"/>
+  <reg name="fr6"  bitsize="64" regnum="46" group="fpu"/>
+  <reg name="fr7"  bitsize="64" regnum="47" group="fpu"/>
+  <reg name="fr8"  bitsize="64" regnum="48" group="fpu"/>
+  <reg name="fr9"  bitsize="64" regnum="49" group="fpu"/>
+  <reg name="fr10" bitsize="64" regnum="50" group="fpu"/>
+  <reg name="fr11" bitsize="64" regnum="51" group="fpu"/>
+  <reg name="fr12" bitsize="64" regnum="52" group="fpu"/>
+  <reg name="fr13" bitsize="64" regnum="53" group="fpu"/>
+  <reg name="fr14" bitsize="64" regnum="54" group="fpu"/>
+  <reg name="fr15" bitsize="64" regnum="55" group="fpu"/>
+  <reg name="vr0"  bitsize="128" regnum="56" group="fpu"/>
+  <reg name="vr1"  bitsize="128" regnum="57" group="fpu"/>
+  <reg name="vr2"  bitsize="128" regnum="58" group="fpu"/>
+  <reg name="vr3"  bitsize="128" regnum="59" group="fpu"/>
+  <reg name="vr4"  bitsize="128" regnum="60" group="fpu"/>
+  <reg name="vr5"  bitsize="128" regnum="61" group="fpu"/>
+  <reg name="vr6"  bitsize="128" regnum="62" group="fpu"/>
+  <reg name="vr7"  bitsize="128" regnum="63" group="fpu"/>
+  <reg name="vr8"  bitsize="128" regnum="64" group="fpu"/>
+  <reg name="vr9"  bitsize="128" regnum="65" group="fpu"/>
+  <reg name="vr10" bitsize="128" regnum="66" group="fpu"/>
+  <reg name="vr11" bitsize="128" regnum="67" group="fpu"/>
+  <reg name="vr12" bitsize="128" regnum="68" group="fpu"/>
+  <reg name="vr13" bitsize="128" regnum="69" group="fpu"/>
+  <reg name="vr14" bitsize="128" regnum="70" group="fpu"/>
+  <reg name="vr15" bitsize="128" regnum="71" group="fpu"/>
+  <reg name="psr"  bitsize="32"  regnum="89"  group="cr"/>
+  <reg name="fcr"  bitsize="32" regnum="121" group="fvcr"/>
+  <reg name="fid"  bitsize="32" regnum="122" group="fvcr"/>
+  <reg name="fesr" bitsize="32" regnum="123" group="fvcr"/>
+  <!--usp cr_bank1-->
+  <reg name="usp"  bitsize="32" regnum="127"/>
+  <reg name="mcr0"  bitsize="32" regnum="128" group="mmu"/>
+  <reg name="mcr2"  bitsize="32" regnum="129" group="mmu"/>
+  <reg name="mcr3"  bitsize="32" regnum="130" group="mmu"/>
+  <reg name="mcr4"  bitsize="32" regnum="131" group="mmu"/>
+  <reg name="mcr6"  bitsize="32" regnum="132" group="mmu"/>
+  <reg name="mcr8"  bitsize="32" regnum="133" group="mmu"/>
+  <reg name="mcr29" bitsize="32" regnum="134" group="mmu"/>
+  <reg name="mcr30" bitsize="32" regnum="135" group="mmu"/>
+  <reg name="mcr31" bitsize="32" regnum="136" group="mmu"/>
+</feature>

gdb-xml/csky-abiv2-softmmu-core.xml

@@ -0,0 +1,139 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2008 Free Software Foundation, Inc.
+
+     Copying and distribution of this file, with or without modification,
+     are permitted in any medium without royalty provided the copyright
+     notice and this notice are preserved.  -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.csky.abiv2.gpr">
+  <reg name="r0"  bitsize="32" regnum="0"  group="gpr"/>
+  <reg name="r1"  bitsize="32" regnum="1"  group="gpr"/>
+  <reg name="r2"  bitsize="32" regnum="2"  group="gpr"/>
+  <reg name="r3"  bitsize="32" regnum="3"  group="gpr"/>
+  <reg name="r4"  bitsize="32" regnum="4"  group="gpr"/>
+  <reg name="r5"  bitsize="32" regnum="5"  group="gpr"/>
+  <reg name="r6"  bitsize="32" regnum="6"  group="gpr"/>
+  <reg name="r7"  bitsize="32" regnum="7"  group="gpr"/>
+  <reg name="r8"  bitsize="32" regnum="8"  group="gpr"/>
+  <reg name="r9"  bitsize="32" regnum="9"  group="gpr"/>
+  <reg name="r10" bitsize="32" regnum="10" group="gpr"/>
+  <reg name="r11" bitsize="32" regnum="11" group="gpr"/>
+  <reg name="r12" bitsize="32" regnum="12" group="gpr"/>
+  <reg name="r13" bitsize="32" regnum="13" group="gpr"/>
+  <reg name="r14" bitsize="32" regnum="14" group="gpr"/>
+  <reg name="r15" bitsize="32" regnum="15" group="gpr"/>
+  <reg name="r16" bitsize="32" regnum="16" group="gpr"/>
+  <reg name="r17" bitsize="32" regnum="17" group="gpr"/>
+  <reg name="r18" bitsize="32" regnum="18" group="gpr"/>
+  <reg name="r19" bitsize="32" regnum="19" group="gpr"/>
+  <reg name="r20" bitsize="32" regnum="20" group="gpr"/>
+  <reg name="r21" bitsize="32" regnum="21" group="gpr"/>
+  <reg name="r22" bitsize="32" regnum="22" group="gpr"/>
+  <reg name="r23" bitsize="32" regnum="23" group="gpr"/>
+  <reg name="r24" bitsize="32" regnum="24" group="gpr"/>
+  <reg name="r25" bitsize="32" regnum="25" group="gpr"/>
+  <reg name="r26" bitsize="32" regnum="26" group="gpr"/>
+  <reg name="r27" bitsize="32" regnum="27" group="gpr"/>
+  <reg name="r28" bitsize="32" regnum="28" group="gpr"/>
+  <reg name="r29" bitsize="32" regnum="29" group="gpr"/>
+  <reg name="r30" bitsize="32" regnum="30" group="gpr"/>
+  <reg name="r31" bitsize="32" regnum="31" group="gpr"/>
+  <reg name="hi"  bitsize="32" regnum="36"/>
+  <reg name="lo"  bitsize="32" regnum="37"/>
+  <reg name="pc"  bitsize="32" regnum="72"/>
+  <reg name="fr0"  bitsize="64" regnum="40" group="fpu"/>
+  <reg name="fr1"  bitsize="64" regnum="41" group="fpu"/>
+  <reg name="fr2"  bitsize="64" regnum="42" group="fpu"/>
+  <reg name="fr3"  bitsize="64" regnum="43" group="fpu"/>
+  <reg name="fr4"  bitsize="64" regnum="44" group="fpu"/>
+  <reg name="fr5"  bitsize="64" regnum="45" group="fpu"/>
+  <reg name="fr6"  bitsize="64" regnum="46" group="fpu"/>
+  <reg name="fr7"  bitsize="64" regnum="47" group="fpu"/>
+  <reg name="fr8"  bitsize="64" regnum="48" group="fpu"/>
+  <reg name="fr9"  bitsize="64" regnum="49" group="fpu"/>
+  <reg name="fr10" bitsize="64" regnum="50" group="fpu"/>
+  <reg name="fr11" bitsize="64" regnum="51" group="fpu"/>
+  <reg name="fr12" bitsize="64" regnum="52" group="fpu"/>
+  <reg name="fr13" bitsize="64" regnum="53" group="fpu"/>
+  <reg name="fr14" bitsize="64" regnum="54" group="fpu"/>
+  <reg name="fr15" bitsize="64" regnum="55" group="fpu"/>
+  <reg name="vr0"  bitsize="128" regnum="56" group="fpu"/>
+  <reg name="vr1"  bitsize="128" regnum="57" group="fpu"/>
+  <reg name="vr2"  bitsize="128" regnum="58" group="fpu"/>
+  <reg name="vr3"  bitsize="128" regnum="59" group="fpu"/>
+  <reg name="vr4"  bitsize="128" regnum="60" group="fpu"/>
+  <reg name="vr5"  bitsize="128" regnum="61" group="fpu"/>
+  <reg name="vr6"  bitsize="128" regnum="62" group="fpu"/>
+  <reg name="vr7"  bitsize="128" regnum="63" group="fpu"/>
+  <reg name="vr8"  bitsize="128" regnum="64" group="fpu"/>
+  <reg name="vr9"  bitsize="128" regnum="65" group="fpu"/>
+  <reg name="vr10" bitsize="128" regnum="66" group="fpu"/>
+  <reg name="vr11" bitsize="128" regnum="67" group="fpu"/>
+  <reg name="vr12" bitsize="128" regnum="68" group="fpu"/>
+  <reg name="vr13" bitsize="128" regnum="69" group="fpu"/>
+  <reg name="vr14" bitsize="128" regnum="70" group="fpu"/>
+  <reg name="vr15" bitsize="128" regnum="71" group="fpu"/>
+  <reg name="ar0"  bitsize="32" regnum="73" group="gar"/>
+  <reg name="ar1"  bitsize="32" regnum="74" group="gar"/>
+  <reg name="ar2"  bitsize="32" regnum="75" group="gar"/>
+  <reg name="ar3"  bitsize="32" regnum="76" group="gar"/>
+  <reg name="ar4"  bitsize="32" regnum="77" group="gar"/>
+  <reg name="ar5"  bitsize="32" regnum="78" group="gar"/>
+  <reg name="ar6"  bitsize="32" regnum="79" group="gar"/>
+  <reg name="ar7"  bitsize="32" regnum="80" group="gar"/>
+  <reg name="ar8"  bitsize="32" regnum="81" group="gar"/>
+  <reg name="ar9"  bitsize="32" regnum="82" group="gar"/>
+  <reg name="ar10" bitsize="32" regnum="83" group="gar"/>
+  <reg name="ar11" bitsize="32" regnum="84" group="gar"/>
+  <reg name="ar12" bitsize="32" regnum="85" group="gar"/>
+  <reg name="ar13" bitsize="32" regnum="86" group="gar"/>
+  <reg name="ar14" bitsize="32" regnum="87" group="gar"/>
+  <reg name="ar15" bitsize="32" regnum="88" group="gar"/>
+  <reg name="psr"  bitsize="32" regnum="89"  group="cr"/>
+  <reg name="vbr"  bitsize="32" regnum="90"  group="cr"/>
+  <reg name="epsr" bitsize="32" regnum="91"  group="cr"/>
+  <reg name="fpsr" bitsize="32" regnum="92"  group="cr"/>
+  <reg name="epc"  bitsize="32" regnum="93"  group="cr"/>
+  <reg name="fpc"  bitsize="32" regnum="94"  group="cr"/>
+  <reg name="ss0"  bitsize="32" regnum="95"  group="cr"/>
+  <reg name="ss1"  bitsize="32" regnum="96"  group="cr"/>
+  <reg name="ss2"  bitsize="32" regnum="97"  group="cr"/>
+  <reg name="ss3"  bitsize="32" regnum="98"  group="cr"/>
+  <reg name="ss4"  bitsize="32" regnum="99"  group="cr"/>
+  <reg name="gcr"  bitsize="32" regnum="100" group="cr"/>
+  <reg name="gsr"  bitsize="32" regnum="101" group="cr"/>
+  <reg name="cr13" bitsize="32" regnum="102" group="cr"/>
+  <reg name="cr14" bitsize="32" regnum="103" group="cr"/>
+  <reg name="cr15" bitsize="32" regnum="104" group="cr"/>
+  <reg name="cr16" bitsize="32" regnum="105" group="cr"/>
+  <reg name="cr17" bitsize="32" regnum="106" group="cr"/>
+  <reg name="cr18" bitsize="32" regnum="107" group="cr"/>
+  <reg name="cr19" bitsize="32" regnum="108" group="cr"/>
+  <reg name="cr20" bitsize="32" regnum="109" group="cr"/>
+  <reg name="cr21" bitsize="32" regnum="110" group="cr"/>
+  <reg name="cr22" bitsize="32" regnum="111" group="cr"/>
+  <reg name="cr23" bitsize="32" regnum="112" group="cr"/>
+  <reg name="cr24" bitsize="32" regnum="113" group="cr"/>
+  <reg name="cr25" bitsize="32" regnum="114" group="cr"/>
+  <reg name="cr26" bitsize="32" regnum="115" group="cr"/>
+  <reg name="cr27" bitsize="32" regnum="116" group="cr"/>
+  <reg name="cr28" bitsize="32" regnum="117" group="cr"/>
+  <reg name="cr29" bitsize="32" regnum="118" group="cr"/>
+  <reg name="cr30" bitsize="32" regnum="119" group="cr"/>
+  <reg name="cr31" bitsize="32" regnum="120" group="cr"/>
+  <reg name="fcr"  bitsize="32" regnum="121" group="fvcr"/>
+  <reg name="fid"  bitsize="32" regnum="122" group="fvcr"/>
+  <reg name="fesr" bitsize="32" regnum="123" group="fvcr"/>
+  <!--usp cr_bank1-->
+  <reg name="usp"  bitsize="32" regnum="127"/>
+  <reg name="mcr0"  bitsize="32" regnum="128" group="mmu"/>
+  <reg name="mcr2"  bitsize="32" regnum="129" group="mmu"/>
+  <reg name="mcr3"  bitsize="32" regnum="130" group="mmu"/>
+  <reg name="mcr4"  bitsize="32" regnum="131" group="mmu"/>
+  <reg name="mcr6"  bitsize="32" regnum="132" group="mmu"/>
+  <reg name="mcr8"  bitsize="32" regnum="133" group="mmu"/>
+  <reg name="mcr29" bitsize="32" regnum="134" group="mmu"/>
+  <reg name="mcr30" bitsize="32" regnum="135" group="mmu"/>
+  <reg name="mcr31" bitsize="32" regnum="136" group="mmu"/>
+</feature>