Adjust format

src/hotspot/cpu/aarch64/vm_version_aarch64.hpp

@@ -199,6 +199,8 @@ enum Ampere_CPU_Model {
 
   constexpr static bool supports_secondary_supers_table() { return true; }
 
+  constexpr static bool supports_misaligned_vector_accesses() { return true; }
+
   static void get_compatible_board(char *buf, int buflen);
 
   static const SpinWait& spin_wait_desc() { return _spin_wait; }

src/hotspot/cpu/ppc/vm_version_ppc.hpp

@@ -64,6 +64,7 @@ public:
   constexpr static bool supports_stack_watermark_barrier() { return true; }
   constexpr static bool supports_recursive_lightweight_locking() { return true; }
   constexpr static bool supports_secondary_supers_table() { return true; }
+  constexpr static bool supports_misaligned_vector_accesses() { return true; }
 
   static bool supports_float16() { return PowerArchitecturePPC64 >= 9; }
 

src/hotspot/cpu/riscv/vm_version_riscv.cpp

@@ -24,9 +24,14 @@
  *
  */
 
+#include "asm/macroAssembler.hpp"
+#include "asm/macroAssembler.inline.hpp"
 #include "classfile/vmIntrinsics.hpp"
+#include "code/codeBlob.hpp"
+#include "memory/resourceArea.hpp"
 #include "runtime/java.hpp"
 #include "runtime/os.inline.hpp"
+#include "runtime/stubCodeGenerator.hpp"
 #include "runtime/vm_version.hpp"
 #include "utilities/formatBuffer.hpp"
 #include "utilities/macros.hpp"
@@ -34,6 +39,57 @@
 #include <ctype.h>
 
 uint32_t VM_Version::_initial_vector_length = 0;
+address VM_Version::_misaligned_vector_fault_pc1 = nullptr;
+address VM_Version::_misaligned_vector_fault_pc2 = nullptr;
+address VM_Version::_misaligned_vector_continuation_pc = nullptr;
+short short_array[4] = { 0, 0, 0, 0 };
+
+static BufferBlob* stub_blob;
+static const int stub_size = 256;
+
+extern "C" {
+  typedef int (*detect_misaligned_vector_stub_t)();
+}
+
+static detect_misaligned_vector_stub_t detect_misaligned_vector_stub = nullptr;
+
+
+class VM_Version_StubGenerator: public StubCodeGenerator {
+ public:
+
+  VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
+  ~VM_Version_StubGenerator() {}
+
+  address generate_detect_misaligned_vector(address* fault_pc1, address* fault_pc2, address* continuation_pc) {
+    StubCodeMark mark(this, "VM_Version", "detect_misaligned_vector_stub");
+#   define __ _masm->
+    address start = __ pc();
+
+    __ enter();
+    __ mv(x10, zr);
+    __ la(t1, ExternalAddress((address) short_array));
+    __ addi(t1, t1, 1);   // Misaligned address
+    __ vsetivli(x0, 1, Assembler::e16);
+    __ vmv_s_x(v2, zr);
+
+    __ addi(t2, zr, 1);
+    __ vmv_s_x(v1, t2);
+    *fault_pc1 = __ pc();
+    __ vse16_v(v1, t1);   // Misaligned vector store
+
+    *fault_pc2 = __ pc();
+    __ vle16_v(v2, t1);   // Misaligned vector load
+
+    *continuation_pc = __ pc();
+    __ vmv_x_s(x10, v2);
+    __ leave();
+    __ ret();
+
+#   undef __
+
+    return start;
+  }
+};
 
 #define DEF_RV_EXT_FEATURE(PRETTY, LINUX_BIT, FSTRING, FLAGF) \
 VM_Version::ext_##PRETTY##RVExtFeatureValue VM_Version::ext_##PRETTY;
@@ -167,9 +223,25 @@ void VM_Version::common_initialize() {
       (unaligned_scalar.value() == MISALIGNED_SCALAR_FAST));
   }
 
-  if (FLAG_IS_DEFAULT(AlignVector)) {
-    FLAG_SET_DEFAULT(AlignVector,
-      unaligned_vector.value() != MISALIGNED_VECTOR_FAST);
+  if (UseRVV) {
+    // The hwprobe syscall won't be able to detect support for misaligned vector accesses on old kernels.
+    // Resort to detect_misaligned_vector_support() to see if misaligned vector accesses may trap or not.
+    if (!unaligned_vector.enabled()) {
+      if (AlignVector == false && !VM_Version::detect_misaligned_vector_support()) {
+        warning("Misaligned vector accesses are not supported on this CPU");
+        FLAG_SET_DEFAULT(AlignVector, true);
+      }
+    } else {
+      if (FLAG_IS_DEFAULT(AlignVector)) {
+        FLAG_SET_DEFAULT(AlignVector,
+          unaligned_vector.value() != MISALIGNED_VECTOR_FAST);
+      } else if (AlignVector == false) {
+        if (unaligned_vector.value() != MISALIGNED_VECTOR_FAST) {
+          warning("Misaligned vector accesses are not supported on this CPU");
+          FLAG_SET_DEFAULT(AlignVector, true);
+        }
+      }
+    }
   }
 
 #ifdef __riscv_ztso
@@ -481,3 +553,22 @@ bool VM_Version::is_intrinsic_supported(vmIntrinsicID id) {
   }
   return true;
 }
+
+bool VM_Version::detect_misaligned_vector_support() {
+  ResourceMark rm;
+
+  stub_blob = BufferBlob::create("detect_misaligned_vector_stub", stub_size);
+    if (stub_blob == nullptr) {
+      vm_exit_during_initialization("Unable to allocate detect_misaligned_vector_stub");
+    }
+
+    CodeBuffer c(stub_blob);
+    VM_Version_StubGenerator g(&c);
+    detect_misaligned_vector_stub = CAST_TO_FN_PTR(detect_misaligned_vector_stub_t,
+                                                   g.generate_detect_misaligned_vector(
+                                                   &VM_Version::_misaligned_vector_fault_pc1,
+                                                   &VM_Version::_misaligned_vector_fault_pc2,
+                                                   &VM_Version::_misaligned_vector_continuation_pc));
+
+  return detect_misaligned_vector_stub() == 1;
+}

src/hotspot/cpu/riscv/vm_version_riscv.hpp

@@ -502,6 +502,21 @@ private:
 
   constexpr static bool supports_secondary_supers_table() { return true; }
 
+  static bool supports_misaligned_vector_accesses() { return !AlignVector; }
+
+  static bool is_misaligned_vector_fault(address pc) {
+    return pc != nullptr && (pc == _misaligned_vector_fault_pc1 || pc == _misaligned_vector_fault_pc2);
+  }
+
+  static address continuation_for_misaligned_vector_fault(address pc) {
+    assert(_misaligned_vector_continuation_pc != nullptr , "not initialized");
+    return _misaligned_vector_continuation_pc;
+  }
+
+  static address _misaligned_vector_fault_pc1;
+  static address _misaligned_vector_fault_pc2;
+  static address _misaligned_vector_continuation_pc;
+
   static bool supports_on_spin_wait() { return UseZihintpause; }
 
   // RISCV64 supports fast class initialization checks
@@ -514,6 +529,9 @@ private:
 
   // Check intrinsic support
   static bool is_intrinsic_supported(vmIntrinsicID id);
+
+  // Detect misaligned vector support
+  static bool detect_misaligned_vector_support();
 };
 
 #endif // CPU_RISCV_VM_VERSION_RISCV_HPP

src/hotspot/cpu/s390/vm_version_s390.hpp

@@ -425,6 +425,8 @@ class VM_Version: public Abstract_VM_Version {
 
   constexpr static bool supports_secondary_supers_table() { return true; }
 
+  constexpr static bool supports_misaligned_vector_accesses() { return true; }
+
   constexpr static bool supports_recursive_lightweight_locking() { return true; }
 
   // CPU feature query functions

src/hotspot/cpu/x86/vm_version_x86.hpp

@@ -991,6 +991,10 @@ public:
     return true;
   }
 
+  constexpr static bool supports_misaligned_vector_accesses() {
+    return true;
+  }
+
   constexpr static bool supports_stack_watermark_barrier() {
     return true;
   }

src/hotspot/os_cpu/linux_riscv/os_linux_riscv.cpp

@@ -287,6 +287,11 @@ bool PosixSignals::pd_hotspot_signal_handler(int sig, siginfo_t* info,
         stub = addr_slow;
       }
     }
+
+    if (sig == SIGBUS && VM_Version::is_misaligned_vector_fault(pc)) {
+      os::Posix::ucontext_set_pc(uc, VM_Version::continuation_for_misaligned_vector_fault(pc));
+      return true;
+    }
   }
 
   if (stub != nullptr) {

src/hotspot/share/classfile/modules.cpp

@@ -456,7 +456,7 @@ void Modules::define_module(Handle module, jboolean is_open, jstring version,
 #if COMPILER2_OR_JVMCI
   // Special handling of jdk.incubator.vector
   if (strcmp(module_name, "jdk.incubator.vector") == 0) {
-    if (FLAG_IS_DEFAULT(EnableVectorSupport)) {
+    if (FLAG_IS_DEFAULT(EnableVectorSupport) && VM_Version::supports_misaligned_vector_accesses()) {
       FLAG_SET_DEFAULT(EnableVectorSupport, true);
     }
     if (EnableVectorSupport && FLAG_IS_DEFAULT(EnableVectorReboxing)) {

src/hotspot/share/runtime/abstract_vm_version.hpp

@@ -197,6 +197,9 @@ class Abstract_VM_Version: AllStatic {
   // Does platform support secondary supers table lookup?
   constexpr static bool supports_secondary_supers_table() { return false; }
 
+  // Does platform support misaligned vector accesses?
+  constexpr static bool supports_misaligned_vector_accesses() { return false; }
+
   // Does platform support float16 instructions?
   static bool supports_float16() { return false; }
 

test/hotspot/jtreg/compiler/rangechecks/TestRangeCheckHoistingScaledIV.java

@@ -30,6 +30,7 @@
  * @requires vm.flagless
  * @requires vm.debug & vm.compiler2.enabled
  * @requires os.simpleArch == "x64" | os.arch == "aarch64" | (os.arch == "riscv64" & vm.cpu.features ~= ".*rvv.*")
+ * @requires vm.opt.EnableVectorSupport == true
  * @modules jdk.incubator.vector
  * @run main/othervm compiler.rangechecks.TestRangeCheckHoistingScaledIV
  */

test/hotspot/jtreg/compiler/vectorapi/TestVectorAddMulReduction.java

@@ -41,6 +41,7 @@ import jdk.test.lib.Utils;
  * @library /test/lib /
  * @summary Verify non-strictly ordered AddReductionVF/VD and MulReductionVF/VD
  *          nodes are generated in VectorAPI
+ * @requires vm.opt.EnableVectorSupport == true
  * @modules jdk.incubator.vector
  * @run driver compiler.vectorapi.TestVectorAddMulReduction
  */

test/hotspot/jtreg/compiler/vectorapi/TestVectorTest.java

@@ -36,6 +36,7 @@ import jdk.incubator.vector.VectorMask;
  * @requires (os.simpleArch == "x64" & vm.cpu.features ~= ".*sse4.*" & (vm.opt.UseSSE == "null" | vm.opt.UseSSE > 3))
  *           | os.arch == "aarch64"
  *           | (os.arch == "riscv64" & vm.cpu.features ~= ".*rvv.*")
+ * @requires vm.opt.EnableVectorSupport == true
  * @run driver compiler.vectorapi.TestVectorTest
  */
 public class TestVectorTest {

test/hotspot/jtreg/compiler/vectorapi/VectorCommutativeOperSharingTest.java

@@ -35,6 +35,7 @@ import jdk.test.lib.Utils;
  * @key randomness
  * @library /test/lib /
  * @summary Promote vector IR node sharing
+ * @requires vm.opt.EnableVectorSupport == true
  * @modules jdk.incubator.vector
  *
  * @run driver compiler.vectorapi.VectorCommutativeOperSharingTest

test/hotspot/jtreg/compiler/vectorapi/VectorExpandTest.java

@@ -34,6 +34,7 @@ import jdk.test.lib.Asserts;
  * @key randomness
  * @library /test/lib /
  * @summary AArch64: Add missing backend support of VectorAPI expand operation
+ * @requires vm.opt.EnableVectorSupport == true
  * @modules jdk.incubator.vector
  *
  * @run driver compiler.vectorapi.VectorExpandTest

test/hotspot/jtreg/compiler/vectorapi/VectorFusedMultiplyAddSubTest.java

@@ -48,6 +48,7 @@ import jdk.test.lib.Utils;
  * @key randomness
  * @library /test/lib /
  * @requires vm.cpu.features ~= ".*sve.*" | vm.cpu.features ~= ".*rvv.*"
+ * @requires vm.opt.EnableVectorSupport == true
  * @summary Add optimized rules for masked vector multiply-add/sub for SVE and RVV
  * @modules jdk.incubator.vector
  *

test/hotspot/jtreg/compiler/vectorapi/VectorMaskCompareNotTest.java

@@ -36,6 +36,7 @@ import jdk.test.lib.Asserts;
  * @summary test combining vector not operation with compare
  * @modules jdk.incubator.vector
  * @requires vm.opt.final.MaxVectorSize == "null" | vm.opt.final.MaxVectorSize >= 16
+ * @requires vm.opt.EnableVectorSupport == true
  *
  * @run driver compiler.vectorapi.VectorMaskCompareNotTest
  */

test/hotspot/jtreg/compiler/vectorapi/VectorMaskFromLongTest.java

@@ -26,6 +26,7 @@
 * @bug 8356760 8367391
 * @library /test/lib /
 * @summary Optimize VectorMask.fromLong for all-true/all-false cases
+* @requires vm.opt.EnableVectorSupport == true
 * @modules jdk.incubator.vector
 *
 * @run driver compiler.vectorapi.VectorMaskFromLongTest

test/hotspot/jtreg/compiler/vectorapi/VectorMaskLaneIsSetTest.java

@@ -33,6 +33,7 @@ import jdk.test.lib.Asserts;
  * @key randomness
  * @library /test/lib /
  * @summary VectorAPI: Re-intrinsify VectorMask.laneIsSet where the input index is a variable
+ * @requires vm.opt.EnableVectorSupport == true
  * @modules jdk.incubator.vector
  *
  * @run driver compiler.vectorapi.VectorMaskLaneIsSetTest

test/hotspot/jtreg/compiler/vectorapi/VectorMaskToLongTest.java

@@ -26,6 +26,7 @@
 * @bug 8356760
 * @library /test/lib /
 * @summary Optimize VectorMask.fromLong for all-true/all-false cases
+* @requires vm.opt.EnableVectorSupport == true
 * @modules jdk.incubator.vector
 *
 * @run driver compiler.vectorapi.VectorMaskToLongTest

test/hotspot/jtreg/compiler/vectorapi/VectorSaturatedOperationsTest.java

@@ -25,6 +25,7 @@
 * @test
 * @bug 8338021 8342677 8349522
 * @summary Add IR validation tests for newly added saturated vector add / sub operations
+* @requires vm.opt.EnableVectorSupport == true
 * @modules jdk.incubator.vector
 * @library /test/lib /
 * @run driver compiler.vectorapi.VectorSaturatedOperationsTest

test/hotspot/jtreg/compiler/vectorapi/VectorUnsignedMinMaxOperationsTest.java

@@ -25,6 +25,7 @@
 * @test
 * @bug 8342676
 * @summary Unsigned Vector Min / Max transforms
+* @requires vm.opt.EnableVectorSupport == true
 * @modules jdk.incubator.vector
 * @library /test/lib /
 * @run driver compiler.vectorapi.VectorUnsignedMinMaxOperationsTest

test/hotspot/jtreg/compiler/vectorapi/reshape/TestVectorCastRVV.java

@@ -35,6 +35,7 @@ import compiler.vectorapi.reshape.utils.VectorReshapeHelper;
  * @modules java.base/jdk.internal.misc
  * @summary Test that vector cast intrinsics work as intended on riscv (rvv).
  * @requires os.arch == "riscv64" & vm.cpu.features ~= ".*rvv.*"
+ * @requires vm.opt.EnableVectorSupport == true
  * @library /test/lib /
  * @run main/timeout=300 compiler.vectorapi.reshape.TestVectorCastRVV
  */

test/hotspot/jtreg/compiler/vectorapi/reshape/TestVectorReinterpret.java

@@ -40,6 +40,7 @@ import jdk.incubator.vector.VectorSpecies;
  * @modules java.base/jdk.internal.misc
  * @summary Test that vector reinterpret intrinsics work as intended.
  * @requires os.arch != "riscv64" | vm.cpu.features ~= ".*rvv.*"
+ * @requires vm.opt.EnableVectorSupport == true
  * @library /test/lib /
  * @run main compiler.vectorapi.reshape.TestVectorReinterpret
  */