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52 lines
1.3 KiB
Diff
52 lines
1.3 KiB
Diff
From 1cb69d9dd96ac8e315e1cf97e3f4c282cd2e6de1 Mon Sep 17 00:00:00 2001
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From: Chao Liu <chao.liu.riscv@isrc.iscas.ac.cn>
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Date: Mon, 5 Jan 2026 22:23:15 +0800
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Subject: [PATCH 6/6] target/riscv: update satp_mode to SV48 for rvsp-ref
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Signed-off-by: Chao Liu <chao.liu.riscv@isrc.iscas.ac.cn>
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---
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target/riscv/cpu.c | 15 ++++++++++++++-
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1 file changed, 14 insertions(+), 1 deletion(-)
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diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
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index 3ddb249970..f62c4f1a8e 100644
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--- a/target/riscv/cpu.c
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+++ b/target/riscv/cpu.c
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@@ -2182,11 +2182,24 @@ static RISCVCPUProfile RVA23S64 = {
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}
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};
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+static RISCVCPUProfile RVSP_RVA23S64 = {
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+ .u_parent = &RVA23S64,
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+ .s_parent = NULL,
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+ .name = "rvsp-rva23s64",
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+ .misa_ext = 0,
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+ .priv_spec = RISCV_PROFILE_ATTR_UNUSED,
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+ .satp_mode = VM_1_10_SV48,
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+ .ext_offsets = {
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+ RISCV_PROFILE_EXT_LIST_END
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+ }
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+};
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+
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RISCVCPUProfile *riscv_profiles[] = {
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&RVA22U64,
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&RVA22S64,
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&RVA23U64,
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&RVA23S64,
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+ &RVSP_RVA23S64,
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NULL,
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};
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@@ -3307,7 +3320,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
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DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RVSP_REF, TYPE_RISCV_BARE_CPU,
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.misa_mxl_max = MXL_RV64,
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- .profile = &RVA23S64,
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+ .profile = &RVSP_RVA23S64,
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/*
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* ISA extensions
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--
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2.52.0
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