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10 Commits
d7db0dff01 ... 892445a035

Author SHA1 Message Date
Ran Wang
892445a035 configs: Add new defconfig for case of large rootfs 
Signed-off-by: Ran Wang <wangran@bosc.ac.cn>
 2025-08-18 15:51:13 +08:00
zhangzhijie
a278f10405 NanHu-V5 DTS: Add PLIC And XDMA(pcie) 
1. default status is disabled
2. PLIC interrupt-extended dispatch to each dts

Signed-off-by: zhangzhijie <zhangzhijie@bosc.ac.cn>
 2025-08-14 15:57:32 +08:00
zhangzhijie
f4247862d2 Support Pcie , Default is disable 
Signed-off-by: zhangzhijie <zhangzhijie@bosc.ac.cn>
 2025-08-08 11:30:25 +08:00
Yaxing Guo
d6328edc03 dts: kvm-v2: Add no-imsic-ipi in imsic_s node 
There is a hardware issue of losing IPI interrupt when using imsic ipi.
Add this quir property to use clint IPI instead.

Signed-off-by: Yaxing Guo <guoyaxing@bosc.ac.cn>
 2025-08-06 12:05:31 +08:00
Yaxing Guo
8dcb5db893 irqchip: riscv-imsic: Add no-imisc-ipi quirk property 
To control whether to use imsic ipi.

Context is that kmh-v2 have known issue that the path from imisic IPI
to CPU might not work sometimes. And the workaround is to use clint IPI
instead.

Signed-off-by: Yaxing Guo <guoyaxing@bosc.ac.cn>
 2025-08-06 11:25:58 +08:00
Ran Wang
8759fda167 minimal_defconfigs: Select debug options 
Signed-off-by: Ran Wang <wangran@bosc.ac.cn>
 2025-08-05 13:55:54 +08:00
gaochengbo
742d223e56 dts: kmh-v2: Fix warning of "riscv-imsic@3b000000: invalid cpuid for parent irq4" 
Move interrupts-extended from dtsi to dts files.

Signed-off-by: Chengbo Gao <gaochengbo@bosc.ac.cn>
 2025-08-04 15:50:50 +08:00
Anzooooo
3368ca3299 dts: kmh-v2: Add cbo-block-size 2025-07-24 09:15:19 +00:00
Ran Wang
7ab90af048 dts: nanhu-v5: Add multiple cpu platforms 
Signed-off-by: Ran Wang <wangran@bosc.ac.cn>
 2025-07-22 14:00:09 +08:00
Ran Wang
d6822ff65b minimal_defconfig: Add CONFIG_POSIX_TIMERS for stress-ng 
Otherwise stress-ng will not return when timerout.

Signed-off-by: Ran Wang <wangran@bosc.ac.cn>
 2025-07-18 18:28:16 +08:00
26 changed files with 1571 additions and 66 deletions
Expand all files Collapse all files

10
arch/riscv/boot/dts/bosc/Makefile
View File

@@ -23,6 +23,14 @@ dtb-$(CONFIG_SOC_XIANGSHAN) += \
kmh-v2-16core-uartlite.dtb \
kmh-v2-nemu.dtb \
nanhu-v5-1core.dtb \
nanhu-v5-1core-uartlite.dtb
nanhu-v5-2core.dtb \
nanhu-v5-4core.dtb \
nanhu-v5-8core.dtb \
nanhu-v5-16core.dtb \
nanhu-v5-1core-uartlite.dtb \
nanhu-v5-2core-uartlite.dtb \
nanhu-v5-4core-uartlite.dtb \
nanhu-v5-8core-uartlite.dtb \
nanhu-v5-16core-uartlite.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

60
arch/riscv/boot/dts/bosc/kmh-v2-16core-uartlite.dts
View File

@@ -86,3 +86,63 @@
&cpu15 {
status = "okay";
};
&clint {
interrupts-extended =
<&intc_cpu0 3>, <&intc_cpu0 7>,
<&intc_cpu1 3>, <&intc_cpu1 7>,
<&intc_cpu2 3>, <&intc_cpu2 7>,
<&intc_cpu3 3>, <&intc_cpu3 7>,
<&intc_cpu4 3>, <&intc_cpu4 7>,
<&intc_cpu5 3>, <&intc_cpu5 7>,
<&intc_cpu6 3>, <&intc_cpu6 7>,
<&intc_cpu7 3>, <&intc_cpu7 7>,
<&intc_cpu8 3>, <&intc_cpu8 7>,
<&intc_cpu9 3>, <&intc_cpu9 7>,
<&intc_cpu10 3>, <&intc_cpu10 7>,
<&intc_cpu11 3>, <&intc_cpu11 7>,
<&intc_cpu12 3>, <&intc_cpu12 7>,
<&intc_cpu13 3>, <&intc_cpu13 7>,
<&intc_cpu14 3>, <&intc_cpu14 7>,
<&intc_cpu15 3>, <&intc_cpu15 7>;
};
&imsics_m {
interrupts-extended =
<&intc_cpu0 0x0b>,
<&intc_cpu1 0x0b>,
<&intc_cpu2 0x0b>,
<&intc_cpu3 0x0b>,
<&intc_cpu4 0x0b>,
<&intc_cpu5 0x0b>,
<&intc_cpu6 0x0b>,
<&intc_cpu7 0x0b>,
<&intc_cpu8 0x0b>,
<&intc_cpu9 0x0b>,
<&intc_cpu10 0x0b>,
<&intc_cpu11 0x0b>,
<&intc_cpu12 0x0b>,
<&intc_cpu13 0x0b>,
<&intc_cpu14 0x0b>,
<&intc_cpu15 0x0b>;
};
&imsics_s {
interrupts-extended =
<&intc_cpu0 0x09>,
<&intc_cpu1 0x09>,
<&intc_cpu2 0x09>,
<&intc_cpu3 0x09>,
<&intc_cpu4 0x09>,
<&intc_cpu5 0x09>,
<&intc_cpu6 0x09>,
<&intc_cpu7 0x09>,
<&intc_cpu8 0x09>,
<&intc_cpu9 0x09>,
<&intc_cpu10 0x09>,
<&intc_cpu11 0x09>,
<&intc_cpu12 0x09>,
<&intc_cpu13 0x09>,
<&intc_cpu14 0x09>,
<&intc_cpu15 0x09>;
};

61
arch/riscv/boot/dts/bosc/kmh-v2-16core.dts
View File

@@ -91,3 +91,64 @@
&cpu15 {
status = "okay";
};
&clint {
interrupts-extended =
<&intc_cpu0 3>, <&intc_cpu0 7>,
<&intc_cpu1 3>, <&intc_cpu1 7>,
<&intc_cpu2 3>, <&intc_cpu2 7>,
<&intc_cpu3 3>, <&intc_cpu3 7>,
<&intc_cpu4 3>, <&intc_cpu4 7>,
<&intc_cpu5 3>, <&intc_cpu5 7>,
<&intc_cpu6 3>, <&intc_cpu6 7>,
<&intc_cpu7 3>, <&intc_cpu7 7>,
<&intc_cpu8 3>, <&intc_cpu8 7>,
<&intc_cpu9 3>, <&intc_cpu9 7>,
<&intc_cpu10 3>, <&intc_cpu10 7>,
<&intc_cpu11 3>, <&intc_cpu11 7>,
<&intc_cpu12 3>, <&intc_cpu12 7>,
<&intc_cpu13 3>, <&intc_cpu13 7>,
<&intc_cpu14 3>, <&intc_cpu14 7>,
<&intc_cpu15 3>, <&intc_cpu15 7>;
};
&imsics_m {
interrupts-extended =
<&intc_cpu0 0x0b>,
<&intc_cpu1 0x0b>,
<&intc_cpu2 0x0b>,
<&intc_cpu3 0x0b>,
<&intc_cpu4 0x0b>,
<&intc_cpu5 0x0b>,
<&intc_cpu6 0x0b>,
<&intc_cpu7 0x0b>,
<&intc_cpu8 0x0b>,
<&intc_cpu9 0x0b>,
<&intc_cpu10 0x0b>,
<&intc_cpu11 0x0b>,
<&intc_cpu12 0x0b>,
<&intc_cpu13 0x0b>,
<&intc_cpu14 0x0b>,
<&intc_cpu15 0x0b>;
};
&imsics_s {
interrupts-extended =
<&intc_cpu0 0x09>,
<&intc_cpu1 0x09>,
<&intc_cpu2 0x09>,
<&intc_cpu3 0x09>,
<&intc_cpu4 0x09>,
<&intc_cpu5 0x09>,
<&intc_cpu6 0x09>,
<&intc_cpu7 0x09>,
<&intc_cpu8 0x09>,
<&intc_cpu9 0x09>,
<&intc_cpu10 0x09>,
<&intc_cpu11 0x09>,
<&intc_cpu12 0x09>,
<&intc_cpu13 0x09>,
<&intc_cpu14 0x09>,
<&intc_cpu15 0x09>;
};

15
arch/riscv/boot/dts/bosc/kmh-v2-1core-uartlite.dts
View File

@@ -26,3 +26,18 @@
&uart1 {
status = "okay";
};
&clint {
interrupts-extended =
<&intc_cpu0 3>, <&intc_cpu0 7>;
};
&imsics_m {
interrupts-extended =
<&intc_cpu0 0x0b>;
};
&imsics_s {
interrupts-extended =
<&intc_cpu0 0x09>;
};

15
arch/riscv/boot/dts/bosc/kmh-v2-1core.dts
View File

@@ -31,3 +31,18 @@
&uart0 {
status = "okay";
};
&clint {
interrupts-extended =
<&intc_cpu0 3>, <&intc_cpu0 7>;
};
&imsics_m {
interrupts-extended =
<&intc_cpu0 0x0b>;
};
&imsics_s {
interrupts-extended =
<&intc_cpu0 0x09>;
};

18
arch/riscv/boot/dts/bosc/kmh-v2-2core-uartlite.dts
View File

@@ -30,3 +30,21 @@
&cpu1 {
status = "okay";
};
&clint {
interrupts-extended =
<&intc_cpu0 3>, <&intc_cpu0 7>,
<&intc_cpu1 3>, <&intc_cpu1 7>;
};
&imsics_m {
interrupts-extended =
<&intc_cpu0 0x0b>,
<&intc_cpu1 0x0b>;
};
&imsics_s {
interrupts-extended =
<&intc_cpu0 0x09>,
<&intc_cpu1 0x09>;
};

19
arch/riscv/boot/dts/bosc/kmh-v2-2core.dts
View File

@@ -35,3 +35,22 @@
&uart0 {
status = "okay";
};
&clint {
interrupts-extended =
<&intc_cpu0 3>, <&intc_cpu0 7>,
<&intc_cpu1 3>, <&intc_cpu1 7>;
};
&imsics_m {
interrupts-extended =
<&intc_cpu0 0x0b>,
<&intc_cpu1 0x0b>;
};
&imsics_s {
interrupts-extended =
<&intc_cpu0 0x09>,
<&intc_cpu1 0x09>;
};

24
arch/riscv/boot/dts/bosc/kmh-v2-4core-uartlite.dts
View File

@@ -38,3 +38,27 @@
&cpu3 {
status = "okay";
};
&clint {
interrupts-extended =
<&intc_cpu0 3>, <&intc_cpu0 7>,
<&intc_cpu1 3>, <&intc_cpu1 7>,
<&intc_cpu2 3>, <&intc_cpu2 7>,
<&intc_cpu3 3>, <&intc_cpu3 7>;
};
&imsics_m {
interrupts-extended =
<&intc_cpu0 0x0b>,
<&intc_cpu1 0x0b>,
<&intc_cpu2 0x0b>,
<&intc_cpu3 0x0b>;
};
&imsics_s {
interrupts-extended =
<&intc_cpu0 0x09>,
<&intc_cpu1 0x09>,
<&intc_cpu2 0x09>,
<&intc_cpu3 0x09>;
};

24
arch/riscv/boot/dts/bosc/kmh-v2-4core.dts
View File

@@ -43,3 +43,27 @@
&cpu3 {
status = "okay";
};
&clint {
interrupts-extended =
<&intc_cpu0 3>, <&intc_cpu0 7>,
<&intc_cpu1 3>, <&intc_cpu1 7>,
<&intc_cpu2 3>, <&intc_cpu2 7>,
<&intc_cpu3 3>, <&intc_cpu3 7>;
};
&imsics_m {
interrupts-extended =
<&intc_cpu0 0x0b>,
<&intc_cpu1 0x0b>,
<&intc_cpu2 0x0b>,
<&intc_cpu3 0x0b>;
};
&imsics_s {
interrupts-extended =
<&intc_cpu0 0x09>,
<&intc_cpu1 0x09>,
<&intc_cpu2 0x09>,
<&intc_cpu3 0x09>;
};

36
arch/riscv/boot/dts/bosc/kmh-v2-8core-uartlite.dts
View File

@@ -54,3 +54,39 @@
&cpu7 {
status = "okay";
};
&clint {
interrupts-extended =
<&intc_cpu0 3>, <&intc_cpu0 7>,
<&intc_cpu1 3>, <&intc_cpu1 7>,
<&intc_cpu2 3>, <&intc_cpu2 7>,
<&intc_cpu3 3>, <&intc_cpu3 7>,
<&intc_cpu4 3>, <&intc_cpu4 7>,
<&intc_cpu5 3>, <&intc_cpu5 7>,
<&intc_cpu6 3>, <&intc_cpu6 7>,
<&intc_cpu7 3>, <&intc_cpu7 7>;
};
&imsics_m {
interrupts-extended =
<&intc_cpu0 0x0b>,
<&intc_cpu1 0x0b>,
<&intc_cpu2 0x0b>,
<&intc_cpu3 0x0b>,
<&intc_cpu4 0x0b>,
<&intc_cpu5 0x0b>,
<&intc_cpu6 0x0b>,
<&intc_cpu7 0x0b>;
};
&imsics_s {
interrupts-extended =
<&intc_cpu0 0x09>,
<&intc_cpu1 0x09>,
<&intc_cpu2 0x09>,
<&intc_cpu3 0x09>,
<&intc_cpu4 0x09>,
<&intc_cpu5 0x09>,
<&intc_cpu6 0x09>,
<&intc_cpu7 0x09>;
};

36
arch/riscv/boot/dts/bosc/kmh-v2-8core.dts
View File

@@ -59,3 +59,39 @@
&cpu7 {
status = "okay";
};
&clint {
interrupts-extended =
<&intc_cpu0 3>, <&intc_cpu0 7>,
<&intc_cpu1 3>, <&intc_cpu1 7>,
<&intc_cpu2 3>, <&intc_cpu2 7>,
<&intc_cpu3 3>, <&intc_cpu3 7>,
<&intc_cpu4 3>, <&intc_cpu4 7>,
<&intc_cpu5 3>, <&intc_cpu5 7>,
<&intc_cpu6 3>, <&intc_cpu6 7>,
<&intc_cpu7 3>, <&intc_cpu7 7>;
};
&imsics_m {
interrupts-extended =
<&intc_cpu0 0x0b>,
<&intc_cpu1 0x0b>,
<&intc_cpu2 0x0b>,
<&intc_cpu3 0x0b>,
<&intc_cpu4 0x0b>,
<&intc_cpu5 0x0b>,
<&intc_cpu6 0x0b>,
<&intc_cpu7 0x0b>;
};
&imsics_s {
interrupts-extended =
<&intc_cpu0 0x09>,
<&intc_cpu1 0x09>,
<&intc_cpu2 0x09>,
<&intc_cpu3 0x09>,
<&intc_cpu4 0x09>,
<&intc_cpu5 0x09>,
<&intc_cpu6 0x09>,
<&intc_cpu7 0x09>;
};

201
arch/riscv/boot/dts/bosc/kmh-v2.dtsi
View File

@@ -31,6 +31,8 @@
riscv,isa = "rv64imafdcvh_smaia_smstateen_sscofpmf_sstc_zicntr_zihpm_zicboz_zicbom_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smaia", "smcsrind", "smdbltrp", "smmpm", "smnpm", "smrnmi", "smstateen", "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", "zksed", "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", "zvkt", "zvl128b", "zvl32b", "zvl64b";
riscv,cbom-block-size = <0x40>;
riscv,cboz-block-size = <0x40>;
status = "disabled";
next-level-cache = <&l2_cache>;
@@ -59,6 +61,8 @@
riscv,isa = "rv64imafdcvh_smaia_smstateen_sscofpmf_sstc_zicntr_zihpm_zicboz_zicbom_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smaia", "smcsrind", "smdbltrp", "smmpm", "smnpm", "smrnmi", "smstateen", "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", "zksed", "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", "zvkt", "zvl128b", "zvl32b", "zvl64b";
riscv,cbom-block-size = <0x40>;
riscv,cboz-block-size = <0x40>;
status = "disabled";
next-level-cache = <&l2_cache>;
@@ -87,6 +91,8 @@
riscv,isa = "rv64imafdcvh_smaia_smstateen_sscofpmf_sstc_zicntr_zihpm_zicboz_zicbom_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smaia", "smcsrind", "smdbltrp", "smmpm", "smnpm", "smrnmi", "smstateen", "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", "zksed", "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", "zvkt", "zvl128b", "zvl32b", "zvl64b";
riscv,cbom-block-size = <0x40>;
riscv,cboz-block-size = <0x40>;
status = "disabled";
next-level-cache = <&l2_cache>;
@@ -115,6 +121,8 @@
riscv,isa = "rv64imafdcvh_smaia_smstateen_sscofpmf_sstc_zicntr_zihpm_zicboz_zicbom_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smaia", "smcsrind", "smdbltrp", "smmpm", "smnpm", "smrnmi", "smstateen", "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", "zksed", "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", "zvkt", "zvl128b", "zvl32b", "zvl64b";
riscv,cbom-block-size = <0x40>;
riscv,cboz-block-size = <0x40>;
status = "disabled";
next-level-cache = <&l2_cache>;
@@ -143,6 +151,8 @@
riscv,isa = "rv64imafdcvh_smaia_smstateen_sscofpmf_sstc_zicntr_zihpm_zicboz_zicbom_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smaia", "smcsrind", "smdbltrp", "smmpm", "smnpm", "smrnmi", "smstateen", "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", "zksed", "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", "zvkt", "zvl128b", "zvl32b", "zvl64b";
riscv,cbom-block-size = <0x40>;
riscv,cboz-block-size = <0x40>;
status = "disabled";
next-level-cache = <&l2_cache>;
@@ -171,6 +181,8 @@
riscv,isa = "rv64imafdcvh_smaia_smstateen_sscofpmf_sstc_zicntr_zihpm_zicboz_zicbom_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smaia", "smcsrind", "smdbltrp", "smmpm", "smnpm", "smrnmi", "smstateen", "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", "zksed", "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", "zvkt", "zvl128b", "zvl32b", "zvl64b";
riscv,cbom-block-size = <0x40>;
riscv,cboz-block-size = <0x40>;
status = "disabled";
next-level-cache = <&l2_cache>;
@@ -199,6 +211,8 @@
riscv,isa = "rv64imafdcvh_smaia_smstateen_sscofpmf_sstc_zicntr_zihpm_zicboz_zicbom_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smaia", "smcsrind", "smdbltrp", "smmpm", "smnpm", "smrnmi", "smstateen", "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", "zksed", "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", "zvkt", "zvl128b", "zvl32b", "zvl64b";
riscv,cbom-block-size = <0x40>;
riscv,cboz-block-size = <0x40>;
status = "disabled";
next-level-cache = <&l2_cache>;
@@ -227,6 +241,8 @@
riscv,isa = "rv64imafdcvh_smaia_smstateen_sscofpmf_sstc_zicntr_zihpm_zicboz_zicbom_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smaia", "smcsrind", "smdbltrp", "smmpm", "smnpm", "smrnmi", "smstateen", "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", "zksed", "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", "zvkt", "zvl128b", "zvl32b", "zvl64b";
riscv,cbom-block-size = <0x40>;
riscv,cboz-block-size = <0x40>;
status = "disabled";
next-level-cache = <&l2_cache>;
@@ -255,6 +271,8 @@
riscv,isa = "rv64imafdcvh_smaia_smstateen_sscofpmf_sstc_zicntr_zihpm_zicboz_zicbom_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smaia", "smcsrind", "smdbltrp", "smmpm", "smnpm", "smrnmi", "smstateen", "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", "zksed", "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", "zvkt", "zvl128b", "zvl32b", "zvl64b";
riscv,cbom-block-size = <0x40>;
riscv,cboz-block-size = <0x40>;
status = "disabled";
next-level-cache = <&l2_cache>;
@@ -283,6 +301,8 @@
riscv,isa = "rv64imafdcvh_smaia_smstateen_sscofpmf_sstc_zicntr_zihpm_zicboz_zicbom_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smaia", "smcsrind", "smdbltrp", "smmpm", "smnpm", "smrnmi", "smstateen", "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", "zksed", "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", "zvkt", "zvl128b", "zvl32b", "zvl64b";
riscv,cbom-block-size = <0x40>;
riscv,cboz-block-size = <0x40>;
status = "disabled";
next-level-cache = <&l2_cache>;
@@ -311,6 +331,8 @@
riscv,isa = "rv64imafdcvh_smaia_smstateen_sscofpmf_sstc_zicntr_zihpm_zicboz_zicbom_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smaia", "smcsrind", "smdbltrp", "smmpm", "smnpm", "smrnmi", "smstateen", "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", "zksed", "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", "zvkt", "zvl128b", "zvl32b", "zvl64b";
riscv,cbom-block-size = <0x40>;
riscv,cboz-block-size = <0x40>;
status = "disabled";
next-level-cache = <&l2_cache>;
@@ -339,6 +361,8 @@
riscv,isa = "rv64imafdcvh_smaia_smstateen_sscofpmf_sstc_zicntr_zihpm_zicboz_zicbom_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smaia", "smcsrind", "smdbltrp", "smmpm", "smnpm", "smrnmi", "smstateen", "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", "zksed", "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", "zvkt", "zvl128b", "zvl32b", "zvl64b";
riscv,cbom-block-size = <0x40>;
riscv,cboz-block-size = <0x40>;
status = "disabled";
next-level-cache = <&l2_cache>;
@@ -367,6 +391,8 @@
riscv,isa = "rv64imafdcvh_smaia_smstateen_sscofpmf_sstc_zicntr_zihpm_zicboz_zicbom_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smaia", "smcsrind", "smdbltrp", "smmpm", "smnpm", "smrnmi", "smstateen", "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", "zksed", "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", "zvkt", "zvl128b", "zvl32b", "zvl64b";
riscv,cbom-block-size = <0x40>;
riscv,cboz-block-size = <0x40>;
status = "disabled";
next-level-cache = <&l2_cache>;
@@ -395,6 +421,8 @@
riscv,isa = "rv64imafdcvh_smaia_smstateen_sscofpmf_sstc_zicntr_zihpm_zicboz_zicbom_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smaia", "smcsrind", "smdbltrp", "smmpm", "smnpm", "smrnmi", "smstateen", "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", "zksed", "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", "zvkt", "zvl128b", "zvl32b", "zvl64b";
riscv,cbom-block-size = <0x40>;
riscv,cboz-block-size = <0x40>;
status = "disabled";
next-level-cache = <&l2_cache>;
@@ -423,6 +451,8 @@
riscv,isa = "rv64imafdcvh_smaia_smstateen_sscofpmf_sstc_zicntr_zihpm_zicboz_zicbom_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smaia", "smcsrind", "smdbltrp", "smmpm", "smnpm", "smrnmi", "smstateen", "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", "zksed", "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", "zvkt", "zvl128b", "zvl32b", "zvl64b";
riscv,cbom-block-size = <0x40>;
riscv,cboz-block-size = <0x40>;
status = "disabled";
next-level-cache = <&l2_cache>;
@@ -451,6 +481,8 @@
riscv,isa = "rv64imafdcvh_smaia_smstateen_sscofpmf_sstc_zicntr_zihpm_zicboz_zicbom_svpbmt_sdtrig_smcsrind_sscsrind_svade";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "h", "sdtrig", "sha", "shcounterenw", "shgatpa", "shlcofideleg", "shtvala", "shvsatpa", "shvstvala", "shvstvecd", "smaia", "smcsrind", "smdbltrp", "smmpm", "smnpm", "smrnmi", "smstateen", "ss1p13", "ssaia", "ssccptr", "sscofpmf", "sscounterenw", "sscsrind", "ssdbltrp", "ssnpm", "sspm", "ssstateen", "ssstrict", "sstc", "sstvala", "sstvecd", "ssu64xl", "supm", "sv39", "sv48", "svade", "svbare", "svinval", "svnapot", "svpbmt", "za64rs", "zacas", "zawrs", "zba", "zbb", "zbc", "zbkb", "zbkc", "zbkx", "zbs", "zcb", "zcmop", "zfa", "zfh", "zfhmin", "zic64b", "zicbom", "zicbop", "zicboz", "ziccamoa", "ziccif", "zicclsm", "ziccrse", "zicntr", "zicond", "zicsr", "zifencei", "zihintntl", "zihintpause", "zihpm", "zimop", "zkn", "zknd", "zkne", "zknh", "zksed", "zksh", "zkt", "zvbb", "zvfh", "zvfhmin", "zvkt", "zvl128b", "zvl32b", "zvl64b";
riscv,cbom-block-size = <0x40>;
riscv,cboz-block-size = <0x40>;
status = "disabled";
next-level-cache = <&l2_cache>;
@@ -480,45 +512,11 @@
clint: timer@38000000 {
compatible = "riscv,clint0";
reg = <0x0 0x38000000 0x0 0x10000>;
interrupts-extended =
<&intc_cpu0 3>, <&intc_cpu0 7>,
<&intc_cpu1 3>, <&intc_cpu1 7>,
<&intc_cpu2 3>, <&intc_cpu2 7>,
<&intc_cpu3 3>, <&intc_cpu3 7>,
<&intc_cpu4 3>, <&intc_cpu4 7>,
<&intc_cpu5 3>, <&intc_cpu5 7>,
<&intc_cpu6 3>, <&intc_cpu6 7>,
<&intc_cpu7 3>, <&intc_cpu7 7>,
<&intc_cpu8 3>, <&intc_cpu8 7>,
<&intc_cpu9 3>, <&intc_cpu9 7>,
<&intc_cpu10 3>, <&intc_cpu10 7>,
<&intc_cpu11 3>, <&intc_cpu11 7>,
<&intc_cpu12 3>, <&intc_cpu12 7>,
<&intc_cpu13 3>, <&intc_cpu13 7>,
<&intc_cpu14 3>, <&intc_cpu14 7>,
<&intc_cpu15 3>, <&intc_cpu15 7>;
};
imsics_m: imsics@3a800000 {
riscv,num-ids = <0xff>;
reg = <0x0 0x3a800000 0x0 0x10000>;
interrupts-extended =
<&intc_cpu0 0x0b>,
<&intc_cpu1 0x0b>,
<&intc_cpu2 0x0b>,
<&intc_cpu3 0x0b>,
<&intc_cpu4 0x0b>,
<&intc_cpu5 0x0b>,
<&intc_cpu6 0x0b>,
<&intc_cpu7 0x0b>,
<&intc_cpu8 0x0b>,
<&intc_cpu9 0x0b>,
<&intc_cpu10 0x0b>,
<&intc_cpu11 0x0b>,
<&intc_cpu12 0x0b>,
<&intc_cpu13 0x0b>,
<&intc_cpu14 0x0b>,
<&intc_cpu15 0x0b>;
msi-controller;
interrupt-controller;
#interrupt-cells = <0x00>;
@@ -528,28 +526,12 @@
imsics_s: imsics@3b000000 {
riscv,num-ids = <0xff>;
reg = <0x0 0x3b000000 0x0 0x80000>;
interrupts-extended =
<&intc_cpu0 0x09>,
<&intc_cpu1 0x09>,
<&intc_cpu2 0x09>,
<&intc_cpu3 0x09>,
<&intc_cpu4 0x09>,
<&intc_cpu5 0x09>,
<&intc_cpu6 0x09>,
<&intc_cpu7 0x09>,
<&intc_cpu8 0x09>,
<&intc_cpu9 0x09>,
<&intc_cpu10 0x09>,
<&intc_cpu11 0x09>,
<&intc_cpu12 0x09>,
<&intc_cpu13 0x09>,
<&intc_cpu14 0x09>,
<&intc_cpu15 0x09>;
msi-controller;
interrupt-controller;
#interrupt-cells = <0x00>;
compatible = "riscv,imsics";
riscv,guest-index-bits = <0x03>;
no-imsic-ipi;
};
aplic_s: aplic@31120000 {
@@ -589,6 +571,123 @@
reg-names = "control";
status = "disabled";
};
synps_pcie0: pcie_synps@48000000 {
compatible = "snps,dw-pcie";
reg = <0x0 0x48000000 0x0 0x8000000>,
<0x0 0x6fff0000 0x0 0x0010000>;
reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges = <0x02000000 0x00000000 0x40000000 0x00000000 0x60000000 0x00000000 0xfff0000>,
<0x03000000 0x00000040 0x00000000 0x00000040 0x00000000 0x00000002 0x0000000>;
num-ib-windows = <1>;
dma-ranges = <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x80000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0x0 0 0 7>;
interrupt-parent = <&aplic_s>;
msi-parent = <&imsics_s>;
interrupts = <12 IRQ_TYPE_EDGE_RISING>, <13 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "msi", "hp";
num-lanes = <1>;
status = "disabled";
};
synps_pcie1: pcie_synps@50000000 {
compatible = "snps,dw-pcie";
reg = <0x0 0x50000000 0x0 0x00080000>,
<0x0 0x7fff0000 0x0 0x0010000>;
reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges = <0x02000000 0x00000000 0x40000000 0x00000000 0x70000000 0x00000000 0xfff0000>,
<0x03000000 0x00000060 0x00000000 0x00000060 0x00000000 0x0000002 0x0>;
num-ib-windows = <1>;
dma-ranges = <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x80000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0x0 0 0 7>;
interrupt-parent = <&aplic_s>;
msi-parent = <&imsics_s>;
interrupts = <15 IRQ_TYPE_EDGE_RISING>, <16 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "msi", "hp";
num-lanes = <1>;
status = "disabled";
};
xdma_clkc: misc_clk_0 {
#clock-cells = <0>;
clock-frequency = <10000000>;
compatible = "fixed-clock";
};
xdma_0: pcie_xdma@48000000 {
#address-cells = <3>;
#interrupt-cells = <1>;
#size-cells = <2>;
clock-names = "sys_clk", "sys_clk_gt";
clocks = <&xdma_clkc>, <&xdma_clkc>;
compatible = "xlnx,xdma-host-3.00", "xlnx,axi-pcie-host-1.00.a";
device_type = "pci";
interrupt-map = <0x0 0 0 1 &pcie_intc_0 1>,
<0x0 0 0 2 &pcie_intc_0 2>,
<0x0 0 0 3 &pcie_intc_0 3>,
<0x0 0 0 4 &pcie_intc_0 4>;
interrupt-map-mask = <0x0 0 0 7>;
interrupt-names = "misc", "msi0", "msi1";
interrupt-parent = <&aplic_s>;
interrupts = <14 IRQ_TYPE_EDGE_RISING>, <13 IRQ_TYPE_EDGE_RISING>, <12 IRQ_TYPE_EDGE_RISING>;
msi-parent = <&imsics_s>;
bus-range = <0x00 0xff>;
ranges = <0x02000000 0x0000000 0x60000000 0x00000000 0x60000000 0x0000000 0x10000000>, // MEM resource Bit32
<0x03000000 0x00000040 0x00000000 0x00000040 0x00000000 0x0000020 0x00000000>; // MEM resrouce Bit64 Prefetch
reg = <0x00000000 0x48000000 0x0 0x8000000>;
status = "disabled";
pcie_intc_0: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller ;
};
};
xdma_1: pcie_xdma@50000000 {
#address-cells = <3>;
#interrupt-cells = <1>;
#size-cells = <2>;
clock-names = "sys_clk", "sys_clk_gt";
clocks = <&xdma_clkc>, <&xdma_clkc>;
compatible = "xlnx,xdma-host-3.00", "xlnx,axi-pcie-host-1.00.a";
device_type = "pci";
interrupt-map = <0x0 0 0 1 &pcie_intc_1 1>,
<0x0 0 0 2 &pcie_intc_1 2>,
<0x0 0 0 3 &pcie_intc_1 3>,
<0x0 0 0 4 &pcie_intc_1 4>;
interrupt-map-mask = <0x0 0 0 7>;
interrupt-names = "misc", "msi0", "msi1";
interrupt-parent = <&aplic_s>;
interrupts = <17 IRQ_TYPE_EDGE_RISING>, <16 IRQ_TYPE_EDGE_RISING>, <15 IRQ_TYPE_EDGE_RISING>;
msi-parent = <&imsics_s>;
bus-range = <0x00 0xff>;
ranges = <0x02000000 0x0000000 0x70000000 0x00000000 0x70000000 0x0000000 0x10000000>, // MEM resource Bit32
<0x03000000 0x00000060 0x00000000 0x00000060 0x00000000 0x0000020 0x00000000>; // MEM resrouce Bit64 Prefetch
reg = <0x00000000 0x50000000 0x0 0x10000000>;
status = "disabled";
pcie_intc_1: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller ;
};
};
};
chosen {

117
arch/riscv/boot/dts/bosc/nanhu-v5-16core-uartlite.dts Normal file
View File

@@ -0,0 +1,117 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2025 BOSC */
/dts-v1/;
#include "nanhu-v5.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "bosc,nanhu-v5-dev";
model = "bosc,nanhu-v5-16core-uartlite";
chosen {
bootargs = "console=hvc0 earlycon=sbi loglevel=8";
opensbi-config {
compatible = "opensbi,config";
cold-boot-harts = <&cpu0>;
};
};
};
&uart1 {
status = "okay";
};
&cpu0 {
status = "okay";
};
&cpu1 {
status = "okay";
};
&cpu2 {
status = "okay";
};
&cpu3 {
status = "okay";
};
&cpu4 {
status = "okay";
};
&cpu5 {
status = "okay";
};
&cpu6 {
status = "okay";
};
&cpu7 {
status = "okay";
};
&cpu8 {
status = "okay";
};
&cpu9 {
status = "okay";
};
&cpu10 {
status = "okay";
};
&cpu11 {
status = "okay";
};
&cpu12 {
status = "okay";
};
&cpu13 {
status = "okay";
};
&cpu14 {
status = "okay";
};
&cpu15 {
status = "okay";
};
&PLIC {
interrupts-extended =
<&intc_cpu0 0xb>, <&intc_cpu0 9>,
<&intc_cpu1 0xb>, <&intc_cpu1 9>,
<&intc_cpu2 0xb>, <&intc_cpu2 9>,
<&intc_cpu3 0xb>, <&intc_cpu3 9>,
<&intc_cpu4 0xb>, <&intc_cpu4 9>,
<&intc_cpu5 0xb>, <&intc_cpu5 9>,
<&intc_cpu6 0xb>, <&intc_cpu6 9>,
<&intc_cpu7 0xb>, <&intc_cpu7 9>,
<&intc_cpu8 0xb>, <&intc_cpu8 9>,
<&intc_cpu9 0xb>, <&intc_cpu9 9>,
<&intc_cpu10 0xb>, <&intc_cpu10 9>,
<&intc_cpu11 0xb>, <&intc_cpu11 9>,
<&intc_cpu12 0xb>, <&intc_cpu12 9>,
<&intc_cpu13 0xb>, <&intc_cpu13 9>,
<&intc_cpu14 0xb>, <&intc_cpu14 9>,
<&intc_cpu15 0xb>, <&intc_cpu15 9>;
};
&xdma_0 {
status = "disabled";
};
&xdma_1 {
status = "disabled";
};

117
arch/riscv/boot/dts/bosc/nanhu-v5-16core.dts Normal file
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@@ -0,0 +1,117 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2025 BOSC */
/dts-v1/;
#include "nanhu-v5.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "bosc,nanhu-v5-dev";
model = "bosc,nanhu-v5-16core";
chosen {
bootargs = "console=hvc0 earlycon=sbi loglevel=8";
opensbi-config {
compatible = "opensbi,config";
cold-boot-harts = <&cpu0>;
};
};
};
&cpu0 {
status = "okay";
};
&cpu1 {
status = "okay";
};
&cpu2 {
status = "okay";
};
&cpu3 {
status = "okay";
};
&cpu4 {
status = "okay";
};
&cpu5 {
status = "okay";
};
&cpu6 {
status = "okay";
};
&cpu7 {
status = "okay";
};
&cpu8 {
status = "okay";
};
&cpu9 {
status = "okay";
};
&cpu10 {
status = "okay";
};
&cpu11 {
status = "okay";
};
&cpu12 {
status = "okay";
};
&cpu13 {
status = "okay";
};
&cpu14 {
status = "okay";
};
&cpu15 {
status = "okay";
};
&uart0 {
status = "okay";
};
&PLIC {
interrupts-extended =
<&intc_cpu0 0xb>, <&intc_cpu0 9>,
<&intc_cpu1 0xb>, <&intc_cpu1 9>,
<&intc_cpu2 0xb>, <&intc_cpu2 9>,
<&intc_cpu3 0xb>, <&intc_cpu3 9>,
<&intc_cpu4 0xb>, <&intc_cpu4 9>,
<&intc_cpu5 0xb>, <&intc_cpu5 9>,
<&intc_cpu6 0xb>, <&intc_cpu6 9>,
<&intc_cpu7 0xb>, <&intc_cpu7 9>,
<&intc_cpu8 0xb>, <&intc_cpu8 9>,
<&intc_cpu9 0xb>, <&intc_cpu9 9>,
<&intc_cpu10 0xb>, <&intc_cpu10 9>,
<&intc_cpu11 0xb>, <&intc_cpu11 9>,
<&intc_cpu12 0xb>, <&intc_cpu12 9>,
<&intc_cpu13 0xb>, <&intc_cpu13 9>,
<&intc_cpu14 0xb>, <&intc_cpu14 9>,
<&intc_cpu15 0xb>, <&intc_cpu15 9>;
};
&xdma_0 {
status = "disabled";
};
&xdma_1 {
status = "disabled";
};

18
arch/riscv/boot/dts/bosc/nanhu-v5-1core-uartlite.dts
View File

@@ -23,10 +23,20 @@
};
};
&cpu0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&cpu0 {
status = "okay";
};
&PLIC {
interrupts-extended = <&intc_cpu0 0xb>, <&intc_cpu0 9>;
};
&xdma_0 {
status = "disabled";
};
&xdma_1 {
status = "disabled";
};

12
arch/riscv/boot/dts/bosc/nanhu-v5-1core.dts
View File

@@ -15,7 +15,7 @@
};
chosen {
bootargs = "console=hvc0 earlycon=sbi loglevel=8";
bootargs = "console=ttyS0,115200 earlycon=sbi loglevel=8 root=/dev/nvme0n1p1 rootwait rw";
opensbi-config {
compatible = "opensbi,config";
cold-boot-harts = <&cpu0>;
@@ -30,3 +30,13 @@
&uart0 {
status = "okay";
};
&PLIC {
interrupts-extended = <&intc_cpu0 0xb>, <&intc_cpu0 9>;
};
&xdma_0 {
status = "disabled";
};
&xdma_1 {
status = "disabled";
};

44
arch/riscv/boot/dts/bosc/nanhu-v5-2core-uartlite.dts Normal file
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@@ -0,0 +1,44 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2025 BOSC */
/dts-v1/;
#include "nanhu-v5.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "bosc,nanhu-v5-dev";
model = "bosc,nanhu-v5-2core-uartlite";
chosen {
bootargs = "console=hvc0 earlycon=sbi loglevel=8";
opensbi-config {
compatible = "opensbi,config";
cold-boot-harts = <&cpu0>;
};
};
};
&uart1 {
status = "okay";
};
&cpu0 {
status = "okay";
};
&cpu1 {
status = "okay";
};
&PLIC {
interrupts-extended =
<&intc_cpu0 0xb>, <&intc_cpu0 9>,
<&intc_cpu1 0xb>, <&intc_cpu1 9>;
};
&xdma_0 {
status = "disabled";
};
&xdma_1 {
status = "disabled";
};

44
arch/riscv/boot/dts/bosc/nanhu-v5-2core.dts Normal file
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@@ -0,0 +1,44 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2025 BOSC */
/dts-v1/;
#include "nanhu-v5.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "bosc,nanhu-v5-dev";
model = "bosc,nanhu-v5-2core";
chosen {
bootargs = "console=hvc0 earlycon=sbi loglevel=8";
opensbi-config {
compatible = "opensbi,config";
cold-boot-harts = <&cpu0>;
};
};
};
&cpu0 {
status = "okay";
};
&cpu1 {
status = "okay";
};
&uart0 {
status = "okay";
};
&PLIC {
interrupts-extended =
<&intc_cpu0 0xb>, <&intc_cpu0 9>,
<&intc_cpu1 0xb>, <&intc_cpu1 9>;
};
&xdma_0 {
status = "disabled";
};
&xdma_1 {
status = "disabled";
};

54
arch/riscv/boot/dts/bosc/nanhu-v5-4core-uartlite.dts Normal file
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@@ -0,0 +1,54 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2025 BOSC */
/dts-v1/;
#include "nanhu-v5.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "bosc,nanhu-v5-dev";
model = "bosc,nanhu-v5-4core-uartlite";
chosen {
bootargs = "console=hvc0 earlycon=sbi loglevel=8";
opensbi-config {
compatible = "opensbi,config";
cold-boot-harts = <&cpu0>;
};
};
};
&uart1 {
status = "okay";
};
&cpu0 {
status = "okay";
};
&cpu1 {
status = "okay";
};
&cpu2 {
status = "okay";
};
&cpu3 {
status = "okay";
};
&PLIC {
interrupts-extended =
<&intc_cpu0 0xb>, <&intc_cpu0 9>,
<&intc_cpu1 0xb>, <&intc_cpu1 9>,
<&intc_cpu2 0xb>, <&intc_cpu2 9>,
<&intc_cpu3 0xb>, <&intc_cpu3 9>;
};
&xdma_0 {
status = "disabled";
};
&xdma_1 {
status = "disabled";
};

54
arch/riscv/boot/dts/bosc/nanhu-v5-4core.dts Normal file
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@@ -0,0 +1,54 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2025 BOSC */
/dts-v1/;
#include "nanhu-v5.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "bosc,nanhu-v5-dev";
model = "bosc,nanhu-v5-4core";
chosen {
bootargs = "console=hvc0 earlycon=sbi loglevel=8";
opensbi-config {
compatible = "opensbi,config";
cold-boot-harts = <&cpu0>;
};
};
};
&cpu0 {
status = "okay";
};
&cpu1 {
status = "okay";
};
&cpu2 {
status = "okay";
};
&cpu3 {
status = "okay";
};
&uart0 {
status = "okay";
};
&PLIC {
interrupts-extended =
<&intc_cpu0 0xb>, <&intc_cpu0 9>,
<&intc_cpu1 0xb>, <&intc_cpu1 9>,
<&intc_cpu2 0xb>, <&intc_cpu2 9>,
<&intc_cpu3 0xb>, <&intc_cpu3 9>;
};
&xdma_0 {
status = "disabled";
};
&xdma_1 {
status = "disabled";
};

74
arch/riscv/boot/dts/bosc/nanhu-v5-8core-uartlite.dts Normal file
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@@ -0,0 +1,74 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2025 BOSC */
/dts-v1/;
#include "nanhu-v5.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "bosc,nanhu-v5-dev";
model = "bosc,nanhu-v5-8core-uartlite";
chosen {
bootargs = "console=hvc0 earlycon=sbi loglevel=8";
opensbi-config {
compatible = "opensbi,config";
cold-boot-harts = <&cpu0>;
};
};
};
&uart1 {
status = "okay";
};
&cpu0 {
status = "okay";
};
&cpu1 {
status = "okay";
};
&cpu2 {
status = "okay";
};
&cpu3 {
status = "okay";
};
&cpu4 {
status = "okay";
};
&cpu5 {
status = "okay";
};
&cpu6 {
status = "okay";
};
&cpu7 {
status = "okay";
};
&PLIC {
interrupts-extended =
<&intc_cpu0 0xb>, <&intc_cpu0 9>,
<&intc_cpu1 0xb>, <&intc_cpu1 9>,
<&intc_cpu2 0xb>, <&intc_cpu2 9>,
<&intc_cpu3 0xb>, <&intc_cpu3 9>,
<&intc_cpu4 0xb>, <&intc_cpu4 9>,
<&intc_cpu5 0xb>, <&intc_cpu5 9>,
<&intc_cpu6 0xb>, <&intc_cpu6 9>,
<&intc_cpu7 0xb>, <&intc_cpu7 9>;
};
&xdma_0 {
status = "disabled";
};
&xdma_1 {
status = "disabled";
};

74
arch/riscv/boot/dts/bosc/nanhu-v5-8core.dts Normal file
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@@ -0,0 +1,74 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2025 BOSC */
/dts-v1/;
#include "nanhu-v5.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "bosc,nanhu-v5-dev";
model = "bosc,nanhu-v5-8core";
chosen {
bootargs = "console=hvc0 earlycon=sbi loglevel=8";
opensbi-config {
compatible = "opensbi,config";
cold-boot-harts = <&cpu0>;
};
};
};
&cpu0 {
status = "okay";
};
&cpu1 {
status = "okay";
};
&cpu2 {
status = "okay";
};
&cpu3 {
status = "okay";
};
&cpu4 {
status = "okay";
};
&cpu5 {
status = "okay";
};
&cpu6 {
status = "okay";
};
&cpu7 {
status = "okay";
};
&uart0 {
status = "okay";
};
&PLIC {
interrupts-extended =
<&intc_cpu0 0xb>, <&intc_cpu0 9>,
<&intc_cpu1 0xb>, <&intc_cpu1 9>,
<&intc_cpu2 0xb>, <&intc_cpu2 9>,
<&intc_cpu3 0xb>, <&intc_cpu3 9>,
<&intc_cpu4 0xb>, <&intc_cpu4 9>,
<&intc_cpu5 0xb>, <&intc_cpu5 9>,
<&intc_cpu6 0xb>, <&intc_cpu6 9>,
<&intc_cpu7 0xb>, <&intc_cpu7 9>;
};
&xdma_0 {
status = "disabled";
};
&xdma_1 {
status = "disabled";
};

377
arch/riscv/boot/dts/bosc/nanhu-v5.dtsi
View File

@@ -31,6 +31,291 @@
interrupt-controller;
};
};
cpu1: cpu@1 {
compatible = "bosc,nanhu-v5", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv48";
reg = <0x1>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"sstc";
status = "disabled";
intc_cpu1: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu2: cpu@2 {
compatible = "bosc,nanhu-v5", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv48";
reg = <0x2>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"sstc";
status = "disabled";
intc_cpu2: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu3: cpu@3 {
compatible = "bosc,nanhu-v5", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv48";
reg = <0x3>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"sstc";
status = "disabled";
intc_cpu3: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu4: cpu@4 {
compatible = "bosc,nanhu-v5", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv48";
reg = <0x4>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"sstc";
status = "disabled";
intc_cpu4: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu5: cpu@5 {
compatible = "bosc,nanhu-v5", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv48";
reg = <0x5>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"sstc";
status = "disabled";
intc_cpu5: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu6: cpu@6 {
compatible = "bosc,nanhu-v5", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv48";
reg = <0x6>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"sstc";
status = "disabled";
intc_cpu6: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu7: cpu@7 {
compatible = "bosc,nanhu-v5", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv48";
reg = <0x7>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"sstc";
status = "disabled";
intc_cpu7: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu8: cpu@8 {
compatible = "bosc,nanhu-v5", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv48";
reg = <0x8>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"sstc";
status = "disabled";
intc_cpu8: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu9: cpu@9 {
compatible = "bosc,nanhu-v5", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv48";
reg = <0x9>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"sstc";
status = "disabled";
intc_cpu9: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu10: cpu@10 {
compatible = "bosc,nanhu-v5", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv48";
reg = <0xa>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"sstc";
status = "disabled";
intc_cpu10: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu11: cpu@11 {
compatible = "bosc,nanhu-v5", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv48";
reg = <0xb>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"sstc";
status = "disabled";
intc_cpu11: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu12: cpu@12 {
compatible = "bosc,nanhu-v5", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv48";
reg = <0xc>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"sstc";
status = "disabled";
intc_cpu12: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu13: cpu@13 {
compatible = "bosc,nanhu-v5", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv48";
reg = <0xd>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"sstc";
status = "disabled";
intc_cpu13: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu14: cpu@14 {
compatible = "bosc,nanhu-v5", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv48";
reg = <0xe>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"sstc";
status = "disabled";
intc_cpu14: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu15: cpu@15 {
compatible = "bosc,nanhu-v5", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv48";
reg = <0xf>;
riscv,isa = "rv64imafdc";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"sstc";
status = "disabled";
intc_cpu15: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
soc {
@@ -42,7 +327,33 @@
clint: timer@38000000 {
compatible = "riscv,clint0";
reg = <0x0 0x38000000 0x0 0x10000>;
interrupts-extended = <&intc_cpu0 3>, <&intc_cpu0 7>;
interrupts-extended =
<&intc_cpu0 3>, <&intc_cpu0 7>,
<&intc_cpu1 3>, <&intc_cpu1 7>,
<&intc_cpu2 3>, <&intc_cpu2 7>,
<&intc_cpu3 3>, <&intc_cpu3 7>,
<&intc_cpu4 3>, <&intc_cpu4 7>,
<&intc_cpu5 3>, <&intc_cpu5 7>,
<&intc_cpu6 3>, <&intc_cpu6 7>,
<&intc_cpu7 3>, <&intc_cpu7 7>,
<&intc_cpu8 3>, <&intc_cpu8 7>,
<&intc_cpu9 3>, <&intc_cpu9 7>,
<&intc_cpu10 3>, <&intc_cpu10 7>,
<&intc_cpu11 3>, <&intc_cpu11 7>,
<&intc_cpu12 3>, <&intc_cpu12 7>,
<&intc_cpu13 3>, <&intc_cpu13 7>,
<&intc_cpu14 3>, <&intc_cpu14 7>,
<&intc_cpu15 3>, <&intc_cpu15 7>;
};
PLIC: interrupt-controller@3c000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
reg = <0 0x3c000000 0 0x4000000>;
reg-names = "control";
riscv,max-priority = <7>;
riscv,ndev = <64>;
};
uart0: serial@310b0000 {
@@ -50,6 +361,8 @@
reg = <0x0 0x310b0000 0x0 0x10000>;
reg-shift = <0x02>;
reg-io-width = <0x04>;
interrupt-parent = <&PLIC>;
interrupts = <40>;
clock-frequency = <50000000>;
current-speed = <115200>;
status = "disabled";
@@ -63,14 +376,72 @@
status = "disabled";
};
clkc: misc_clk_xdma {
#clock-cells = <0>;
clock-frequency = <10000000>;
compatible = "fixed-clock";
};
xdma_0: pcie@48000000 {
#address-cells = <3>;
#interrupt-cells = <1>;
#size-cells = <2>;
clock-names = "sys_clk", "sys_clk_gt";
clocks = <&clkc>, <&clkc>;
compatible = "xlnx,xdma-host-3.00";
device_type = "pci";
interrupt-map = <0x0 0 0 1 &pcie_intc_0 1>,
<0x0 0 0 2 &pcie_intc_0 2>,
<0x0 0 0 3 &pcie_intc_0 3>,
<0x0 0 0 4 &pcie_intc_0 4>;
interrupt-map-mask = <0x0 0 0 7>;
interrupt-names = "misc", "msi0", "msi1";
interrupt-parent = <&PLIC>;
interrupts = <53 IRQ_TYPE_EDGE_RISING>, <52 IRQ_TYPE_EDGE_RISING>, <51 IRQ_TYPE_EDGE_RISING>;
ranges = <0x02000000 0x00000000 0x20000000 0x0 0x40000000 0x0 0x10000000>;
reg = <0x00000000 0x48000000 0x0 0x1000000>;
status = "disabled";
pcie_intc_0: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller ;
};
};
xdma_1: pcie@4c000000 {
#address-cells = <3>;
#interrupt-cells = <1>;
#size-cells = <2>;
clock-names = "sys_clk", "sys_clk_gt";
clocks = <&clkc>, <&clkc>;
compatible = "xlnx,xdma-host-3.00";
device_type = "pci";
interrupt-map = <0x0 0 0 1 &pcie_intc_1 1>,
<0x0 0 0 2 &pcie_intc_1 2>,
<0x0 0 0 3 &pcie_intc_1 3>,
<0x0 0 0 4 &pcie_intc_1 4>;
interrupt-map-mask = <0x0 0 0 7>;
interrupt-names = "misc", "msi0", "msi1";
interrupt-parent = <&PLIC>;
interrupts = <59 IRQ_TYPE_EDGE_RISING>, <58 IRQ_TYPE_EDGE_RISING>, <57 IRQ_TYPE_EDGE_RISING>;
ranges = <0x02000000 0x0 0x40000000 0x0 0x60000000 0x00000000 0x20000000>;
reg = <0x00000000 0x4c000000 0x0 0x4000000>;
status = "disabled";
pcie_intc_1: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller ;
};
};
};
chosen {
rng-seed = <0xc8518d39 0x6bde432f 0x4d998c79 0xaa192096 0xdbcf36f3 0x532f3ab3 0x965240fe 0xac379c0e>;
};
memory: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000 >;
reg = <0x0 0x80000000 0x04 0x0>;
};
};

5
arch/riscv/configs/minimal_defconfig
View File

@@ -22,7 +22,7 @@ CONFIG_EXPERT=y
# CONFIG_MULTIUSER is not set
# CONFIG_SYSFS_SYSCALL is not set
# CONFIG_FHANDLE is not set
# CONFIG_POSIX_TIMERS is not set
CONFIG_POSIX_TIMERS=y
# CONFIG_BUG is not set
# CONFIG_BASE_FULL is not set
@@ -36,7 +36,7 @@ CONFIG_FUTEX=y
# CONFIG_IO_URING is not set
# CONFIG_ADVISE_SYSCALLS is not set
# CONFIG_MEMBARRIER is not set
# CONFIG_KALLSYMS is not set
CONFIG_KALLSYMS=y
# CONFIG_KCMP is not set
# CONFIG_RSEQ is not set
@@ -114,3 +114,4 @@ CONFIG_PRINTK_TIME=y
CONFIG_SOC_XIANGSHAN=y
CONFIG_DEBUG_FS=y
CONFIG_SMP=y
CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y

117
arch/riscv/configs/minimal_rd_compressed_defconfig Normal file
View File

@@ -0,0 +1,117 @@
CONFIG_DEFAULT_HOSTNAME="(XiangShan)"
CONFIG_SOC_XIANGSHAN=y
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE="rootfs_nopasswd.cpio"
CONFIG_RD_GZIP=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_XZ is not set
# CONFIG_RD_LZO is not set
# CONFIG_RD_LZ4 is not set
# CONFIG_RD_ZSTD is not set
CONFIG_INITRAMFS_COMPRESSION_GZIP=y
# CONFIG_INITRAMFS_PRESERVE_MTIME is not set
CONFIG_KERNEL_UNCOMPRESSED=y
CONFIG_EXPERT=y
# CONFIG_MULTIUSER is not set
# CONFIG_SYSFS_SYSCALL is not set
# CONFIG_FHANDLE is not set
CONFIG_POSIX_TIMERS=y
# CONFIG_BUG is not set
# CONFIG_BASE_FULL is not set
CONFIG_FUTEX=y
# CONFIG_EPOLL is not set
# CONFIG_SIGNALFD is not set
# CONFIG_TIMERFD is not set
# CONFIG_EVENTFD is not set
# CONFIG_SHMEM is not set
# CONFIG_AIO is not set
# CONFIG_IO_URING is not set
# CONFIG_ADVISE_SYSCALLS is not set
# CONFIG_MEMBARRIER is not set
CONFIG_KALLSYMS=y
# CONFIG_KCMP is not set
# CONFIG_RSEQ is not set
CONFIG_NONPORTABLE=y
CONFIG_ARCH_RV64I=y
CONFIG_CMODEL_MEDLOW=y
# CONFIG_RISCV_ISA_SVPBMT is not set
CONFIG_HZ_100=y
CONFIG_RISCV_SBI_V01=y
# CONFIG_COMPAT is not set
# CONFIG_EFI is not set
# CONFIG_SECCOMP is not set
# CONFIG_STACKPROTECTOR is not set
# CONFIG_VMAP_STACK is not set
# CONFIG_STRICT_KERNEL_RWX is not set
# CONFIG_BLOCK is not set
# CONFIG_BINFMT_SCRIPT is not set
# CONFIG_COREDUMP is not set
# CONFIG_SLAB_MERGE_DEFAULT is not set
# CONFIG_COMPAT_BRK is not set
# CONFIG_COMPACTION is not set
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
# CONFIG_FW_LOADER is not set
# CONFIG_ALLOW_DEV_COREDUMP is not set
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_UNIX98_PTYS is not set
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
CONFIG_HVC_DRIVER=y
CONFIG_HVC_RISCV_SBI=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_VIRTIO_CONSOLE=y
# CONFIG_HW_RANDOM is not set
# CONFIG_DEVMEM is not set
# CONFIG_HWMON is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_VIRTIO_MENU is not set
# CONFIG_VHOST_MENU is not set
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_SIFIVE_PLIC=y
# CONFIG_FILE_LOCKING is not set
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY_USER is not set
# CONFIG_MISC_FILESYSTEMS is not set
# CONFIG_SYMBOLIC_ERRNAME is not set
# CONFIG_DEBUG_MISC is not set
CONFIG_STRIP_ASM_SYMS=y
# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
# CONFIG_FRAME_POINTER is not set
# CONFIG_FTRACE is not set
# CONFIG_RUNTIME_TESTING_MENU is not set
CONFIG_PRINTK_TIME=y
# CONFIG_PM is not set
# CONFIG_SUSPEND is not set
CONFIG_SOC_XIANGSHAN=y
CONFIG_DEBUG_FS=y
CONFIG_SMP=y
CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y

11
drivers/irqchip/irq-riscv-imsic-early.c
View File

@@ -154,10 +154,13 @@ static int __init imsic_early_probe(struct fwnode_handle *fwnode)
}
/* Initialize IPI domain */
rc = imsic_ipi_domain_init();
if (rc) {
pr_err("%pfwP: Failed to initialize IPI domain\n", fwnode);
return rc;
if (!of_property_read_bool(to_of_node(fwnode), "no-imsic-ipi")) {
/* Initialize IPI domain */
rc = imsic_ipi_domain_init();
if (rc) {
pr_err("%pfwP: Failed to initialize IPI domain\n", fwnode);
return rc;
}
}
/* Setup chained handler to the parent domain interrupt */