mirror of
https://github.com/clearlinux/kvmtool.git
synced 2026-08-22 13:37:29 +00:00
Will Deacon
b59816369a
For the MMIO and PCI buses, drivers typically allocate an IRQ line for their device before registering the device with the device tree for the relevant bus. This patch moves the IRQ allocation into the bus code, which is then called directly by the device tree when a new device is registered. IOPORT devices, however, tend to use hardcoded IRQs for legacy reasons, so they are still required to deal with their interrupts (which also require remapping for non-x86 architectures). Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Pekka Enberg <penberg@kernel.org>
97 lines
2.3 KiB
C
97 lines
2.3 KiB
C
#ifndef KVM__PCI_H
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#define KVM__PCI_H
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#include <linux/types.h>
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#include <linux/kvm.h>
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#include <linux/pci_regs.h>
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#include <endian.h>
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#include "kvm/devices.h"
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#include "kvm/kvm.h"
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#include "kvm/msi.h"
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/*
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* PCI Configuration Mechanism #1 I/O ports. See Section 3.7.4.1.
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* ("Configuration Mechanism #1") of the PCI Local Bus Specification 2.1 for
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* details.
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*/
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#define PCI_CONFIG_ADDRESS 0xcf8
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#define PCI_CONFIG_DATA 0xcfc
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#define PCI_CONFIG_BUS_FORWARD 0xcfa
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#define PCI_IO_SIZE 0x100
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#define PCI_CFG_SIZE (1ULL << 24)
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union pci_config_address {
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struct {
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#if __BYTE_ORDER == __LITTLE_ENDIAN
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unsigned reg_offset : 2; /* 1 .. 0 */
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unsigned register_number : 6; /* 7 .. 2 */
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unsigned function_number : 3; /* 10 .. 8 */
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unsigned device_number : 5; /* 15 .. 11 */
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unsigned bus_number : 8; /* 23 .. 16 */
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unsigned reserved : 7; /* 30 .. 24 */
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unsigned enable_bit : 1; /* 31 */
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#else
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unsigned enable_bit : 1; /* 31 */
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unsigned reserved : 7; /* 30 .. 24 */
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unsigned bus_number : 8; /* 23 .. 16 */
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unsigned device_number : 5; /* 15 .. 11 */
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unsigned function_number : 3; /* 10 .. 8 */
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unsigned register_number : 6; /* 7 .. 2 */
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unsigned reg_offset : 2; /* 1 .. 0 */
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#endif
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};
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u32 w;
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};
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struct msix_table {
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struct msi_msg msg;
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u32 ctrl;
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};
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struct msix_cap {
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u8 cap;
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u8 next;
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u16 ctrl;
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u32 table_offset;
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u32 pba_offset;
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};
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struct pci_device_header {
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u16 vendor_id;
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u16 device_id;
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u16 command;
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u16 status;
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u8 revision_id;
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u8 class[3];
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u8 cacheline_size;
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u8 latency_timer;
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u8 header_type;
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u8 bist;
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u32 bar[6];
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u32 card_bus;
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u16 subsys_vendor_id;
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u16 subsys_id;
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u32 exp_rom_bar;
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u8 capabilities;
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u8 reserved1[3];
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u32 reserved2;
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u8 irq_line;
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u8 irq_pin;
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u8 min_gnt;
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u8 max_lat;
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struct msix_cap msix;
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u8 empty[136]; /* Rest of PCI config space */
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u32 bar_size[6];
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} __attribute__((packed));
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int pci__init(struct kvm *kvm);
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int pci__exit(struct kvm *kvm);
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struct pci_device_header *pci__find_dev(u8 dev_num);
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u32 pci_get_io_space_block(u32 size);
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void pci__assign_irq(struct device_header *dev_hdr);
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void pci__config_wr(struct kvm *kvm, union pci_config_address addr, void *data, int size);
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void pci__config_rd(struct kvm *kvm, union pci_config_address addr, void *data, int size);
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#endif /* KVM__PCI_H */
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