1731 Commits

Author SHA1 Message Date
Patrice Chotard 4c3aa5356d clk: scmi: Remove duplicated scmi_generic_protocol_version() request
scmi_generic_protocol_version() request is done twice in scmi_clk_probe().
Remove first call which is useless.

Fixes: ae7e0330ce ("clk: scmi: add compatibility with clock protocol 2.0")
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-01-05 10:04:48 +08:00
Patrice Chotard 0e9055b148 clk: scmi: Fix priv initialization in scmi_clk_gate()
In scmi_clk_probe(), in case of CLK_CCF is not enabled, parent private
data is not set, so in scmi_clk_gate(), an uninitialized priv struct is
retrieved.

SCMI request is performed either using scmi_clk_state_in_v1 or
scmi_clk_state_in_v2 struct depending of the unpredictable value of
priv->version which leads to error during SCMI clock enable.

Issue detected on STM32MP157C-DK2 board using the SCMI device tree
stm32mp157c-dk2-scmi.dts.

Fixes: 0619cb3203 ("firmware: scmi: Add clock v3.2 CONFIG_SET support")
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-01-05 10:04:48 +08:00
Patrice Chotard 9a23c1e5f2 clk: scmi: Fix typo scmi_clk_get_attibute
Fix typo attibute, rename scmi_clk_get_attibute() to
scmi_clk_get_attribute().

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-01-05 10:04:48 +08:00
Niklas Söderlund 06df1a5072 clk: renesas: Do not disable realtime modules on R8A77995 D3
Later versions of the datasheet makes it clear D3 do not have any
realtime module stop control registers (RMSTPCRx). Remove the
manipulation of them from the module clock table to match this.

Suggested-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2025-12-29 20:47:53 +01:00
Niklas Söderlund 3147cd713e clk: renesas: Do not enable MSTP4 extra modules on R8A77995 D3
Since commit a2bd99549c ("clk: renesas: Tear clock controller down
last before booting OS") enabling the module gated by bit 8 in MSTP4
prevents Linux from booting. The bits 8 and 7 of MSTP4 where only
documented in early versions of the datasheet and have since been
removed.

To allow Linux to boot update the MSTP4 enable value to reflect the
hardware default, 0x80.

Suggested-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2025-12-29 20:47:53 +01:00
David Lechner 9d08916a57 clk: mediatek: remove duplicate '@parent' field doc
Remove duplicate '@parent' field documentation in struct mtk_composite.
There is no need to say the same thing twice.

Also fix spelling mistake in the word "parent" while we're at it.

Signed-off-by: David Lechner <dlechner@baylibre.com>
2025-12-16 11:14:31 -06:00
Marek Vasut af96395a82 clk: renesas: Introduce temporary compound clock for SCP compatibility
The current state of SCP on Renesas R-Car Gen5 is not yet final and
is still missing full clock control, the clock control is exposed as
separate enable/disable and rate controls.

Temporarily introduce custom local compound clock, which are used as
an adaptation layer between U-Boot clock tree and current state of
SCP, and which bind two SCP clock into a single compound clock, which
provides both enable/disable and rate controls.

This is mainly meant to be used by SD/eMMC controller, to allow the
driver to both turn its clock on and off, and also obtain the current
clock rate. This is going to be removed once the SCP clock protocol
solidifies.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-12-03 00:17:15 +01:00
Kaustabh Chakraborty 07b8261d48 clk: use private clk struct to access clock flags
There may be cases where the flags set for a clock is not available.
This is usually the case with clocks which have been retrieved using
clk_request(). However, clock flags are found in their respective
private clock struct, so use that instead.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-11-12 13:56:12 +09:00
Kaustabh Chakraborty 67fea5775b clk: exynos: add support for Exynos7870 CMU
Introduce a simple clock driver for Exynos7870's CMU blocks, more
specifically, CMU_MIF, CMU_FSYS, and CMU_PERI banks. This should be
enough to serve U-Boot's minimal requirements.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-11-12 13:56:12 +09:00
Kaustabh Chakraborty 4bee54fbfa clk: exynos: add function for Samsung CMU ops->request
The request function performs a simple check if the clock with the
provided ID is present or not. This is done with a simple call to
clk_get_by_id(). A non-zero return value indicates that the requested
clock is not available.

In some cases, clk->dev points to the clock bank device instead of
the clock device. This pointer is therefore overwritten in order to
reference to the correct device instance.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-11-12 13:56:12 +09:00
Kaustabh Chakraborty 526a257fdb clk: exynos: add support for PLL1417X
PLL1417X seem to be compatible with PLL0822X, as also seen in the
respective Linux kernel driver. Add an enum entry for the type, while
merely being an alias for PLL0822X.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-11-12 13:56:12 +09:00
Kaustabh Chakraborty b006e40963 clk: exynos: add support for fixed rate and fixed factor clocks
Add register functions for fixed rate and fixed factor clock drivers.
The vendor-specific structs defined are borrowed from the CCF driver
found in the Linux kernel.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-11-12 13:56:12 +09:00
Kaustabh Chakraborty 2a07137641 clk: exynos: provide device pointer to clk_register_* functions
The device pointer set as NULL causes problems when clock banks depend
on clocks from another clock bank. In such case, the appropriate clock
needs to be resolved from OF phandle arguments, which is not possible if
the associated device is not provided. Make necessary changes to make
the correct device pointer available.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-11-12 13:56:12 +09:00
Marek Vasut 3547e315c1 clk: scmi: Defer issue of SCMI_CLOCK_ATTRIBUTES
Instead of resolving clock control flags using SCMI_CLOCK_ATTRIBUTES
during probe for each and every clock, resolve the clock control
flags using SCMI_CLOCK_ATTRIBUTES when the clock control flags are
first used. Because most clock are never used by U-Boot, this allows
reducing the amount of SCMI_CLOCK_ATTRIBUTES considerably, and this
improve probe time of the scmi clock driver and U-Boot start up time.

On Renesas X5H, with 1700+ SCMI clock, the boot time improved by 1.7s .

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-11-10 20:57:49 +08:00
Marek Vasut fdb1bffe28 clk: scmi: Postpone clock name resolution
The clock names are retrived via SCMI_CLOCK_ATTRIBUTES, called for each
clock ID. This may take a lot of time to complete and is not strictly
necessary. Register each clock as "scmi-%zu" instead, and let the first
call of SCMI_CLOCK_ATTRIBUTES fill in the actual clock name.

This has a side effect, which can be considered both an upside and also
a downside. Unused clock are never renamed and retain their placeholder
"scmi-%zu" name, which avoids empty clock names for nameless SCMI clock,
and avoids the name resolution and improves boot time. But for those
SCMI clock which do have name, that name is not listed until the clock
are used.

This is a preparatory patch for deferred issue of SCMI_CLOCK_ATTRIBUTES.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-11-10 20:57:48 +08:00
Marek Vasut 21bfe6a291 clk: scmi: Factor out clock control flags resolution
Pull clock control flags resolution into dedicated function and
call it from each site that does access clock control flags. No
functional change.

This is a preparatory patch for deferred issue of SCMI_CLOCK_ATTRIBUTES.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-11-10 20:57:48 +08:00
Marek Vasut ef52f697f2 clk: scmi: Bulk allocate all sub-driver instance data
Allocate all sub-driver instance data at once. The amount of data that
have to be allocated is known up front, so is the size of the data, so
there is no need to call malloc() in a loop, mallocate all data at once.

The upside is, less heap fragmentation and fewer malloc() calls overall,
and a faster boot time.

The downside is, if some of the clock fail to register, then the clock
driver cannot free parts of the bulk allocated sub-driver instance data.
Such a failure can only occur if clk_register() were to fail, and if that
happens, the system has more significant problems. Worse, if a core clock
driver fails to probe, the system has even bigger problem.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-11-10 20:57:46 +08:00
Kamlesh Gurudasani 66cb830291 clk: scmi: fix set_parent support when CCF is not being used
When not using Common clock framework(CCF), calls to
scmi_clk_set_parent returns -ENOTSUPP, which should not be the case.
Fix that.

Fixes: 15fdfef664 ("clk: scmi: check the clock state/parent/rate
control permissions)

Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-11-10 20:57:44 +08:00
Vinh Nguyen 0619cb3203 firmware: scmi: Add clock v3.2 CONFIG_SET support
SCMI v3.2 introduces a new clock CONFIG_SET message format that can
optionally carry also OEM specific configuration values beside the usual
clock enable/disable requests. Add support to use such new format when
talking to a v3.2 compliant SCMI platform.

Support existing enable/disable operations across different clock protocol
versions: this patch still does not add protocol operations to support the
new OEM specific optional configuration capabilities.

No functional change for the SCMI drivers users of the related enable and
disable clock operations.

[Marek: Remodel after Linux e49e314a2cf7 ("firmware: arm_scmi: Add clock v3.2 CONFIG_SET support")
        Support both old < 2.1 and new >= 2.1 protocol versions.
	Update commit message based on Linux one]

Signed-off-by: Vinh Nguyen <vinh.nguyen.xz@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-11-10 20:57:42 +08:00
Tom Rini 6b27b68869 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
Remaining R-Car Gen5 driver patches, MMC, clock. Also a trivial
adjustment for mailbox core to allow operation without .recv callback.
2025-11-08 09:03:54 -06:00
Tom Rini 5e5b630eef Merge patch series "arm: airoha: add support for en7523 based boards"
Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> says:

This patch series adds basic support for the boards based on Airoha
EN7523/EN7529/EN7562 SoCs. Due to ATF restrictions these boards are
able to run 32-bit OS only.

This patch series adds support for the following hardware:
 * console UART
 * ethernet controller/switch
 * spinand flash (in non-dma mode)

The following issues may be expected:
 * Extra slow UBI attaching in U-Boot (up to 20 sec with fastmap enabled).
   This is caused by the lack of DMA support in the U-Boot airoha-snfi driver.
 * Linux airoha-snfi driver in some cases might damage you flash data
   (see: https://lore.kernel.org/lkml/20251012121707.2296160-15-mikhail.kshevetskiy@iopsys.eu/)
 * Latest linux kernel is recommended to properly support flashes
   with more than one plane per lun
   (see: https://lore.kernel.org/lkml/20251012121707.2296160-7-mikhail.kshevetskiy@iopsys.eu/)
 * It's NOT recommended to use flashes working in continuous mode because
   U-Boot airoha-snfi driver does not support such flashes properly.

The patches was tested on the board:
 - SoC: Airoha EN7562
 - RAM: 512 MB
 - SPI NAND: 4 Gbit, made by Toshiba
 - Linux boot: was NOT tested

The U-Boot was chain-loaded from the running U-Boot. Airoha ATF-2.3 does
not allow easily chain-loading of U-Boot from U-Boot, so a special FIT
image (mimic linux kernel) was created

1) Create u-boot.its file with the following contents:

=== cut here ===
/dts-v1/;

/ {
	description = "ARM OpenWrt FIT (Flattened Image Tree)";
	#address-cells = <1>;

	images {
		u-boot-ram {
			description = "OpenWrt U-Boot RAM image";
			data = /incbin/("u-boot.bin.lzma");
			type = "kernel";
			arch = "arm";
			os = "linux";
			compression = "lzma";
			load = <0x81e00000>;
			entry = <0x81e00000>;
			hash@1 {
				algo = "crc32";
			};
			hash@2 {
				algo = "sha1";
			};
		};

		fdt-1 {
			description = "OpenWrt device tree blob";

			data = /incbin/("dts/upstream/src/arm/airoha/en7523-evb.dtb");
			type = "flat_dt";

			arch = "arm";
			compression = "none";
			hash@1 {
				algo = "crc32";
			};
			hash@2 {
				algo = "sha1";
			};
		};
	};

	configurations {
		default = "config-ram-uboot";
		config-ram-uboot {
			description = "OpenWrt RAM U-Boot";
			kernel = "u-boot-ram";
			fdt = "fdt-1";
		};
	};
};
==================

2) Create u-boot.itb image to chain-load new u-boot from the old one

  lzma_alone e u-boot.bin u-boot.bin.lzma
  mkimage -f u-boot.its u-boot.itb

3) Load new u-boot from the old one

  U-Boot> tftpboot u-boot.itb && bootm

Link: https://lore.kernel.org/r/20251101004503.2379529-1-mikhail.kshevetskiy@iopsys.eu
2025-11-07 16:45:09 -06:00
Mikhail Kshevetskiy ee82f804dd clk: airoha: add support for airoha en7523 SoC family
This adds clock driver for airoha en7523/en7529/en7562 SoCs. The code
is based on corresponding linux driver.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2025-11-07 16:00:59 -06:00
Mikhail Kshevetskiy f8cef0b743 clk: airoha: use CHIP_SCU regmap helper
Use common helper to get CHIP_SCU registers.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2025-11-07 16:00:58 -06:00
Marek Vasut bc47ca03b8 clk: renesas: Isolate R-Car Gen3 driver to Gen3, Gen4 and RZ/G2L
Isolate Renesas R-Car Gen3 clock driver to R-Car Gen3 and Gen4 and RZ/G2L.
The Renesas R-Car Gen5 uses SCMI clock protocol driver instead. This is
a preparatory change for R-Car Gen5. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-11-07 17:40:42 +01:00
Tom Rini c2637036b8 Merge tag 'u-boot-rockchip-20251101' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/28119
- New Boards support:
    rk3588: MNT Reform2
    rk3528: Radxa ROCK 2A/2F
    rk3576: ArmSoM Sige1, Luckfox Omni3576, FriendlyElec NanoPi M5,
            Radxa ROCK 4D
    rk3568: Lunzn FastRhino R66S
- Other board level updates.
2025-11-02 12:15:23 -06:00
Jonas Karlman 70a2168569 clk: px30: Allow use of GPU and WIFI_PMU in assigned-clocks
Add dummy implementation of set_rate for SCLK_GPU and SCLK_WIFI_PMU to
allow use of dts/upstream assigned-clocks in cru and pmucru nodes.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-11-01 21:17:42 +08:00
Casey Connolly 9887944c4f clk/qcom: sc7280: add uart5 and uart7 clocks
Allow us to power up UART7 so we can load the QUP firmware, this is used
for bluetooth on RB3 Gen 2 and possibly other boards.

Additionally add the UART5 clocks so we can adjust baud rate for UART

Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20250714-geni-load-fw-v5-5-5abbc0d29838@linaro.org
Signed-off-by: Casey Connolly <kcxt@postmarketos.org>
2025-10-30 11:04:51 -06:00
Jens Reidel 077ae372da clk/stub: add sc7180-rpmh clock
Stub the RPMh clock controller on SC7180.

Signed-off-by: Jens Reidel <adrian@mainlining.org>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250826231752.60633-1-adrian@mainlining.org
Signed-off-by: Casey Connolly <kcxt@postmarketos.org>
2025-10-30 11:04:51 -06:00
Danila Tikhonov 834cbecce7 clk/qcom: add driver for SM7150 GCC
Add a clock driver for the SM7150 SoC. This driver can enable necessary
clocks for UART, UFS, USB, and MMC.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Co-developed-by: Jens Reidel <adrian@mainlining.org>
Signed-off-by: Jens Reidel <adrian@mainlining.org>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250831004602.699953-2-adrian@mainlining.org
Signed-off-by: Casey Connolly <kcxt@postmarketos.org>
2025-10-29 12:27:33 +01:00
Luca Weiss 4ca964ac8c clk/stub: add sm6350-rpmh clock
Stub the RPMh clock controller on SM6350.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
2025-10-29 12:27:33 +01:00
Luca Weiss 4bae582792 clk/qcom: Add SM6350 clock driver
Add Clock driver for the GCC block found in the SM6350 SoC.

Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
2025-10-29 12:27:33 +01:00
Luca Weiss 43a2fc67d3 clk/qcom: sm8250: Remove unused defines
Clean up some defines which are not used in the driver.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250924-2025-10-misc-v1-2-7e75842ca714@fairphone.com
Signed-off-by: Casey Connolly <kcxt@postmarketos.org>
2025-10-29 12:27:33 +01:00
David Wronek 8111e1357e clk/qcom: sdm845: add support for sdm670
The global clock controller on SDM670 is similar to SDM845, so let's add
support here.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: David Wronek <david.wronek@mainlining.org>
Link: https://lore.kernel.org/r/20251003-sdm670-v2-2-52c0fa481286@mainlining.org
Signed-off-by: Casey Connolly <kcxt@postmarketos.org>
2025-10-29 12:27:32 +01:00
David Wronek 0e59113025 clk/stub: add sdm670 rpmh clock
Necessary for MMC to successfully probe all clocks.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: David Wronek <david.wronek@mainlining.org>
Link: https://lore.kernel.org/r/20251003-sdm670-v2-1-52c0fa481286@mainlining.org
Signed-off-by: Casey Connolly <kcxt@postmarketos.org>
2025-10-29 12:27:32 +01:00
Tom Rini 9ed8fafbcd Revert "clk: Return value calculated by ERR_PTR"
This reverts commit 644b4650ee.

While the intention of the above commit is correct, it leads to test
failures in CI that need to be addressed at the same time.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-28 13:27:27 -06:00
Tom Rini f30b6d12da clk: Tighten some clock driver dependencies
A few clock drivers cannot build without access to some platform
specific header files. Express those requirements in Kconfig as well.

Signed-off-by: Tom Rini <trini@konsulko.com>
2025-10-28 12:25:23 -06:00
Andrew Goodbody 644b4650ee clk: Return value calculated by ERR_PTR
In clk_set_default_get_by_id ret is passed to ERR_PTR but nothing is
done with the value that this calculates which is obviously not the
intention of the code. This is confirmed by the code around where this
function is called.
Instead return the value from ERR_PTR.

This issue found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Acked-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-10-28 10:32:59 -06:00
Tom Rini bf09c6abfc Merge patch series "clk: versaclock: Fix two issues found by Smatch"
Andrew Goodbody <andrew.goodbody@linaro.org> says:

Should return value calculated by ERR_PTR as calling code attempts to
check for it.
Also do not dereference a pointer that could be an error pointer before
checking it with IS_ERR.

Link: https://lore.kernel.org/r/20250723-clk_versaclock-v1-0-9d70f2530871@linaro.org
2025-10-28 10:32:59 -06:00
Andrew Goodbody 2a13b59ed4 clk: versaclock: Use IS_ERR check before dereference
In versaclock_probe vc5->pin_xin may be an error pointer so need to
check with IS_ERR before attempting to dereference it.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-10-28 09:48:28 -06:00
Andrew Goodbody 6f48f6f2a2 clk: versaclock: return value calculated by ERR_PTR
In versaclock_get_name -ENOMEM is passed to ERR_PTR but nothing is
done with the value that this calculates which is obviously not the
intention of the code. This is confirmed by the code around where this
function is called.
Instead return the value from ERR_PTR.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
2025-10-28 09:48:27 -06:00
Manikandan Muralidharan 7885969610 clk: at91: remove default values for PMC_PLL_ACR
Remove default values for PMC PLL Analog Control Register(ACR) as the
values are specific for each SoC and PLL, so load them from PLL
characteristics structure

Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
2025-10-17 12:33:46 +03:00
Manikandan Muralidharan 57d88e78a8 clk: at91: Add ACR in all PLL setting.
Add ACR in all PLL setting. Add correct ACR value for each PLL used in
different SoCs.

Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
2025-10-17 12:32:28 +03:00
Tom Rini 0ab7710a06 clk: sophgo: Fix a warning about void returns value
The cv1800b_clk_setfield function returns void, but was doing "return
writel(...);" and while seemingly having a void function return a void
function is not a warning, when readl is a macro this problem is shown.
Correct the code to instead simply call writel.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Yao Zi <ziyao@disroot.org>
2025-10-16 16:44:49 +08:00
Tom Rini b1cc9a53d7 Merge tag 'xilinx-for-v2026.01-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx/FPGA changes for v2026.01-rc1 v2

zynqmp:
- DT updates
- Enable new commands

mbv:
- Simplify defconfigs

clk:
- Separate legacy handler and use SMC handler

misc:
- Tighten TTC Kconfig dependency

net:
- Add 10GBE support to Gem

pwm:
- cadence-ttc: Fix array sizes

fwu:
- Add platform hook support

spi:
- Remove undocumented cdns,is-dma property

video:
- Fix DPSUB RGB handling
2025-10-14 09:48:02 -06:00
Tom Rini ecdc3872a7 Merge patch series "firmware: scmi: various update"
Peng Fan (OSS) <peng.fan@oss.nxp.com> says:

Misc update on firmware scmi:
 - Typo fix
 - Use io helpers
 - Use PAGE_SIZE for arm64
 - Add IN_USE error code
 - Add more error info
 - Support scmi max rx timeout in mailbox
 - Add myself as scmi maintainer, AKASHI contributed most code, but
   seems he is not invovled in the developement anymore, I volunteer to
   help here.

Some items on list that I am thinking to add:
- align with linux kernel to use cpu_to_le32 and le32_to_cpu, but have not find
  a good way to use the helpers.
- Add SCMI version negotiation as Linux Kernel

Link: https://lore.kernel.org/r/20250927-scmi-v1-0-5e9354fb3bff@nxp.com
2025-10-09 14:30:02 -06:00
Peng Fan 0d71bc3a1b clk: scmi: Replace log_debug with dev_dbg
Use dev_dbg to dump device name, dev_dbg also a encapsulation call
to log() and print(). So it is ok to use dev_dbg.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-10-09 14:16:11 -06:00
Naman Trivedi 4146a31dce drivers: firmware: update xilinx_pm_request to support max payload
Currently xilinx_pm_request API supports four u32 payloads. However the
legacy SMC format supports five u32 request payloads and extended SMC
format supports six u32 request payloads. Add support for the same in
xilinx_pm_request API. Also add two dummy arguments to all the callers
of xilinx_pm_request.

The TF-A always fills seven u32 return payload so add support
for the same in xilinx_pm_request API.

Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Acked-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/5ae6b560741f3ca8b89059c4ebb87acf75b4718e.1756388537.git.michal.simek@amd.com
2025-10-09 09:07:03 +02:00
Michal Simek e7fe2c7bc6 clk: xilinx: Separate legacy format to own handler
It is a preparation for adding enhacement format support that's why there
is a need to separate current support to own function.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c4d546553d4f0d69ef75fb1132b7121f36dd306c.1756388537.git.michal.simek@amd.com
2025-10-09 09:07:03 +02:00
Michal Simek f791695685 clk: xilinx: Call generic smc_call_handler()
There is no reason to call SMC from clock driver directly when clock driver
is a child of firmware driver which is providing it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d383d5fea680b33d2eddbca108c452cee97e98ea.1756388537.git.michal.simek@amd.com
2025-10-09 09:07:03 +02:00
Tom Rini 0eaa4b3373 Merge branch 'next'
Merge the outstanding changes from the 'next' branch to master.
2025-10-06 13:20:24 -06:00